KR950003602B1 - Video signal processing device and method of radar - Google Patents

Abstract

The apparatus includes; a digitizer means for stroing the disital signals converted from the analog video signals in the memory; a constant false alarm rate(CFAR) processing means for detecting the pure target signals with the inner algorithm for removing clutter, noise and interference by receiving the output signal from the digitizer means; and a video data and pixel timing control means for synchronizing the video data and pixel by successively outputting the target input signals of the CFAR processing means in accordance with the pixel timing.

Description

Radar device video signal processing device and method

1 is a block diagram showing the configuration of a general radar device to which both the prior art and the present invention can be applied.

2 is a detailed block diagram of the video processor of FIG.

3 is a block diagram of a video signal processing apparatus of a conventional radar apparatus.

4 is a block diagram showing a video signal main processor of the radar apparatus according to the present invention.

FIG. 5 is a detailed block diagram showing the digitizer of FIG. 4 in more detail.

6 is a detailed block diagram showing the CFAR processor of FIG. 4 in more detail.

FIG. 7 is a detailed block diagram illustrating the buffer and pixel timing controller of FIG. 4 in more detail.

FIG. 8A is a block diagram showing an example of implementing the interference avoidance of FIG. 7 in a threshold decoder.

FIG. 9A illustrates an example in which a round plan position indicator is formed on a rectangular screen.

9B shows an example of the number of pixels that change according to an angle on the screen.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing technology of a radar, and more particularly, to a video signal processing apparatus and a method for removing various clutters and noises included in a video signal of a radar and extracting a target signal.

The radar can be classified into pulse radar, continuous wave (hereinafter referred to as CW), radar, frequency modulated radar, and phase modulated radar, depending on the purpose. A block diagram of a general radar used for the purpose is shown in FIG. The pulse modulator 1 generates a repeating pulse train and the transmitter 11 amplifies the signal with high power according to a train of pulses signal and transmits the signal to the antenna 14. The duplexer 12 separates transmission and reception so that one antenna 14 can be shared in transmission and reception. The antenna 14 emits pulses into a space and targets, surface, sea surface, rain, Receive echoes reflected from clouds, fog, etc. The positional coordinates of the antenna 14 are controlled by a positioner 13 connected between the display 13 and the controller 13 and the mechanical 13 driving the antenna 14, such that the azimuth angle on the display and the antenna ( 14) is synchronized. The echo signal received by the antenna 14 is input to the low noise radio frequency (hereinafter referred to as RF) amplifier 15 via the duplexer 12. The low noise RF amplifier 15 amplifies the received signal while suppressing noise. The mixer 16 mixes the local oscillation signal from the local oscillator 17 and the received input RF signal to produce an intermediate frequency signal (hereinafter referred to as IF below intermediate frequency) of 30 MHz to 120 MHz. The intermediate frequency amplifier (IF AMP: 18) is a type of matched filter that amplifies while improving the signal-to-noise (S / N) ratio. Detector 19 detects the video signal at the received IF. The detected video signal contains a signal reflected on the target, noise and clutter. The video signal processor 20 removes unnecessary noise or clutter deemed unnecessary in relation to the radar operation purpose at the time and extracts and displays a pure target signal. The display and controller 21 show the target captured by the radar on a display and display information about the target. There is also an adjuster to select clutter algorithms, allowing the user to manipulate the screen state.

FIG. 2 shows the video signal processor 20 in more detail. The clutter controller 23 removes clutter from the received echo signal and the video extracting the target signal while reducing the extraction level of various noise signals below a certain level. Signal main processor 24 is shown. In the video signal main processor, a constant false alarm rate (CFAR) processing is used to detect pure target signals.

3 is a block diagram of a conventional video signal processing technique. The conventional CFAR (Constant False Alarm Rate) processing method stores a video data, compares a plurality of pulse repetition time (hereinafter referred to as PRT) data, and detects only a relatively large target signal. One such approach is known from US Pat. No. 4,845,500 (Jul. 4, 1989). According to this method, as shown in FIG. 3, the video processor 30 includes a digitizer 32, an averager 33, and a video storage 34, and the digitizer 32 is sampled. According to the sampling rate, an analog radar received signal is converted into a digital word and outputted. The averager 33 adjusts an appropriate size according to the target size. The average of the digital words is then stored in the video storage 34. The averager 33 is also synchronized with the trigger signal and the antenna position coordinates. In this case, the window size is determined by the number of azimuth secotrs and range bins. The number of azimuth sectors is generated by the target size / position device 37 and input to the video storage 34. The number of range bins is determined by the start / stop signal, and the number of range bins is generated by the range start circuit 39 and input according to the range start / stop signal input to the averaging device 33. Is determined. In this way, the tracking processor 31 adjusts the window size to have an appropriate number of range bins and azimuth sectors according to the size of the target. In FIG. 3, the tracking processor 31 includes a noise reducer 35, a target detector 36, a target size and position circuit 37 And a speed and heading circuit 38 and a range start circuit 39 to track the movement of the target. Such a conventional technique does not sufficiently satisfy the video signal processing algorithm, and thus it is difficult to maintain a constant level of noise level, thereby degrading pure target detection ability and displaying a false target. In addition, the video signal processing apparatus according to the conventional technique operates in conjunction with a tracking processor, and thus cannot be used for surface mapping or weather observation, and can be used only in a radar having a tracking processor.

Accordingly, it is an object of the present invention to provide a video signal processing apparatus of a radar device which increases the ability to detect or capture a target by appropriately removing various clutters and noises distributed in the radar received signal.

Another object of the present invention is to provide a video signal processing method of a radar device.

The above-described video signal processing apparatus of a laser device for achieving the present invention comprises a digitizer means for converting an analog video signal into a digital video signal, a clutter, a noise and an interference after inputting the digital video signal of the digitizer means. A CFAR processing means for detecting a target signal with a built-in algorithm for removing the signal; a buffer and pixel timing control means for synchronizing the video data with the pixel by inputting the target signal of the CFAR processing means and outputting them in order according to the pixel timing; Characterized in that provided.

In addition, the video signal processing method of the radar apparatus for achieving the above object of the present invention comprises the steps of converting an analog video signal into a digital video signal, according to a feedback algorithm preset in accordance with the state of the PRF, clutter and noise Summing the feedback data and the current PRT data, storing the summing result, leveling and outputting video data according to the states of the PRF, clutter, and noise; And converting the output into a display display signal.

Next will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a video signal processing apparatus according to the present invention, which is composed of a digitizer 40, a CFAR processor 50, a buffer, and a pixel timing controller 60. As shown in FIG. The radar received signal is first input to the digitizer 40 after the clutter is first attenuated by the clutter remover 23 shown in FIG. The digitizer 40 converts an analog video signal into a digital video signal and stores it in an internal memory so that digital signal processing can be performed. The output signal of the digitizer 40 is supplied to the CFAR processor 50 to remove noise and clutter of the received signal and to detect a pure target. The CFAR processor 50 detects the target signal while maintaining a constant alarm rate by removing clutter and noise included in the digital video signal. Meanwhile, the output signal of the digitizer 40 may be directly supplied to the buffer and pixel timing controller 60 for raw video processing, which is displayed without removing noise or clutter of the radar received signal. The buffer and pixel timing controller 60 outputs a target signal input from the CFAR processor 50 or a digital signal input from the digitizer 40 in order according to pixel timing, thereby tracking a processor (not shown) and a display device (not shown). ), A video memory (not shown), and the like, and generate various timing signals for display. As described above, the video signal processing apparatus 24 according to the present invention, together with the clutter remover 23 shown in FIG. 2 in the navigation radar, performs noise removal, unnecessary clutter attenuation, CFAR function, etc. as an important signal processing system. Perform signal processing for

FIG. 5 is a block diagram showing the digitizer 40 in FIG. 4 in more detail, and includes an A / D converter 41, a video distributor 42, and a video buffer memory 43. As shown in FIG. The analog video signal (Analog Video Signal) is sampled according to the clock in the analog digital converter (A / D Converter) 41 and then converted into a digital video signal. The digital video signal is input to the video distributor 42, classified according to the PRT, and stored in the video buffer memory 43. The sampling clock 100 of the A / D converter 41 is determined according to the resolution, pulse width, range, and pulse repetition frequency (PRF), and divides and uses the base clock. The number of digital bits per range cell ranges from 2 to 12 bits, which is variable depending on the radar's purpose and specifications, but 2-8 bits is sufficient for navigation purposes. The video buffer memory 43 is composed of two or more memory groups. When the first buffer 44 stores data for 1 PRT, the second buffer 45 releases previously stored PRT data, and when the buffer is extended to n, the data can be stored up to n PRT data. You can separate read and write operations.

FIG. 6 is a block diagram illustrating the CFAR processor of FIG. 4 in more detail. The summer 51, the main memory 52, the threshold decoder 53, the feedback integral memory device 54, and the interference eliminator 56 are shown in FIG. It consists of. CFAR treatment is to keep the probability of the target or noise appearing below a certain level, thereby suppressing the display of the target and possibly improving the signal-to-noise ratio. The functions achieved in the CFAR processing are similar to each radar, but the algorithms for implementing them vary widely depending on the type of radar and the distribution of clutter or noise present in the reflected signal. The determinants of such CFAR processing algorithms are the false alarm probability (Pfa), the detection probability (Pd), the number of integration pulses, the number of range bins, and the threshold level ( T: Threshold Level) and S / N ratio. Typical navigable occurrence rate

Where Ntot is the total number of range bins.

In FIG. 6, video input data is supplied to summer 51 for feedback back integration and accumulation. Another input of summer 51 is the data of the PRT that has already been stored by the number of integration pulses and fed back, and the video data continues by multiplying the number of integration pulses with the number of A / D conversion bits. Accumulated data. Here, the number of integration pulses (M) is the number of pulses accumulated in the beam azimuth θa, that is, in one sweep ling, and is generally calculated by the following formula.

Here, θa is the beam azimuth (unit: radian), θRPM is the rotation angle per minute of the antenna, RPF is the number of transmission pulses for 1 second, and PRT is the pulse period. PRFs are typically between 5 and 150 in common navigation radars. The summer 51 adds the current PRT data and the feedback PRT data and stores them in the main memory 52. The main memory 52 has a capacity determined according to the number of integration pulses, 1 PRT period, the number of lazy cells, the resolution of the sampling clock (A / D Samplin Clock) and the indicator (distply), and stores the summed data. The feedback integrating memory device 54 processes the data of the main memory 52 according to the feedback coefficient selected by the PRF signal 110 and then returns to the summer 51. In this case, the feedback coefficient is less than 1, and its value varies depending on the RF. When information on PRF is provided from the outside, the feedback factor in the feedback Vack Integration Memory 54 corresponds to the video. Extract the data. The algorithm result of the feedback back integration (feed back factor or feed back integration constant) can be calculated by the following equation.

Kopt = e-1.17 / M

Here, Kopt is a feedback factor (feed back factor), M is the number of integration pulses, and the relationship between them is shown in Table <1>.

TABLE 1

In Table 1, it can be seen that the feedback coefficient Kopt increases as the number of integration pulses increases, and Kopt (%) expresses the feedback coefficient as a percentage. Here, the S / N ratio (unit: dB) represents the degree to which the CFAR gain, that is, the S / N ratio, is improved according to the number of integration pulses. In addition, CFAR loss (in dB) determined according to the number of integration pulses and the number of totalizer output bits 120 is shown in Table 2.

TABLE 2

In Table 2, the CFAR loss (unit: dB) is shown when the quantile occurrence probability (Pfa) is 10-6 and the detection probability (Pd) is 0.95. The number of integration pulses increases and It can be seen that the loss decreases as the number increases. In addition, when comparing the S / N ratios of Tables <1> and <2>, it can be seen that as the number of integration pulses increases, the gain of CFAR increases sharply rather than the loss of CFAR.

The video data summed up according to the feedback factor (F / B Factor) is represented by the summation signal component as follows.

The video data passed through the summer 51 (V _u T _n ) refers to the digital video data stored by summing up to ViTn among the digital video data having an F / B factor of N. The video data is a threshold decoder ( In the Threshold Decoder (53), leveling is performed for each PRF according to a log functional equalization method. That is, the output of the threshold decoder 53 grasps the number of hits (the signal exists in the same range: hit) for each range cell in the PRT data as many as the number of integration pulses, and stepwise according to the threshold level of the algorithm already set. Is determined. An example of the algorithm constituting this threshold level is shown in Table < 3 &gt;.

TABLE 3

(Output bit: 2 bit)

In Table 3, when the output of the threshold decoder is 2 bits, if the number of integration pulses is 32, the output of the threshold decoder is 11 when any range cell is hit 17 times, and when it is hit 9 times, the output is 10 and 5 times. If you hit 01, 3 times, you will see 00. This leveling algorithm generally divides logarithmically evenly, which is variously implemented according to the PRF, the distribution characteristics of the clutter and the noise state. The threshold decoder 53 retains this algorithm in an internal memory and selects an appropriate algorithm by the PRF signal 110 supplied from the outside. This processing method improves the signal-to-noise (S / N) ratio by reducing random noise or falsity alarms. The interference elimination function is basically executed in the interference eliminator 56 by comparing two consecutive PRTs, and may be output directly from the threshold decoder 53 so as not to execute the interference elimination function if necessary. . In other words, the interference eliminator 56 compares the PRT (N) data with the PRT (N-1) data that is 1 PRT ahead of each other and breaks whether the video signal is changed or not, and then removes the sudden change such as the interference resistance component. The signal component having suppresses passage. In addition, there are two kinds of the interference eliminator 56 which basically uses a part of video integration and compares and outputs the output data of two consecutive PRTs which have been decoded. 8A and 8B illustrate these two methods, and FIG. 8A implements a function of adjusting an interference level for removing interference in the decoder 53 & 56, and the interference signal 141 Choose your step accordingly. In FIG. 8B, a comparator 58 and a delayer 57 are disposed at the rear end of the threshold decoder to remove the interference. In addition, the interference function may be turned on or off as necessary according to the signal 140 for turning on / off the interference function. Here, interference refers to a very strong interference signal received from other radars having the same or adjacent frequency.

FIG. 7 is a block diagram showing the buffer and pixel timing controller of FIG. 4 in more detail. The video data rate controller 61, the output buffer 62, and the timing controller 63 are shown in FIG. In implementing the video data signal processing and input / output interfaces, the data processing speed should basically be closely synchronized with the pixel timing. Unlike the conventional analog display method, the raster scan display method requires a large amount of digital video data corresponding to individual pixels, so the video data processing speed must be matched with the pixel timing. In addition, because the pixels increase or decrease depending on the resolution and angle of the display, the pixel timing cannot be realized with a certain form of continuity clock. This increase and decrease of the pixels causes the pixel timing and the video data processing speed to coincide with each other, so that distance and orientation errors can be reduced only when mutual synchronization is achieved. Therefore, pixel timing control and video data transmission are closely related. Referring to the form of the screen, an example of configuring a round plane position indicator of 960 × 960 pixels in a rectangular screen of 1024 × 1024 pixels is illustrated in FIG. 9A. FIG. 9B shows that the number of pixels of the 960 × 960 round yellow plane changes with angle. In FIG. 9A, a rectangular screen with 1024 × 1024 pixel resolution constitutes a 960 × 960 pixel round PPI for video display, and the round screen is 90 °, 180 °, 270 ° corresponding to the Cartesian coordinate axis. We can see that at 360 °, it is 480 pixels per radius. In FIG. 9B, since the pixel has a rectangular shape, the pixel on the Cartesian coordinate axis is composed of 480 pixels, but the number of pixels changes as the angle is changed. At approximately 45 °, 135 °, 225 °, and 315 °, the number of pixels becomes the minimum, and the number of pixels is about 340, which is 480 × COS45 °. In FIG. 7, the video data rate controller Reference numeral 61 synchronizes the digital video input signal from which noise and clutter are removed with the pixels of the display according to the control signal of the timing controller 63. The timing controller 63 generates a control signal for synchronizing the speed of the pixel and the video data according to the pixel control signal 130 changed by the increase or decrease of the pixel, and provides the generated control signal to the video data rate controller 61. The output buffer 62 outputs an input video signal to a device requiring CFAR processing and a completed video signal, that is, a tracking processor (not shown), a display (not shown), a video memory (not shown), and the like.

As described above, the present invention efficiently detects a target through CFAR processing that appropriately attenuates clutter and noise levels in a radar video signal, and prevents display of a fake target. In addition, the ability to detect targets by using dedicated memory for feedback integration and threshold decoding has been improved, and it is possible to perform high-speed processing and miniaturization by applying digital signal processing technique. It can also be applied to color video signal processing of marine navigation, coastal surveillance, marine control, meteorological observation, and mapping radar.

Claims (6)

Digitizer means for converting an analog video signal into digital and storing it in a memory; CFAR processing means for receiving the output signal from the digitizer and detecting a pure target signal by incorporating an algorithm for removing clutter, noise, and interference; And a buffer and pixel timing control means for inputting the target signal of the CFAR processing means and sequentially outputting the target signal according to the pixel timing to synchronize the video data with the pixel. The digital divider of claim 1, wherein the digitizer comprises at least one of an analog / digital converter for converting an analog signal into a digital signal, a video distributor for inputting and distributing a digital video signal from the analog / digital converter, and a digital video signal distributed from the video distributor. And a video buffer memory for alternately storing in two or more buffers. The apparatus of claim 1, wherein the CFAR processing unit comprises: an adder for accumulating current PRT data inputted from the digitizer means and previous PRT data inputted first and then feedback; and a main memory for storing the accumulated result from the adder; And a threshold decoder for inputting previous data from the main memory and feedback according to a feedback algorithm, and a threshold decoder for inputting video data from the main memory and leveling the video data according to a threshold level algorithm. The video data rate controller of claim 1, wherein the buffer and pixel timing control means inputs a display signal detected by the CFAR processor to adjust an output speed of video data according to a control clock for display. An output buffer means for inputting the output of the output to the outside and a timing controller for providing a signal for synchronizing the pixel with the video data by inputting a signal having data relating to the number of pixels from the outside to the video data rate controller; A video signal processing apparatus of a radar device. Converting the analog video signal into a digital video signal; Summing data fed back and current PRT data according to a feedback algorithm set in advance according to PRF, clutter, and noise conditions; Storing the sum result; Leveling and outputting video data according to a threshold level algorithm preset according to states of PRF, clutter and noise; And converting the leveled video output into a display display signal. 4. The video signal processing apparatus of claim 3, further comprising an interference eliminator for removing an interference present in the video signal.