JPH04317371A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE:To easily manufacture a semiconductor memory high in integration. CONSTITUTION:The BPSG film 36 and the SiO2 film 17 on the N<-> diffused layer of a memory cell part 24 are anisotropically etched to form a sidewall consisting of these film at the side of a polycide film 16, and then the BPSG film 36 is let flow. Therefore, a contact hole 15a is never buried with the BPSG film 36 after flow, and in other areas, the step part is flattened by the BPSG film 36.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a DRAM, particularly a semiconductor memory called a stacked capacitor DRAM.

0002

2. Description of the Related Art FIG. 7 shows a stacked capacitor type DRAM in the manufacturing process according to a conventional example of the present invention. A DRAM memory cell is composed of a transistor 11 and a capacitor 12, and is a stacked capacitor type DRA.
In M, one N- diffusion layer 13a of the transistor 11
and a polycrystalline Si film 14 which is a storage node of the capacitor 12.
are in contact with each other through the contact hole 15a.

In such a DRAM, the transistor 11
The memory cell area can be reduced by a self-aligned contact structure in which a sidewall made of SiO2 film 17 is formed on the side of the polycide film 16, which is a gate wiring, that is, a word line, and at the same time, a contact hole 15a is formed in a self-aligned manner. ing.

0004

However, in the self-aligned contact structure, the polycide film 16 and the polycrystalline Si film 1
4, it is necessary to provide an offset SiO2 film 21 on the polycide film 16.

For this reason, when attempting to pattern the polycrystalline Si film 14, which has a large step difference in the underlying layer and is made thicker in order to increase the memory cell capacity, so-called stringers 14a remaining after etching are removed. This tends to occur at the step portion between the polycide films 16. As a result, there is a possibility that the polycrystalline Si films 14 of adjacent memory cells may be short-circuited via this stringer 14a.

On the other hand, as a method to prevent this, as shown in FIG. 8, it is possible to planarize the base of the polycrystalline Si film 14 by flowing a low melting point glass film such as a BPSG film 22.

However, this time, the polycrystalline Si film 14 and N-
The contact portion with the diffusion layer 13a is also flattened. As a result, even if the entire surface of the BPSG film 22 after the flow shown by the dashed line is etched back, the BPSG film 22 shown by the solid line
In particular, it becomes difficult to form the contact hole 15a in a self-aligned manner.

In other words, in any of the above-mentioned conventional examples, it is difficult to achieve both self-alignment contact and thickening of the polycrystalline Si film 14 serving as the storage node. Therefore, it is difficult to ensure a large memory cell capacity with a small memory cell area, and it has been impossible to manufacture a highly integrated DRAM.

[0009]

[Means for Solving the Problems] A method for manufacturing a semiconductor memory according to the present invention includes a step of forming a wiring 16 between a memory cell section 24 and a peripheral circuit section 25, and a step of forming a wiring 16 between the entire surface of the memory cell section 24 and the peripheral circuit section. Step 25 of forming a silicon oxide film 17 on the sides of the wiring 16; and after forming the silicon oxide film 17, forming a low melting point glass film 36 on the entire surface of the memory cell section 24 and the peripheral circuit section 25. process, and the low melting point glass film 3 at the contact portion between the storage node 14 of the capacitor 12 and the transistor 11.
6 and the silicon oxide film 17 are selectively anisotropically etched, so that the silicon oxide film 17 and the low melting point glass film 36 are etched only on the sides of the wiring 16 in the contact portion.
and a step of causing the low melting point glass film 36 to flow after the anisotropic etching.

0010

[Operation] In the semiconductor memory manufacturing method according to the present invention, before flowing the low melting point glass film 36, the capacitor 12 is
The low melting point glass film 36 and silicon oxide film 17 in the contact area for the storage node 14 are selectively anisotropically etched, and at the time of anisotropic etching, the film thickness of the low melting point glass film 36 in the contact area is reduced. is not thick. Therefore, in the contact portion for the storage node 14, by leaving the silicon oxide film 17 and the low melting point glass film 36 only on the sides of the wiring 16, the contact hole 15a for the storage node 14 can be formed in a self-aligned and stable manner. can do.

Moreover, the storage node 14 of the capacitor 12
In the contact area for the semiconductor device, the low melting point glass film 36 is left only on the sides of the wiring 16, but in other areas, the low melting point glass film 36 is left on the entire surface. Therefore, other regions can be flattened with the low melting point glass film 36 without filling the contact hole 15a for the storage node 14 formed in a self-aligned manner with the low melting point glass film 36 after flowing. Therefore, patterning of the storage node 14 is easy;
The film thickness of the storage node 14 can be increased.

On the other hand, in the peripheral circuit section 25, the side walls of the wiring 16 are formed only with the silicon oxide film 17, and in the contact section for the storage node 14 of the capacitor 12, the silicon oxide film 1
7 and the low melting point glass film 36 form the side walls of the wiring 16, so that the film thicknesses of these side walls are made different from each other. Therefore, when leaving the low melting point glass film 36 only on the sides of the wiring 16 in the contact portion for the storage node 14, there is no need for an additional process compared to the conventional method.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to the manufacture of a stacked capacitor type DRAM will be described below with reference to FIGS. 1 to 6.

In this embodiment, as shown in FIG. 1, a SiO2 film 26 is formed in the element isolation regions of both the memory cell section 24 and the peripheral circuit section 25 of the Si substrate 23 by the LOCOS method, and the active region 27 is SiO which is a gate oxide film on the surface
2. Form the film 31. Then, a polycide film 16 and an offset SiO2 film 21 are successively deposited over the entire surface by CVD.

Thereafter, the SiO2 film 21 and the polycide film 16 are simultaneously patterned to form word lines, and using the word lines and the SiO2 film 26 as masks, N-
Impurity 32 for forming a diffusion layer is ion-implanted into the active region 27.

Next, as shown in FIG. 2, a SiO2 film 17 is deposited to a thickness of approximately 1000 to 3000 Å by CVD, and only the memory cell portion 24 is covered with a resist 33. Note that instead of the SiO2 film 17, a PSG film or a two-layer film of a PSG film and a SiO2 film may be used.

Thereafter, by etching back only the SiO2 film 17 of the peripheral circuit section 25 using the resist 33 as a mask, side walls made of the SiO2 film 17 are formed on the sides of the polycide film 16 and the SiO2 film 21 of the peripheral circuit section 25. Form.

After removing the resist 33, a resist (not shown) is patterned to expose only the N-channel transistor region of the peripheral circuit section 25, and the resist, polycide film 16, SiO2 film 21, and S
Using the iO2 film 26 as a mask, impurities (not shown) for forming an N+ diffusion layer are ion-implanted into the active region 27.

Furthermore, a resist (not shown) is patterned to expose only the P channel transistor region of the peripheral circuit section 25, and in the same way, impurities (not shown) for forming a P+ diffusion layer are activated. Ions are implanted into region 27.

Next, heat treatment is performed, as shown in FIG.
At the same time as the N- diffusion layers 13a and 13b are formed in the memory cell section 24, the N- diffusion layers 34a and 13b are formed in the peripheral circuit section 25.
34b, N+ diffusion layers 35a and 35b, and P+ diffusion layers (not shown) are formed.

[0021] Then, the BPSG film 36 is formed by the CVD method.
is deposited to a thickness of about 1000 to 2000 Å, and a resist 37 having an opening 37a as shown in FIG. 6 is patterned on the BPSG film .

After that, using the resist 37 as a mask, BP
The SG film 36 and the SiO2 film 17 are anisotropically etched, and the SiO2 film 17 and BP are etched on the sides of the polycide film 16 and the SiO2 film 21 on the N- diffusion layer 13a.
A side wall made of the SG film 36 is formed.

At this time, at the same time as the sidewalls made of the SiO2 film 17 and the BPSG film 31 are formed, the N- diffusion layer 13a is formed.
The surface of the contact hole 15a is exposed and a contact hole 15a is formed in a self-aligned manner.

Note that the sidewalls of the polycide film 16 and the SiO2 film 21 are the same as the SiO2 film 17 in the memory cell section 24.
The peripheral circuit section 25 consists of only the SiO2 film 17 and is thin, whereas the peripheral circuit section 25 consists of only the SiO2 film 17 and is thin.

This is because in the memory cell section 24, the contact hole 15a is formed in a self-aligned manner, so it is necessary to ensure sufficient interlayer breakdown voltage by the sidewalls, whereas in the periphery, the contact hole 15a is not formed in a self-aligned manner. This is because if the side wall thickness of the circuit portion 25 is too thick, the N- diffusion layers 34a and 34b will become too wide, and the performance of the transistor will deteriorate. Therefore, taking this into consideration, the SiO2 film 17 and BP
The respective film thicknesses of the SG film 36 are set as described above.

Thereafter, heat treatment is performed at a temperature of about 800 to 900° C. to cause the BPSG film 36 to flow. As a result, the step portion is flattened in regions other than the region above the N- diffusion layer 13a, particularly in the regions 41 and 42 where the interval between the polycide films 16 is narrow and stringers are likely to occur. However, N-
Since the BPSG film 36 remains only as part of the sidewall on the diffusion layer 13a, the contact hole 15a is not filled with the flowed BPSG film 36.

Next, as shown in FIG. 4, an interlayer insulating film 43, which is a single-layer film of only an SiO2 film or a two-layer film of a PSG film and a SiN film, is deposited over the entire surface. Then, using a resist mask (not shown), a contact hole 44 is opened only in a portion of the interlayer insulating film 43 above the N- diffusion layer 13a, and the contact hole 15a is opened again in a self-aligned manner. do.

Note that the interlayer insulating film 43 is used for N-
This is to increase the thickness of the interlayer insulating film in areas other than the area above the diffusion layer 13a. Therefore, if these are not necessary, the interlayer insulating film 43 is not necessarily necessary.

In this state, polycrystalline Si is grown by CVD method.
A film 14 is deposited, and this polycrystalline Si film 14 is filled with N such as phosphorus.
After doping type impurities at a high concentration, the polycrystalline Si film 14
is processed into a pattern of memory nodes.

Next, as shown in FIG. 5, the SiO2 film and S
A capacitor insulating film is formed by an ONO film 45, which is a three-layer film of an iN film and a SiO2 film, and a plate electrode is formed by a polycrystalline Si film 46 doped with impurities. Then, planarization is performed with an interlayer insulating film 47 such as a BPSG film, and a contact hole 15b reaching the N- diffusion layer 13b is formed in the interlayer insulating film 47 or the like.

Thereafter, bit lines are formed using the polycide film 48 to complete the stacked capacitor type DRAM. Note that a high melting point metal film or the like may be used instead of the polycide film 48.

In this embodiment as described above, although the contact hole 15a for the polycrystalline Si film 14 serving as a storage node is formed in a self-aligned manner, the difference in level between the regions 41 and 42 where stringers are likely to occur The area is flattened. Therefore, even if the thickness of the polycrystalline Si film 14 is increased, it can be patterned, and the surface area of the storage node can be increased to increase the memory cell capacity.

[0033]

Effects of the Invention In the semiconductor memory manufacturing method of the present invention, contact holes for storage nodes can be formed in a self-aligned and stable manner, so the memory cell area can be reduced. First, since the film thickness of the storage node can be increased, the memory cell capacity can be increased, and since no additional steps are required compared to the conventional method, the process does not become complicated. Therefore,
A highly integrated semiconductor memory can be easily manufactured.

[Brief explanation of drawings]

FIG. 1 is a side sectional view showing a part of an embodiment of the present invention.

FIG. 2 is a side sectional view showing a step following FIG. 1;

FIG. 3 is a side sectional view showing a step following FIG. 2;

FIG. 4 is a side sectional view showing a step following FIG. 3;

FIG. 5 is a side sectional view showing a step following FIG. 4;

FIG. 6 is a plan view showing one embodiment.

FIG. 7 is a side sectional view showing a conventional example of the present invention.

FIG. 8 is a side sectional view showing another conventional example of the present invention.

[Explanation of symbols]

11 Transistor 12 Capacitor 14 Polycrystalline Si film 15a Contact hole 16 Polycide film 17 SiO2 film 24 Memory cell section 25 Peripheral circuit section 36 BPSG film

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor memory having a memory cell section and a peripheral circuit section, in which a memory cell is constituted by a transistor and a capacitor, wherein wiring is provided between the memory cell section and the peripheral circuit section. a step of forming a silicon oxide film on the entire surface of the memory cell portion and a side portion of the wiring in the peripheral circuit portion; forming a low melting point glass film on the entire surface of the capacitor, and selectively anisotropically etching the low melting point glass film and the silicon oxide film at the contact portion between the storage node of the capacitor and the transistor, The method for manufacturing a semiconductor memory includes the steps of: leaving the silicon oxide film and the low melting point glass film only on the sides of the wiring; and flowing the low melting point glass film after the anisotropic etching.