JPH04315381A - Fixed pattern noise suppression system - Google Patents

Abstract

PURPOSE:To provide the system in which a signal is processed with high accuracy without reducing the dynamic range in the FPN suppression system used to suppress the FPN from an image pickup signal of a solid-state image pickup device. CONSTITUTION:The FPN suppression system consists of a 1st step A/D- converting a dark state signal and storing the result, a 2nd step in which an A/D-converted memory storage signal is subtracted from the dark state signal and the result is multiplied by a factor of K, a 3rd step in which a residual FNP is multiplied by K and A/D-converted, the result is added to the one obtd. by multiplying a memory storage signal by K and the result is stored again in the memory 10, a 4th step in which the FPN stored in the memory 10 is multiplied with 1/K and the result is D/A-converted, and a 5th step in which the light shield is released, and the FPN subjected to D/A-conversion in the 4th step is subtracted from the image pickup signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fixed pattern noise suppression method for suppressing, with high precision, fixed pattern noise inherent in a solid-state imaging device such as an amplified image sensor.

0002

2. Description of the Related Art In general, a dark signal from an amplified image pickup device includes fixed pattern noise (hereinafter abbreviated as FPN) unique to the device. It is superimposed on the image signal in an offset manner, impairing the image quality. Conventionally, as a suppression method for removing such dark FPN, the following FPN suppression circuit has been used. That is, as shown in FIG. 5, the dark signal from the image sensor 101 that is shielded from light is A/D converted by the A/D converter 102 and recorded in advance in the memory 103, and then the dark signal from the image sensor 101 that is shielded from light is recorded in the memory 103. The image signal from the A/D converter 10
2, A/D conversion is performed and the image signal is sent to the memory 103.
A subtracter 104 subtracts the dark signal recorded on the F, and the output of the subtracter 104 is D/A converted by a D/A converter 105 and then input to a monitor 106.
There is a PN suppression circuit. This FPN suppression circuit is called a digital subtraction FPN suppression method in which dark FPN is subtracted using a digital circuit.

On the other hand, an FPN suppression circuit shown in FIG. 6 is also known. This FPN suppression circuit, like the one shown in FIG.
Record it in Next, the image sensor 101 with the light shielding removed
The dark signal recorded in the memory 103 is D/A converted by a D/A converter 105 and subtracted by a subtracter 104, and the output of the subtracter 104 is inputted to a monitor 106. This method is called an analog subtraction FPN suppression method because it uses an analog circuit to subtract and remove the dark FPN.

0004

[Problems to be Solved by the Invention] By the way, the digital subtraction FPN suppression method shown in FIG. The disadvantage is that the range is narrow and an attempt to widen the dynamic range requires a multi-bit expensive A/D converter. On the other hand, the analog subtraction FPN suppression method shown in Fig. 6 does not perform A/D conversion on bright imaging signals, so the dynamic range is wide; This method has the disadvantage that the subtraction accuracy decreases due to errors in accuracy.

The present invention was made to solve the above-mentioned problems in conventional FPN suppression circuits, and an object of the present invention is to provide an FPN suppression device having a wide dynamic range and high subtraction accuracy.

[0006]

[Means and operations for solving the problems] In order to solve the above problems, the present invention reads out a dark signal of an image sensor in a light-shielded state, converts it into an A/D, stores it in a memory, and reads it out from the image sensor. In the FPN suppression method of suppressing FPN by D/A converting and subtracting the dark signal stored in the memory from the image pickup signal, a first step of A/D converting the dark signal of the image sensor and storing it in the memory; , a second step of D/A converting and subtracting the dark signal accumulated in the memory from the dark signal of the image sensor, and multiplying the obtained residual FPN by K (K>1); A/D converting the FPN, adding this and the dark signal accumulated in the memory in the first step by multiplying by K, and storing the addition result in the memory again; a fourth step in which the residual FPN accumulated in the image sensor is multiplied by 1/K and subjected to D/A conversion; and a fifth step in which light shielding is removed and the residual FPN subjected to the D/A conversion in the fourth step is subtracted from the image signal of the image sensor. It consists of:

In the first step of the FPN suppression method configured as described above, the memory stores the FPN of the image sensor.
and the residual F due to the quantization error and linearity error of the A/D converter.
PN is accumulated. Then, in the second step, K
A multiplied residual FPN is generated. In the third step, the residual FPN multiplied by K is A/D converted, and the FPN stored in the memory is multiplied by K and added to the FPN of the image sensor multiplied by K. A residual FPN resulting from the second A/D conversion is generated and stored in memory. Next, in the fourth step, the third
Multiply the FPN of the memory accumulated in the step by 1/K and D
By performing the /A conversion, a residual FPN resulting from the second A/D conversion, which is multiplied by 1/K with the FPN of the image sensor, is generated. Next, in the fifth step, the FPN generated in the fourth step is calculated from the image signal of the image sensor whose light shielding is released.
is subtracted, and the signal component and the residual FPN multiplied by 1/K are output. Therefore, FPN can be suppressed with high accuracy without reducing the dynamic range.

[0008]

[Example] Next, an example will be explained. FIG. 1 shows an FPN suppression method for explaining an embodiment of the FPN suppression method according to the present invention.
FIG. 2 is a block configuration diagram of a PN suppression device. In Figure 1,
1 is an image sensor, 2 is a sample and hold circuit (hereinafter referred to as S/H)
3 is a subtracter that subtracts the signal inputted via the S/H circuit 14 from the dark signal or the imaging signal of the image sensor 1 via the S/H circuit 2; The output is input to the multiplier 4, and is also input to the subsequent signal processing circuit as the output of the FPN suppressor. 5 is a first switch S for selecting the output signal of the S/H circuit 2 and the output signal of the multiplier 4 and inputting the selected signal to the A/D converter 6;
W, 7 is an adder that adds the output signal of the A/D converter 6 and the output signal of the K-fold multiplier 8; 9 selects the output signal of the A/D converter 6 and the output signal of the adder 7; The output signal of the memory 10 is input to the multiplier 8 and the divider 11 at the second switch SW for inputting the output signal to the memory 10, and the third switch SW for inputting the output signal to the memory 10.
It is designed to be input to the switching terminal of W12. Third
The switching SW 12 selectively inputs the output signal of the memory 10 and the output signal of the divider 11 to the D/A converter 13, and
The output signal of the converter 13 is configured to be input to the subtracter 3 via the S/H circuit 14.

Further, each of the switching SWs 5, 9, and 12 is shown in FIG.
It is controlled by control pulses 1 and 2 generated in synchronization with a vertical synchronizing signal VD as shown in FIG. That is, the first and second switching SWs 5 and 9 are controlled by the control pulse 1, and the third switching SW 12 is controlled by the control pulse 2. In addition, Figure 2
, t1 is the first storage operation period to the memory 10, t2 is the second storage operation period, and t3 is the operation period for writing while reading from the memory 10.

Next, the operation of the FPN suppressor configured as described above will be explained with reference to the timing chart of FIG. 2, the signal waveform diagram of FIG. 3, and the flow chart of FIG. 4. First, the image sensor 1 is placed in a light-shielded state, and the first, second, and third switching SWs 5, 9, and 12 are connected to the ■ side using the control pulses 1 and 2. Then, the dark signal NS of the image sensor 1 shown in FIG.
The data is A/D converted by the D converter 6, and then stored in the memory 10 via the second switching SW9. At this time, the memory 10 stores the FPN (NS) of the image sensor as shown in FIG. 3(B).
and the residual F due to the quantization error and linearity error of the A/D converter.
PN(N1) and the difference signal (NS-N1) are stored. Next, the through dark signal NS that does not pass through the A/D converter 6 and the dark signal (NS -N
1) is subjected to subtraction processing by the subtracter 3 via the D/A converter 13 and the S/H circuit 14. As a result, the dark FPN (NS) of the image sensor 1 is removed from the subtracter 3, and the residual FPN (N1) is output as shown in FIG. 3C. Then, as shown in FIG. 3(D), this residual FPN
(N1) is multiplied by K in the multiplier 4, and the first and second switching S
W5 and 9 are switched to the ■ side.

Next, the residual FPN multiplied by K (K・N1)
is A/D converted by the A/D converter 6 and becomes (E) in FIG.
As shown in , a difference signal (K·N1 −N2 ) between the residual FPN (K·N1 ) multiplied by K and the residual FPN (N2 ) resulting from the second A/D conversion is output. Next, the FPN(NS-N1) stored in the memory 10 is read out, and as shown in FIG. While adding the output signals (K・N1 −N2) using the adder 7,
Stored in memory 10. As a result, the memory 10 has the following information as shown in FIG.
FPN (K·NS −N2 ) is stored.

Next, the FPN is read from the memory 10 and multiplied by 1/K by the divider 11, as shown in (H) of FIG.
NS -N2 /K) level FPN, and D/A converter 13 performs D/A conversion. Next, the light shielding is released, and the image signal from the image sensor 1 is input to the subtracter 3 via the S/H circuit 2, and the output signal (N
S −N2 /K) through the S/H circuit 14 to the subtracter 3
and perform subtraction processing between the two. As shown in FIG. 3(I), the bright imaging signal is composed of the signal component S and the element FPN(N
S ) is added, so by the subtraction process by the subtractor 3, as shown in (J) of FIG. 3,
The signal component S and the 1/K times the residual FPN (N2/K) are output and input to the signal processing circuit. Therefore, it is possible to improve FPN suppression accuracy using a single memory without reducing the dynamic range of the analog subtraction FPN suppression method.

[0013]

[Effect of the invention] As explained above based on the embodiments,
According to the present invention, by performing an FPN write operation twice to a single memory, the element FPN multiplied by K and the residual FPN
The difference signal is stored, multiplied by 1/K, and subtracted from the imaged signal to suppress the FPN of the output signal to 1/K times the residual FPN, making it possible to use a single memory. With this simple configuration, a highly accurate FPN suppression method can be realized without reducing the dynamic range.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of an FPN suppression device for explaining an embodiment of an FPN suppression method according to the present invention.

FIG. 2 is a diagram showing the timing of control pulses of the FPN suppressor shown in FIG. 1;

FIG. 3 is a signal waveform diagram for explaining the operation of the FPN suppression device shown in FIG. 1;

FIG. 4 is a flowchart for explaining the operation of the FPN suppression device shown in FIG. 1;

FIG. 5 is a block configuration diagram showing a configuration example of a conventional FPN suppression circuit.

FIG. 6 is a block configuration diagram showing another configuration example of a conventional FPN suppression circuit.

[Explanation of symbols]

1 Imaging device 2,14 S/H circuit 3. Subtractor 4, 8 multiplier 5 First switching SW 6 A/D converter 7 Adder 9 Second switching SW 10 Memory 11 Divider 12 Third switching SW 13 D/A converter

Claims (1)

[Claims] 1. A dark time signal of an image sensor is read out in a light-shielded state, A/D converted, and stored in a memory, and a dark time signal stored in the memory is converted from an image signal read out from the image sensor to D.
In a fixed pattern noise suppression method that suppresses fixed pattern noise by A/A conversion and subtraction, the first step is to A/D convert the dark signal of the image sensor and store it in a memory, and to convert the dark signal of the image sensor to the A second step in which the dark signal stored in the memory is D/A converted and subtracted, and the resulting residual fixed pattern noise is multiplied by K (K>1), and the residual fixed pattern noise multiplied by K is converted to A/D. a third step in which the dark signal accumulated in the memory in the first step is multiplied by K and added, and the addition result is stored in the memory again; and a residual fixed signal accumulated in the memory in the third step. A fourth step in which the pattern noise is multiplied by 1/K and D/A converted, and a fifth step in which light shielding is removed and the residual fixed pattern noise resulting from the D/A conversion in the fourth step is subtracted from the image signal of the image sensor. Fixed pattern noise suppression method.