JPH04306983A - Image pickup signal processing circuit - Google Patents

Abstract

PURPOSE:To realize the image pickup signal processing circuit in which a bit length of an A/D converter is effectively utilized, bit allocation to an FPN is reduced and bit allocation to an actual signal is increased so as to expand the dynamic range. CONSTITUTION:The image pickup signal processing circuit is made up of a 1st FPN suppression circuit 1 comprising an A/D converter 12 converting an input image pickup signal into a digital signal, a frame. memory 13 storing its output signal by one frame period, a D/A converter 15 converting an output data of the frame memory 13 into an analog signal, and an analog subtractor 16 subtracting an output signal of the D/A converter 15 from the input image pickup signal, and made up of a 2nd FPN suppression circuit 2 comprising an A/D converter 17 converting an output of the subtractor circuit 16 into a digital signal, a frame memory 19 storing its output signal by one frame period, and a digital subtractor 20 subtracting an output data of the frame memory 19 from an output of the A/D converter 17.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an imaging signal processing circuit for suppressing fixed pattern noise (hereinafter abbreviated as FPN) specific to an amplified solid-state imaging device from an output signal of the device.

0002

[Background Art] Conventionally, FPN unique to amplified solid-state image sensors
Various proposals have been made for suppressing the
1 is a diagram showing the circuit configuration of the most common FPN suppression circuit. A signal IN from the image sensor is input through an input terminal 101 and converted into digital data by an A/D converter 102 . At this time, if the light to the image sensor is blocked by a light blocking means such as a shutter, the control signal CONT input from the terminal 107 indicating FPN capture is input.
As a result, the gate circuit 103 passes the output signal of the A/D converter 102 to write data to the frame memory 104, and operates to prohibit data writing when writing for one frame is completed.
4 incorporates FPN. After this, the frame memory 104 enters a read operation, and the arithmetic circuit 105 outputs a signal obtained by subtracting the FPN read from the frame memory 104 from the output signal of the A/D converter 102 to the output terminal 101. There is.

FIG. 5 shows the FPN capture control signal CONT.
2 is a diagram illustrating the timing of FPN capture for one frame period, where VD is a vertical synchronization signal synchronized with the image sensor. FIG.

0004

[Problem to be Solved by the Invention] In the conventional FPN suppression circuit of this type, the A/D converter 102 must have a bit length equal to the sum of the FPN and the actual imaging signal. First, it must be constructed with a large number of bits. 1 as the bit length of the A/D converter
When configuring a 0-bit system, set the FPN to 8~
9 bits must be allocated, and the actual dynamic range of the signal is only about 9 bits, and in order to further expand the dynamic range, the bit length of the A/D converter must be increased. However, there was a problem in that it resulted in an expensive system.

The present invention was made to solve the above-mentioned problems of the conventional FPN suppression circuit, and effectively utilizes the bit length of the A/D converter to reduce the allocation of FPN to the image signal. An object of the present invention is to provide an imaging signal processing circuit that can increase bit allocation to an actual signal.

[0006]

[Means and operations for solving the problems] In order to solve the above problems, the present invention suppresses the FPN specific to the amplified solid-state image sensor from the signal of the amplified solid-state image sensor, as shown in the conceptual diagram of FIG. In the imaging signal processing circuit for
A D converter, a first frame memory that stores the output signal of the A/D converter for one frame period, and a first D/A that converts the data in the frame memory into an analog signal.
a first FPN suppression circuit 1 comprising a converter and a first arithmetic circuit that subtracts the output signal of the first D/A converter from the signal IN from the image sensor; a second A/D converter that converts the output of the first arithmetic circuit of the circuit into a digital signal;
A second FPN suppression circuit 2 comprising a second frame memory that stores data for a frame period, and a second arithmetic circuit that subtracts the second frame memory output data from the output of the second A/D converter. These constitute an imaging signal processing circuit.

In the imaging signal processing circuit configured as described above, the bit length of the A/D converter of the first FPN suppression circuit 1 is assigned to the FPN of the image sensor, and the A/D conversion of the second FPN suppression circuit 2 is performed. The bit length of the frame memory is assigned to the bit length necessary for the dynamic range of the imaging signal, and the first FPN suppression circuit 1 subtracts the output signal of the frame memory after D/A conversion from the signal from the imaging device in an analog manner. After coarsely suppressing the FPN, the second FPN suppressing circuit 2 suppresses the FPN with high precision. This makes it possible to increase the bit length assigned to the image signal.

[0008]

[Example] Next, an example will be explained. FIG. 2 is a block diagram showing an embodiment of the imaging signal processing circuit according to the present invention, and FIG. 3 is a diagram showing the timing of control signals used for its operation. In FIG. 2, 11 is an input terminal for inputting the signal IN from the image sensor, 12 and 17 are the first and second A/D converters, and 13 and 18 are the first and second A/D converters by the FPN capture control signal CONT. First and second gate circuits that operate to write data into frame memories 14 and 19; 14 and 19 are first and second frame memories that store signals for one frame period;
5 is a D/A converter, 16 is a D/A from the input image signal IN
An analog subtracter for subtracting the output of the converter 15, 20 is A
/D converter 17 output to second frame memory 19
21 is an output terminal for the output signal OUT after FPN suppression, 22 is an input terminal for the control signal CONT that controls FPN capture, and
/D converter 12, first frame memory 14, D/A
The converter 15 and the analog subtracter 16 constitute a first FPN suppression circuit, and the second A/D converter 17, the second gate circuit 18, the second frame memory 19, and the subtracter 2
0 constitutes a second FPN suppression circuit.

Further, as shown in FIG. 3, the control signal CONT is synchronized with the vertical synchronization signal VD that is synchronized with the image sensor, and when the light to the image sensor is blocked by a light shielding means such as a shutter, the control signal CONT is generated for two frame periods. It becomes “H” level. (For the sake of explanation, let's assume it's "H" level)

Next, the operation of this embodiment will be explained. When light to the image sensor is blocked by a light blocking means such as a shutter, the FPN of the image sensor is output to the input terminal 11. At the same time, FPN is synchronized with vertical synchronization signal VD.
The capture control signal CONT becomes "H" level. At this time, the signal input to the input terminal 11 is transmitted to the A/D converter 1.
2 and the gate circuit 13 to the frame memory 14, and after one frame, the FPN unique to the image sensor is stored in the frame memory 14. However, until the storage of FPN is completed, the contents of the frame memory 14 are uncertain, so the content is transferred to the analog subtracter 16 via the D/A converter 15.
The data processed in the frame memory 19 is also uncertain, and the value of the frame memory 19 is also uncertain. However, once the writing of the FPN to the frame memory 14 is completed, the FPN taken in by the A/D converter 12 via the D/A converter 15 is input to the analog subtracter 16, where it is roughly subtracted and the second
The signal is input to the A/D converter 17 of the FPN suppression circuit. In this first FPN suppression circuit, for example, the input signal is
In the case of 0 bits, assuming that FPN occupies half of the total, it becomes 9 bits, and the bit length of the A/D converter 12 is constituted by 9 bits, which is the maximum value of FPN.

The data A/D converted by the A/D converter 17 is sent to the frame memory 1 via a gate circuit 18.
9, and capture ends after one frame period. In other words, in a two-frame period from the time when light is blocked to the image sensor,
FP to the first and second frame memories 14 and 19
After the acquisition of N is completed, the memory moves to the read operation. Note that the frame memory 1 of the second FPN suppression circuit
As is clear from the operation of loading the FPN into the A/D converter 17, the bit length of the frame memory 19 only needs to be equal to the maximum value of the FPN appearing in the A/D converter 17.

[0012] After that, when the light shielding to the image sensor is released, a signal obtained by adding the image signal to the FPN is inputted to the input terminal 11, and after the FPN is roughly removed by the analog subtracter 16, A/D conversion is performed. After the signal is input to the subtracter 17 and becomes digital data, the FPN is accurately removed by the digital subtracter 20, and the signal after FPN suppression is output to the output terminal 21.

[0013] The imaging signal processing circuit configured as described above has the following features:
This can be easily achieved by configuring the gate circuits 13 and 18 with AND elements, using FIFO memories, etc. as the frame memories 14 and 19, and controlling the read and write clocks to the frame memory using the same method as the gate circuit. can. The bit length of the frame memory 19 in this embodiment depends on the bit length of the A/D converter 12;
~4 bits is sufficient.

[0014]

[Effect of the invention] As explained above based on the embodiments,
According to the present invention, by using two FPN suppression circuits, it is possible to increase the bit length allocated to the image signal and expand the dynamic range, without using a large memory capacity compared to the conventional example. realizable. Further, the configurations of the two FPN suppression circuits are almost the same, and it is possible to easily configure the circuits without considering complicated operation timing.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram showing the configuration of the present invention.

FIG. 2 is a block configuration diagram showing an embodiment of an imaging signal processing circuit according to the present invention.

FIG. 3 is a diagram showing the timing of control signals used for the operation of the imaging signal processing circuit shown in FIG. 1;

FIG. 4 is a block configuration diagram showing a conventional FPN suppression circuit.

FIG. 5 is a diagram showing the timing of control signals used in the operation of the conventional FPN suppression circuit shown in FIG. 4;

[Explanation of symbols]

1 First FPN suppression circuit 2 Second FPN suppression circuit 11 Input terminal 12 First A/D converter 13 First gate circuit 14 First frame memory 15 D/A converter 16 Analog subtractor 17 Second A/D converter 18 Second gate circuit 19 Second frame memory 20 Digital subtractor 21 Output terminal

Claims (3)

[Claims] 1. In an imaging signal processing circuit for suppressing fixed pattern noise specific to an amplified solid-state imaging device from a signal of the imaging device, a first A/D converting the signal from the imaging device into a digital signal. a converter, a first frame memory that stores the output signal of the A/D converter for one frame period, a first D/A converter that converts the data of the frame memory into an analog signal, and the imaging device. a first fixed pattern noise suppression circuit comprising a first arithmetic circuit that subtracts the output signal of the first D/A converter from the signal from the element; a second A/D converter that converts the output of the arithmetic circuit into a digital signal; a second frame memory that stores the output signal of the A/D converter for one frame period;
a second arithmetic circuit that subtracts the output data of the second frame memory from the output of the A/D converter of the second frame memory;
An imaging signal processing circuit comprising: a fixed pattern noise suppression circuit; and a fixed pattern noise suppression circuit. 2. The imaging signal processing circuit according to claim 1, wherein the bit length of the first A/D converter has a maximum value of fixed pattern noise of the imaging device. 3. The bit length of the second frame memory is equal to the maximum value of fixed pattern noise appearing in the second A/D converter.
The imaging signal processing circuit described.