JPH04313936A - Communication equipment - Google Patents

Abstract

PURPOSE:To provide a buffer memory, especially that buffering a communication data for transmission and reception. CONSTITUTION:Addresses of a buffer memory are allocated so that high-order bits designate any of plural transmission and reception buffers 1, 2a, 2b and low-order its designate sequentially each storage area in each buffer. When a high-order bit of an address is given, a counter generates a low-order bit sequentially and automatically and both bits are integrated into an address signal to access each storage area of the buffer by an address generating means. Moreover, when information to be received is stored in each buffer, the number of storage areas used for storing the information is stored in a head storage area and the information to be received is stored in each buffer, then a CRC check data of the area is stored in a storage area next to the end storage area in use.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device, and more particularly to a buffer memory, and particularly to a buffer memory for buffering communication data for transmission and reception.

0002

BACKGROUND OF THE INVENTION In the United States, from 1995 onwards, passenger cars are scheduled to be regulated by the Bryan Bill.

[0003] This bill stipulates that fuel efficiency in 1995 had improved by 20% compared to 1988;
As of 2000, sales of passenger cars in the United States are permitted on the condition that the same 40% improvement is achieved. The most effective way to improve the fuel efficiency of passenger cars is to reduce the weight of the car body. In order to achieve this weight reduction of the vehicle body, it is effective to introduce an in-vehicle LAN that can reduce the number of wire harnesses and simplify wiring.

[0004] Also, the California Air Resources Board (CARB) of the United States of America
The ir Resources Board is planning to implement exhaust gas-related regulations for passenger cars from the 1994 model year onwards, with the aim of protecting air resources. Under these regulations, it goes without saying that emissions of harmful substances such as NOx, HC, and CO need to be reduced compared to the current level, but also include various sensors and exhaust gas control parts (catalysts) connected to the engine control unit of passenger cars. etc.) is required to have a self-diagnosis function called on-board diagnostics that detects deterioration or failure and notifies the user. The specifications for the failure diagnosis data and data transfer format for this purpose have already been established by SAE
It is published as J1850 or ISO-9141.

On the other hand, irrespective of the above-mentioned regulations, as the control units of passenger cars have become more sophisticated and have a wider variety of functions in recent years, networks for self-diagnosis functions have been spread throughout passenger cars, and various control units have become more sophisticated. Technology has already been introduced to monitor the operation of In addition to the control unit,
Networking of operations and displays of various systems such as navigation systems, audio systems, air conditioning, and telephones is progressing. From this point of view as well, it is becoming essential to introduce in-vehicle LANs to passenger cars.

[0006]

[Problems to be Solved by the Invention] As described above, in order to reduce the weight and improve functionality of future passenger cars, it is possible to reduce the number of wire harnesses and simplify the wiring inside the passenger car.
The introduction of AN is essential, and for that purpose the SA mentioned above is necessary.
It is necessary to use a communication device that complies with E-J1850 or ISO-9141 specifications. The present invention has been made in view of the above circumstances, and is mainly directed to SAE-
The main purpose of the present invention is to provide a communication device that complies with J1850 or ISO-9141 specifications, especially a buffer memory thereof.

[0007]

[Means for Solving the Problems] A communication device of the present invention has a buffer memory whose address specifies one of a plurality of transmitting buffers and receiving buffers by high-order bits,
The lower bits are allocated to sequentially designate each storage area within each buffer.

Further, the communication device of the present invention has a counter that automatically generates lower bits in sequence when upper bits of an address are given, and when upper bits given from the outside and the counter are generated. The present invention includes an address generating means that can access each storage area of one buffer of the buffer memory with the above-mentioned address allocation by outputting the lower bits as an address signal.

Furthermore, the communication device of the present invention provides that when information to be transmitted or information to be received is stored in each buffer,
The configuration is such that the number of storage areas used to store the information is stored in the first storage area.

Furthermore, in the communication device of the present invention, when information to be received is stored in each buffer, the C of the information is
The configuration is such that the RC check data is stored in the storage area next to the last storage area in use.

[0011]

[Operation] In the communication device of the present invention, the address of the buffer memory specifies one of a plurality of transmission buffers and reception buffers using the upper bits, and sequentially specifies each storage area within each buffer using the lower bits. It has a counter that automatically generates the lower bits in sequence when the upper bits of the address are given, and the upper bits given from the outside and the lower bits generated by the counter are Since it is equipped with an address generation means that can access each storage area of one buffer of the buffer memory with the above-mentioned address allocation by outputting this as an address signal, it is possible to access the upper bits of the address from outside. By simply specifying each buffer, each storage area within that buffer is accessed.

Furthermore, in the communication device of the present invention, when information to be transmitted or information to be received is stored in each buffer, the number of storage areas used to store the information is stored in the first storage area. Therefore, when information is read from each buffer, the number of storage areas that actually need to be read is known at the time the first data of that information is read, and this value and the lower bit address signal mentioned above are used. By comparing the output value of the counter that outputs the information each time the information is read,
If they match, reading of information is stopped.

Furthermore, in the communication device of the present invention, when information to be received is stored in each buffer, the information is stored in the storage area next to the last storage area used for storing the information.
Since the CRC check data is stored, it becomes possible for the receiving side to compare the CRC data generated at the time of transmitting the information with the CRC data generated for the received data again.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to drawings showing embodiments thereof. The communication device of the present invention described below performs protocol control in accordance with the aforementioned SAE 1850, and its transmission and reception data strings comply with SAE 2054.
It consists of multiple data strings according to the frame format specified in .

FIG. 1 is a block diagram schematically showing the configuration of a buffer memory of a communication device according to the present invention.

Before explaining the configuration of the communication device according to the present invention, first, referring to a block diagram showing the overall configuration of the communication device according to the present invention shown in FIG. Explain the concept of flow.

In FIG. 4, the communication device 8 of the present invention is located between a microcomputer 91 and a LAN transmission line 90, and is connected to a microcomputer interface block.
(hereinafter referred to as microcomputer IF block)
11, a buffer memory block 9, and a LAN interface block (hereinafter referred to as LAN IF block) 10.

When transmitting data from the microcomputer 91 to the LAN transmission line 90, the data string is transferred from the microcomputer 91 to reference numerals 18a, 18, 18,
As shown in 13 and 13a, the data string is sequentially transferred to the microcomputer IF block 11, buffer memory block 9, and LAN IF block 10.
It is sent to the LAN transmission line 90.

Specifically, as indicated by the reference numeral 18a, the transmission data string is transferred from the microcomputer 91 to the microcomputer IF block 11 in the communication device 8, and then, as indicated by the reference numeral 18, The data is transferred to the buffer memory block 9, further transferred to the LAN IF block 10 as shown by reference numeral 13, and finally sent from the LAN IF block 10 to the LAN transmission line 90 as shown by reference numeral 13a. The transmission operation is completed.

[0020] A series of controls for the transfer timing of the transmission data string as described above are carried out by the microcomputer IF block 11, the buffer memory block 9, and the LAN I
This is performed in each block of the F block 10.

Next, the direction of transfer of a received data string when the data string is received from the LAN transmission line 90 to the microcomputer 91 will be explained.

The data string received from the LAN transmission path 90 is transmitted from the LAN IF block 10 to reference numerals 15a and 1.
As shown in 5, 20, 20a, the data string is LAN
IF block 10, buffer memory block 9,
The data is sequentially transferred through the microcomputer IF block 11 and input to the microcomputer 91.

Specifically, as indicated by the reference numeral 15a, the received data string is transferred from the LAN transmission line 90 to the LAN IF block 10 in the communication device 8, and as indicated by the reference numeral 15, it is transferred to the buffer memory. Transferred to block 9. Then, as indicated by reference numeral 20, the received data string and data having the same attributes regarding the received data string are transferred to the microcomputer IF block 11, and the data string is transferred to the microcomputer 91, as indicated by reference numeral 20a. be transferred.

[0024] A series of controls on the timing of transfer of the received data string as described above are performed in each block of the microcomputer IF block 11, buffer memory block 9, and LAN IF block 10, as in the case of transmission. .

The buffer memory shown in FIG. 1 is disposed within the buffer memory block 9 in the communication device 8 shown in FIG. 4 as described above.

Next, an example of the structure of the buffer memory will be explained with reference to FIG. 1, which is a block diagram showing an outline of the structure.

The buffer memory can be roughly divided into a transmission buffer 1, a reception buffer group 2, a transmission data string, and a reception data string (hereinafter, a data string is expressed as a frame,
A group of registers (hereinafter referred to as status register group) 3 stores data for managing the status of a transmitted data string (sent data string is called a transmit frame, a received data string is called a received frame), and a data transfer state of one frame is stored. It is comprised of a register group 5 consisting of a plurality of registers each storing data, and a register group 6 consisting of a plurality of registers each storing specific data in one frame.

The transmission buffer 1 is composed of a plurality of registers for storing transmission data strings, and one set is provided.

The reception buffer group 2 includes two sets of first and second reception buffers 2a and 2b. Each receive buffer 2a, 2b receives one received frame.
It consists of multiple registers that store frames.

As mentioned above, the status register group 3 includes:
The first, second, and third sections each store one piece of data for managing the status of the transmitted frame and the received frame.
, fourth status register 3a, 3b, 3c, 3
It is composed of d.

The register group 5 is composed of a transmission error register 4 and a reception error register group 5d.

The transmission error register 4 is a register in which data regarding the transmission status of a set of transmission frames is stored. Furthermore, the reception error register group 5d includes first, second, and third reception error registers 5a, 5b, and 5b, each storing data regarding the reception status of a set of reception frames.
5c.

The register group 6 is composed of a source address register group 6d and a reply RSP register 7.

The source address register group 6d includes first registers each storing specific data in a set of received frames.
, second and third source address registers 6a, 6b,
6c. Further, the reply RSP register 7 is a register that stores specific data regarding one set of transmission frames.

Next, the configuration of the buffer memory of the communication device of the present invention will be explained in more detail with reference to FIGS. 2 and 3 showing the specific configuration of the buffer memory of the communication device of the present invention.

The transmission buffer 1 is composed of 15 registers each for storing a plurality of data constituting one transmission frame. Transmission buffer 1
Each register has a data capacity of 8 bits (1 byte), and in order from the first address side, the message length, priority code, destination address, source address, type format/diagnosis mode data, and up to 10 bytes of communication data. are stored respectively.

The reception buffer group 2 can store two received frames. Therefore, the receiving buffer group 2 includes first and second receiving buffers 2a and 2 having the same configuration.
b is provided. Each of the receive buffers 2a and 2b is composed of 16 registers each for storing a plurality of data constituting one received frame. Each register of the first and second reception buffers 2a and 2b has a data capacity of 8 bits (1 byte), and in order from the first address side, the message length, priority code, destination address, source address, type format/diagnosis mode. each data, maximum 10
Bytes of communication data and CRC data are stored respectively.

The first, second, third, and fourth stator registers 3a, 3b, 3c, and 3d store one transmission frame stored in the above-mentioned transmission buffer 1 and both reception buffers 2a and 2b. 2 received frames, and data for managing the status of the third frame when reception of the third frame is requested when the received frames are stored in both receive buffers 2a and 2b. Store each.

The transmission error register 4 is the transmission buffer 1.
Data on the transmission status of the transmission frame stored in , that is, data indicating whether or not an error has occurred is stored.

The first and second registers of the reception error register group 5d
, the third reception error registers 5a, 5b, and 5c store the two reception frames stored in the above-mentioned reception buffers 2a and 2b, and when a reception frame is already stored in both reception buffers 2a and 2b, the third reception error register 5a, 5b, and 5c also store the third reception frame. When reception is requested, data on the reception status, ie, data indicating whether or not an error has occurred, is stored.

The first of the source address register group 6d,
Second and third source address registers 6a, 6b, 6
c stores the source address which is the fourth byte data in the received frames stored in the above-mentioned receive buffers 2a and 2b and the above-mentioned third frame, respectively.

[0042]Reply RSP register 7 contains the above-mentioned SAE
- Stores the reply response (hereinafter referred to as reply RSP) sent back from the receiving side when a transmission frame specified in J1850 is sent.

Next, the address structure of both the transmitting buffer 1 and the receiving buffers 2a and 2b of the receiving buffer group 2 will be explained with reference to the schematic diagram shown in FIG. 5.

The transmission buffer 1 has a memory area capable of storing 15 bytes (there is an unused area of 1 byte) of a data string composed of 8 bits per byte. Further, both receive buffers 2a and 2b each have a memory area capable of storing 16 bytes of a data string composed of 8 bits in 1 byte.

Write address 1WA of transmission buffer 1
and read address 1RA are commonly assigned addresses from "00" to "0F" in hexadecimal notation. Also, the write address 2aWA of the first reception buffer 2a
And the read address 2aRA is commonly assigned from "10" to "1F" in hexadecimal notation. Furthermore, the second
The write address 2bWA and read address 2bRA of the reception buffer 2b are also expressed in hexadecimal from "20" to "2F".
are commonly assigned.

Note that addresses are assigned to each register other than the transmission buffer 1 and the reception buffer group 2 as shown in FIG. Here, the TX register write completion registers 64 and R at addresses "7E" and "7F"
The X register read completion register 67 will be described later.

[0047] Here, the data constituting the transmission frame stored in the transmission buffer 1 and its arrangement will be explained with reference to the schematic diagram of FIG.

In FIG. 7, the range indicated by reference numeral 100 is the transmission data group stored in the transmission buffer 1. This data group is message field 10
2, and a message length field 101 in which data indicating the message length (number of bytes) of this message field 102 is stored.

The message field 102 is composed of a 4-byte communication control data group field 110 and a maximum 10-byte communication data group field 120, which is a field in which the original communication data is stored. Each 1-byte field of the communication control data group field 110 is a field 111 in which each data of priority code, destination address, source address, type format/diagnosis mode is stored.
They are 112, 113, 114.

The communication data group field 120 of this transmission frame has a different number of bytes depending on each transmission frame, and therefore the message length of the entire transmission frame is undefined. Therefore, the message length field 101 of the transmission data group 100 contains the message field 102.
The number of bytes is stored. However, the maximum is 14 bytes.

Such a transmission data group 100 is stored in the transmission buffer 1, and specifically, it is stored as follows.

Both addresses 1WA, 1 of transmission buffer 1
A message length field 101 is stored in a 1-byte area of RA "00". Address “01” to “01”
04" 4-byte area contains communication control data group 110.
4 bytes of data making up each are stored. That is, each data of the communication control data group 110 has a priority code field 111 in the first byte of address "01".
However, the destination address field 112 is in the second byte of address "02", and the destination address field 112 is in the second byte of address "02".
”, the source address field 113 is placed in the third byte of
However, a type format/diagnosis mode field 114 is stored in the fourth byte of address "04". The 10-byte area from addresses "05" to "0G" stores each field of a communication data group field 120 consisting of n (n is 1 to 10) communication data groups.

Next, the data and data arrangement of the receive frame stored in both receive buffers 2a and 2b will be explained with reference to the schematic diagram of FIG. 8 showing the structure thereof.

The range indicated by reference numeral 200 in FIG. 8 is the data group stored in both reception buffers 2a and 2b. This data group stores the message field 102 and CRC byte data.C
Received frame 2 consisting of RC field 203
02, a message length field 201 indicating the message length of this received frame 202 is added.

The message field 102 is composed of a 4-byte communication control data group field 110 and a maximum 10-byte communication data group field 120, which is a field in which the original communication data is stored. Each 1-byte field of the communication control data group field 110 is a field 111 in which each data of priority code, destination address, source address, type format/diagnosis mode is stored.
They are 112, 113, 114.

The number of bytes in the communication data group field 120 of the received frames 2a and 2b differs depending on the received frame, and therefore the message length of the entire transmitted frame is undefined. Therefore, the message length field 201 of the received data group 200 contains the number of bytes of the message field 102 and the CRC field 203.
The number of bytes added is stored. However, since a CRC field 203 is added to the received frame, the maximum length is 15 bytes, which is different from the message length field 101 of the transmitted data group.

Such a received data group is stored in either or both of the receiving buffers 2a and 2b, and specifically, it is stored as follows.

Both addresses 2aW of the first reception buffer 2a
A message length field 201 is stored in the 1-byte area of "10" of A, 2aRA. address”1
4-byte data constituting the communication control data group 110 is stored in the 4-byte areas from 1" to 14. That is, each data of the communication control data group 110 is stored in the first The priority code field 111 is in byte 111, and the destination address field 112 is in the second byte of address "12".
However, the source address field 113 is in the third byte of address "13", and the type format/diagnosis mode field 1 is in the fourth byte of address "14".
14 are stored respectively. Address “15” to “15”
The 10-byte area up to 1G" stores each field of the communication data group field 120 composed of n (n is 1 to 10) communication data groups. For example, the communication data group field 120 is biggest 10
If it is composed of communication data, the address "
CRC field 203 is in the 1-byte area of “1F”.
is stored.

[0059] The same is basically true for the second reception buffer 2b, and both addresses 2bWA and 2bRA
“1” when the upper side of both is the first receiving buffer 2a
The only difference is that “” becomes “2”.

To summarize the above, the transmission data group 100 stored in the transmission buffer 1 and both reception buffers 2a,
The difference from the received data group 200 stored in 2b is as follows.
Only the 16th byte is stored in the area where the lower 4 bits of the address of the transmitting buffer 1 or receiving buffers 2a, 2b are "F". That is, in the transmission data group 100, the 16th byte is unused, and in the reception data group 200, for example, if the communication data group field 120 is composed of the maximum 10 pieces of communication data, the 16th byte is the CRC field. It is used as 203. The upper 4 bits of addresses 1WA and 1RA assigned to transmit buffer 1 are fixed to "0" in hexadecimal notation, and the lower 4 bits are written as "0" to "F" (actually "G").
), it is possible to specify a unique address within the 16-byte transmission buffer 1.

[0061] Furthermore, the upper 4 bits of addresses 2aWA and 2aRA assigned to the first reception buffer 2a are 1.
It is fixed at "1" in hexadecimal notation, and by sequentially changing the lower 4 bits from "0" to "F", you can specify a unique address in the 16-byte first reception buffer 2a. It is now possible. Furthermore, the second reception buffer 2
The upper 4 bits of addresses 2bWA and 2bRA assigned to b are fixed to "2" in hexadecimal notation,
By sequentially changing the lower 4 bits from "0" to "F", it is possible to specify a unique address within the 16-byte second reception buffer 2b.

In other words, the address specification for the buffer memory block 9 is based on the upper 4 of the 8-bit address.
The bits specify either the transmission buffer 1, the first reception buffer 2a, or the second reception buffer 2b, and the lower 4 bits specify each 1-byte area.

Next, the structure for generating addresses of the transmitting buffer 1 and the receiving buffer group 2 having such an address structure will be explained.

FIG. 9 is a block diagram showing the configuration of the main parts of the address generation mechanism including the transmission buffer 1 and the reception buffer group 2. In FIG. In addition, in FIG. 9, the LAN IF block 10 is on the right side, and the microcomputer IF block 11 is on the left side.
are located respectively.

In FIG. 9, reference numeral 14a is a LAN
This is a 4-bit address signal given from the IF block 10, and is input to the decoder 150. A 4-bit counter 151 2 is connected to this decoder 150 2 , and the output signal 14b of the count value is inputted to the decoder 150 2 . The decoder 150 is a LAN
Address signal 1 given from IF block 10
4a as the upper 4 bits and the output signal 14b of the counter 151 as the lower 4 bits, an 8-bit address signal 14 is generated and applied to the transmitting buffer 1, the first receiving buffer 2a, and the second receiving buffer 2b, respectively.

The output signal 14b of the counter 151 is also given to a comparator 153, and this comparator 15
A reset signal RS1 is applied from the counter 151 to the counter 151.

[0067] Reference numbers 15a and 15b are LA, respectively.
N shows input data signals from the IF block 10 to the first reception buffer 2a and the second reception buffer 2b,
Reference numeral 13 indicates an output data signal from the transmission buffer 1. The output data signal 13 from the transmission buffer 1 is also given to the message length register 152, and when the transmission data group stored in the transmission buffer 1 is output to the LAN IF block 10, it is placed at the beginning of the transmission data group. The message length data is stored in this message length register 152.

Note that this message length register 152
The message length data stored in is provided to a comparator 153. Then, the comparator 153 compares the message length data given from the message length register 152 and the count value output signal 14b of the counter 151, and when they match, activates the aforementioned reset signal RS1 output to the counter 151. Make it.

On the other hand, reference numeral 17a is a 4-bit address signal given from the microcomputer IF block 11, and is input to the decoder 160. A 4-bit counter 161 is connected to this decoder 160, and the output signal 17b of the count value is input to the decoder 160. The decoder 160 uses the address signal 17a given from the microcomputer IF block 11 as the upper 4 bits, and uses the counter 1
An 8-bit address signal 17 is generated using the output signal 17b of 61 as the lower 4 bits, and is applied to the transmission buffer 1, the first reception buffer 2a, and the second reception buffer 2b.

The output signal 17b of the counter 161 is also given to the comparator 163, and this comparator 16
A reset signal RS2 is applied to the counter 161 from the counter 161.

[0071] Reference numerals 20a and 20b each indicate the first
It shows output data signals from the reception buffer 2a and the second reception buffer 2b to the microcomputer IF block 11, and reference numeral 18 indicates the microcomputer IF block 11.
An input data signal from block 11 to transmit buffer 1 is shown. The output data signals 20a, 20b from the first receive buffer 2a, second receive buffer 2b to the microcomputer IF block 11 are given to the message length register 162 via the selector 164, and both receive buffers 2a, 2b The received data group stored in microcomputer IF block 1
1, the message length data located at the beginning is stored in this message length register 162.

Note that this message length register 162
The message length data stored in is provided to a comparator 163. Then, the comparator 163 compares the message length data given from the message length register 162 and the count value output signal 17b of the counter 161, and when they match, activates the aforementioned reset signal RS2 output to the counter 161. Make it.

Next, as an example of the operation of the address generation mechanism configured as shown in the block diagram of FIG. ”)
and add a 1-byte message length field 101 to this
A case will be described in which a transmission frame to which . Note that FIG. 10 is a timing chart showing the state of the output signal of each component of FIG. 9 and the state of writing data to the transmission buffer 1 in that case, and FIG. 11 is a flowchart showing the procedure. It is assumed that each component shown in the block diagram of FIG. 9 operates in synchronization with a clock, which is not shown.

First, as shown in FIG. 10(a), the LAN
4-bit address signal 14 from the IF block 10 side
a is output. The value of 4 bits of this address signal 14a is fixed to "0" in hexadecimal notation. Since the counter 151 is not activated at this point, its output signal 14b is "0" in hexadecimal notation, as shown in FIG. 10(b). Therefore, decoder 1
The address signal 14 output from 50 is shown in FIG.
), the address signal 14a is the upper 4 bits, and the output signal 14b of the counter 151 is
It becomes "00" in hexadecimal notation with "00" as the lower bit. This address signal "00" accesses the address "00" of the transmission buffer 1, and the message length data "0B" stored at that address is output as the output data signal 13 to the LAN IF block 10 side.
The lower 4 bits of data "B" are stored in the message length register 152 as shown in FIG. 10(e) (step S1 in FIG. 11).

As data is newly stored in the message length register 152, the reset signal RS1 applied from the comparator 153 to the counter 152 becomes inactive, and the counter 151 becomes inactive, as shown in FIG. 10(f). Start up and start counting (Figure 11
step S2). As shown in FIG. 10(b), the output signal 14b of the count value of the counter 151 is expressed in hexadecimal from "0" to "1" by its 4 bits.
2". Therefore, the address signal 14 output from the decoder 150 also changes as shown in FIG.
c) “00”, “01” in hexadecimal as shown.
, "02", etc. are sequentially incremented. As a result, each address of transmission buffer 1 is accessed sequentially, and each address stored at each address is accessed sequentially.
Byte data is sequentially read out from the transmission buffer 1 by clock synchronization and sent to the LAN as an output data signal 13.
It is output to the IF block 10 (step S3 in FIG. 11).

As described above, by sequentially counting up the counter 151 while the address signal 14a is fixed at "0", each address of the transmission buffer 1 is sequentially accessed, and the data of each byte of the transmission frame is transferred to the LAN. It is output to the IF block 10 side, but during this time the comparator 153 is output to the message length register 152.
The message length data "B" stored in the counter 151 is compared with the output signal 14b of the count value of the counter 151 (step S4 in FIG. 11). Then, as long as the comparison result by the comparator 153 does not match, the counter 151 continues to count up as described above (
Step S6 in FIG. 11). Eventually, when the output signal of the counter 151 becomes "B", the comparison result by the comparator 153 matches, so the comparator 153 activates the reset signal RS1 output to the counter 151 (step in FIG. 11). S5). As a result, the counter 151 stops counting up, and reading of the transmission frame from the transmission buffer 1 is completed.

[0077] Furthermore, the decoder 160, 4-bit counter 161,
The operations of the message length register 163 and the comparator 163 are also the same as those of the decoder 150 on the LAN IF block 10 side.
4-bit counter 151, message length register 152
, comparator 153. However, since received frames are output from both receive buffers 2a and 2b to the microcomputer IF block 11 side, input of message length data to the message length register 162 is selected by the selector 164.

Therefore, the above-mentioned LAN IF block 10
Similarly to the operation of the first receiving buffer 2a, by fixing the address signal 17a input to the decoder 160 to one of "0", "1", or "2" and counting up the counter 161, , the second reception buffer 2b, and the microcomputer IF block 11 can read the reception data stored therein.

Next, the CRC byte stored in the CRC field 203, which is the last byte of the transmission frame, will be explained.

FIG. 12 is a block diagram showing a configuration in which two sets of communication devices of the present invention are connected to the LAN transmission path 90 and communicate with each other.

In FIG. 12, reference numerals 8a and 8b indicate communication devices of the present invention, to which microcomputers 91a and 91b are connected, respectively. Further, both communication devices 8a and 8b have transmission drivers 96a and 8b, respectively.
96b and reception drivers 97a, 97b
It is connected to a LAN transmission line 90.

Both in-vehicle transmission processors 8a and 8b have LAN IF blocks 10a and 1, respectively, as described above.
0b, buffer memory blocks 9a, 9a, microcomputer IF blocks 11a, 11b, and a unit consisting of a communication device 8a and a microcomputer 91a, each of which has an a added to its reference numeral, is referred to as a node A. A communication device 8b and a microcomputer 9 with b added to their respective reference numbers.
Let the unit consisting of 1b and 1b be node B.

[0083] As an example, a case of communication from node A to node B will be described. In this case, the flow of communication data is in the direction indicated by the arrow 99 in FIG.

First, the microcomputer 9 of node A
1a to microcomputer IF block 11a
A transmission frame having the data arrangement as described above is stored in the transmission buffer 1 in the buffer memory block 9a according to the address allocation as described above.

Next, the transmission frame stored in the transmission buffer 1 is transferred to the LANIF block 10a, where the message field 102 is CR
A C operation is performed. As a result of this CRC calculation, the transmission frame stored in the transmission buffer 1 is determined by the transmission driver 9.
6a is added to the end of the transmission frame when it is sent to the LAN transmission line 90.

[0086] Node B receives the transmission frame sent from node A as a reception frame from LAN transmission line 90 through reception driver 97b. LAN I
The F block 10b performs a CRC operation on the message field 102 and the CRC field 203 of the received frame, and also performs a CRC operation on the message field 102 and the CRC field 203 of the received frame.
02 and the number of bytes in the CRC field 203, the result is used as data in the message length field 201 of the received frame, and is written to the first reception buffer 2a or the second reception buffer 2b according to the data arrangement and address allocation described above.

Here, as an example, from node A to node B
Communication data group field 120 of the frame sent to
The schematic diagram of FIG. 13 shows a state in which a received frame in which the communication data group stored in the first receiving buffer 2a is 5 bytes is stored in the first receiving buffer 2a.

As shown in FIG. 13, the CRC byte is stored at address "1A" of the first reception buffer 2a, and is located at the end of the series of data strings of the transmission frame. In this case, from address “1B” to “1F”
The areas up to are not used. Further, for example, if the communication data group has a maximum of 10 bytes, the CRC byte will be stored at address "1F".

Next, specific control of the buffer memory of the communication device of the present invention will be explained with reference to the drawings.

FIG. 14 is a schematic diagram showing the input/output relationship of address signals and data signals in the communication device of the present invention, and FIG. 15 is a schematic diagram showing the input/output relationship of data to the buffer memory. 16 and 17 are schematic diagrams mainly showing the input/output relationship of control signals and address signals of the buffer memory. Note that the lower side of Figure 16 and Figure 1
It is continuous with the upper side of 7.

Reference numeral 12 in FIGS. 14 and 16 indicates LA
N - This is an address signal given from the IF block 10 to the buffer memory block 9, and as shown in FIG. 16, it is a read address signal for the transmission buffer 1 (hereinafter referred to as a transmission read address signal). More specifically, this transmission read address signal 12 is an address signal when the address signal 14 generated by the address generation mechanism described above specifies the transmission buffer 1.

Reference numeral 13 in FIGS. 14 and 15 is a data output signal output from the transmission buffer 1 to the LAN IF block 10, and is stored at the address of the transmission buffer 1 designated by the transmission read address signal 12. The data of the transmitted frame is output.

Reference numeral 14 in FIGS. 14 and 16 indicates LA
This is an address signal (hereinafter referred to as a received write address signal) given from the NIF block 10 to the buffer memory block 9. This received write address signal 1
More specifically, 4 is a write address signal to the reception buffer group 2, the status register group 3, the transmission error register 4, the reception error register group 5d, the source address register group 6d, and the reply RSP register 7.

Reference numeral 15 in FIGS. 14 and 15 indicates LA
N This is a data signal of a received frame inputted from the IF block 10 to the buffer memory block 9 (hereinafter referred to as a received write data signal).

Reference numeral 16 in FIGS. 14 and 16 is a signal (hereinafter referred to as
(referred to as the received write signal).

Reference numeral 17 in FIGS. 13 and 16 is an address signal applied from the microcomputer IF block 11 to the buffer memory block 9 (hereinafter referred to as an address signal from the microcomputer IF block 11). More specifically, this address signal 17 is a write address signal to the transmission buffer 1 and a reception buffer group 2.
, status register group 3, transmission error register 4,
These are read address signals for the reception error register group 5d, source address register group 6d, and reply RSP register 7.

Reference numeral 18 in FIGS. 14 and 15 is a data signal of a transmission frame given from the microcomputer IF block 11 to the buffer memory block 9, and as shown in FIG. This is a write data signal (hereinafter referred to as a transmission write data signal).

Reference numeral 19 in FIGS. 14 and 16 is a signal for writing the transmission write data signal 18 into the address of the transmission buffer 1 designated by the address signal 17 from the microcomputer IF block 11 (hereinafter referred to as microcomputer IF block). 11).

Reference numeral 20 in FIGS. 14 and 15 indicates the read data signals ( (hereinafter referred to as a received read data signal), which is a data output signal of a received frame from the buffer memory block 9 to the microcomputer IF block 11, as shown in FIG.

Reference numeral 21 in FIG. 16 is a data number counter composed of a ternary up/down counter. This data number counter 21 counts up when writing to the reception buffer group 2 is completed, and counts down when reading from the reception buffer group 2 is completed, thereby increasing the number of frames existing in the reception buffer group 2. , and outputs the count value output signal 24.

Similarly, reference numeral 22 is a status number counter 22 composed of a quinary up/down counter. This status number counter 22 counts up the number of data existing in the status register group 3 by counting up when writing to the status register group 3 is completed and counting down when reading is completed. A count value output signal 30 is output.

Next, receive buffer group 2, status register group 3, transmit error register 4, receive error register group 5d, source address register group 6d, and reply R.
The configuration and general operation of the block that controls writing to the SP register 7 will be explained.

Reference numeral 23a is a first control unit that controls the input/output of data from the LAN IF block 10 side to the buffer memory block 9, and is controlled by the received write address signal 14, the received write signal 16, and the received write data signal 15. Generates write signals to receive buffer group 2, status register group 3, transmit error register 4, receive error register group 5d, source address register group 6d, and reply RSP register 7. 1st
The specific configuration of the control section 23a is shown in the block diagram of FIG.

The first control section 23a is composed of an address decoder 68, a first control circuit 70, a second control circuit 71, a third control circuit 72, AND gates 35a and 44a, an overrun detection circuit 69, etc. .

The address decoder 68 receives the received write address signal 14 provided from the LAN IF block 10.
A write address signal 68a to the reception buffer group 2, a write address signal 68b to the transmission error register 4, a write address signal 68c to the reception error register group 5d, a write address signal 68d to the source address register group 6d, and Reply RSP
It is output as a write address signal 68e to the register 7.

The first control circuit 70 generates a write signal 27 to the receive buffer group 2 (hereinafter referred to as a receive buffer write signal) according to the above-described write address signal 68a to the receive buffer group 2 and the receive write signal 16. . This reception buffer write signal 27 is generated when the count value of the data number counter 21 is "2", that is, when data has been written to both reception buffers 2a and 2b but has not been read. (hereinafter, this state is referred to as a receive buffer full state), it is not generated. Therefore, the first control circuit 70 has a signal (hereinafter referred to as a receive buffer full flag) that is set when the receive buffer is full.
79 is given from the data number counter 21.

The second control circuit 71 writes a write signal ( (hereinafter referred to as status write signal)
Generate 33. This status write signal 33 is sent when the count value of the status number counter 22 is "4", that is, all the status registers 3a, 3b,
It is not generated when data has been written to 3c and 3d but has not been read (hereinafter, this state is referred to as a status full state). For this reason, the second control circuit 71 is supplied with a signal 80 from the status number counter 22 that is set when the status is full (hereinafter referred to as a status full flag).

The second control circuit 71 also generates a signal indicating that writing to the status register group 3 is completed after the status write signal 33 is generated, that is, a status write completion signal 31. Furthermore, this status write completion signal 31 is given to the status number counter 22 as its up-count clock.

Reference numeral 35 is a write signal to the transmission error register 4 (hereinafter referred to as transmission error write signal)
is generated by ANDing the write address signal 68b from the address decoder 68 to the transmission error register 4 and the reception write signal 16 using the AND gate 35A.

Overrun detection circuit 69 detects overrun data in received write data signal 15 and generates overrun detection flag 81 after this overrun data is stored in the buffer memory.

The third control circuit 72 generates a write signal 37 (hereinafter referred to as reception error write signal) to the reception error register group 5d in accordance with the write address signal 68c to the reception error register and the reception write signal 16 described above. , a write signal 38 to be written to the source address register group 6d (hereinafter referred to as source address write signal) 38 is generated according to the write address signal 68d to be written to the source address register group 6d and the received write signal 16. This source address write signal 38 is not generated when the above-described overrun detection flag 81 and reception buffer full flag 79 are generated. For this reason, the third control circuit 72 is provided with the above-mentioned overrun detection flag 81 and reception buffer full flag 79.

Further, the third control circuit 72 generates a signal indicating that writing to the reception error register group 5d and source address register group 6d is completed after the reception error write signal 37 described above is generated, that is, a reception error write completion signal. A signal 39 is also generated.

Further, the third control circuit 72 outputs the reception buffer write completion signal 25 after the reception error write signal 37 is generated.
However, if the above-mentioned receive buffer full flag 79 is generated, this receive buffer write completion signal 2 is generated.
5 is not generated. Further, the above-mentioned receive buffer write completion signal 25 is given to the data number counter 21 as its up-count clock.

Reference numeral 44 is the reply RSP register 7
(hereinafter referred to as the reply RSP write signal), and is the write address signal 68e to the reply RSP register 7 output from the address decoder 68.
AND gate 44 and the received write signal 16.
It is generated by taking A

Reference numeral 26 in FIG. 16 indicates a receive buffer write signal 27 and a receive buffer write completion signal 2 generated by the first controller 23a.
5 is the receive buffer write pointer (hereinafter referred to as receive buffer WR pointer) that is input. The receive buffer WR pointer 26 receives the receive buffer write signal 27 from the first
Receive buffer group write signal switching to switch between a write signal 28 to the receive buffer 2a (hereinafter referred to as the first receive buffer write signal) and a write signal 29 to the second receive buffer 2b (hereinafter referred to as the second receive buffer write signal) It functions as a control block.

Reference numeral 32 in FIG. 16 indicates the first control section 23.
This is a status WR pointer to which the status write completion signal 31 and the status write signal 33 in which a is generated are input. This status WR pointer 32 converts the status write signal 33 into the status write completion signal 31.
The write signal to the first status register 3a is
(hereinafter referred to as the first status write signal) 34a;
Write signal to second status register 3b (hereinafter,
A write signal to the third status register 3c (hereinafter referred to as the third status write signal) 34c, and a write signal to the fourth status register 3d (hereinafter referred to as the fourth status write signal) 34b. ) 34d and functions as a status register group write signal switching control block.

Reference numeral 36 in FIG. 17 indicates the first control section 23.
This is a reception error WR pointer to which a reception error write completion signal 39, reception error write signal 37, and source address write signal 38 in which a has occurred are input. This reception error WR pointer 36 indicates the reception error write signal 37.
The reception error write completion signal 39 causes a write signal 40a to the first reception error register 5a (hereinafter referred to as the first reception error write signal) 40a and a write signal to the second reception error register 5b (hereinafter referred to as the second reception error 40b and a write signal (hereinafter referred to as the third reception error write signal) 40c to the third reception error register 5c, and the source address write signal 38 is switched to the first reception error write completion signal 39. Write signal to the source address register 6a (hereinafter referred to as the first
source address write signal) 41a and a write signal to the second source address register 6b (hereinafter referred to as the second
A reception error register group address switching control block and a source address register group write address switching control block that switches between the source address write signal) 41b and the write signal (hereinafter referred to as the third source address write signal) 41c to the third source address register 6c. It has both functions as a control block.

Next, write control to transmission buffer 1,
Reception buffer group 2, status register group 3, transmission error register 4, reception error register group 5d, source address register group 6d, and reply RSP register 7
The configuration and general operation of the block that performs read control will be described.

Reference numeral 23b is a second control unit that controls the input/output of data from the microcomputer IF block 11 side to the buffer memory block 9, and the address signal 17 from the microcomputer IF block 11 and the microcomputer IF block 11 A write signal 19 from the status register group 3 and read data (hereinafter referred to as status read data) 55 from the status register group 3 cause a write signal to the transmission buffer 1;
It generates read signals for the reception buffer group 2, status register group 3, transmission error register 4, reception error register group 5d, source address register group 6d, and reply RSP register 7.

The specific configuration of the second control section 23b is shown in FIG.
9 is shown in the block diagram.

The second control section 23b includes an address decoder 73, a control circuit 74, AND gates 45A, 6
It is composed of 5A, 78A, etc.

Address decoder 73 receives address signal 1 from microcomputer IF block 11.
7 is decoded to obtain the read address signal 48 of the receive buffer group 2, the read address signal 53 of the status register group 3, the read address signal 56 of the transmit error register 4, the read address signal 58 of the receive error register group 5d, and the read address signal 58 of the source address register group. 6d as a read address signal 59 and a reply RSP register 7 as a read address signal 63.

Reference numeral 45 is a write signal to the transmission buffer 1, which includes the write address signal 75 to the transmission buffer 1 outputted from the address decoder 73 and the write signal 1 outputted from the microcomputer IF block 11.
It is generated by performing a logical product with 9 using an AND gate 45A.

Further, this buffer memory includes a TX register write completion register 64 for detecting completion of writing to the transmission buffer 1. This T
The X register write completion register 64 stores that writing to the transmission buffer 1 has been completed by receiving a TX register write completion signal 65 to be described later, and outputs a transmission buffer full flag 66 to the LAN IF block 10.

When this transmission buffer full flag 66 is input, the LANIF block 10 monitors the state of the LAN transmission path and outputs the transmission read address signal 12 for reading the data string in the transmission buffer 1 at a certain timing. By doing so, the data strings in the transmission buffer 1 are sequentially read out.

[0126] Above-mentioned TX register write completion register 6
The TX register write completion signal 65 given to the TX register write completion signal 65 is the logical product of the write address signal 76 outputted from the address decoder 73 and the write signal 19 outputted from the microcomputer IF block 11.
By taking A, a write signal to the TX register write completion register 64, that is, a TX register write completion signal 65 is generated.

[0127] Also, in this buffer memory, there are a reception buffer group 2, a status register group 3, a transmission error register 4, a reception error register group 5d, a source address register group 6d), and a reply RSP register 7.
RX register read completion register 67 that stores the completion of reading (see FIG. 6, not shown in FIG. 15)
A write signal 78 to the RX register read completion register 67 (hereinafter referred to as RX register read completion signal) 78 is a write address signal 77 to the RX register read completion register 67 which is the output of the address decoder 73, and a microcomputer. It is generated by performing a logical product with the write signal 19 from the IF block 11 using an AND gate 78A.

The control circuit 74 controls the status register group 3.
When the RX register read completion signal 78 is input according to the contents of the status register data signal 55 input from A status read completion signal 51 indicating that the reception error register and source address register have been read is generated, and a reception error read completion signal 60 indicating that the reception error register and source address register have been read are generated.

Further, the reception buffer read completion signal 46 is sent to the data number counter 21 as a down clock, and the status read completion signal 51 is sent to the status number counter 21.
2 is given as its downclock.

In FIG. 16, reference numeral 47 is a receive buffer read pointer (hereinafter referred to as receive buffer (referred to as RD pointer). This reception buffer RD pointer 47 transfers the read address signal 48 to the reception buffer group 2 to the read address signal 49 (
(hereinafter referred to as the first reception buffer read address signal)
and a read address signal 50 to the second reception buffer 2b.
(Hereinafter referred to as the second reception buffer read address signal) It has a function as a reception buffer group read address switching control block that switches between the two.

Reference numeral 52 denotes a status R to which the status register read address signal 53 and status read completion 51 generated by the second control unit 23b are input.
It is a D pointer. This status RD pointer 52 converts the read address signal 53 of the status register into a read address signal (hereinafter referred to as the first status read address signal) 54a to the first status register 3a and a second status register 3b by the status read completion 51. A read address signal (hereinafter referred to as the second status read address signal) 54b to the third status register 3c, a read address signal (hereinafter referred to as the third status read address signal) 54c to the third status register 3c, and a read address signal to the fourth status register 3d. Read address signal (hereinafter referred to as 4th status read address signal)
It has a function as a status register group read address switching control block that switches between 54d and 54d.

Reference numeral 57 is a reception error RD pointer to which a reception error read completion signal 60, a reception error read address signal 58, and a source address read address signal 59 generated by the second control section 23b are input. This reception error RD pointer 57 indicates the reception error read address signal 58 and the reception error read completion signal 60.
As a result, a read address signal 61a to the first reception error register 5a (hereinafter referred to as the first reception error read address signal) and a read address signal 61a to the second reception error register 5b (hereinafter referred to as the second reception error read address signal) are generated. ) 61b and the third reception error register 5c
The source address read address signal 59 is switched to the read address signal (hereinafter referred to as the third reception error read address signal) 61c to the first source address register 6a by the reception error read completion signal 60. A read address signal (hereinafter referred to as the first source address read address signal) 62a to the second source address register 6b (hereinafter referred to as the second source address read address signal) 62b, and a write address to the third source address register 6c. It also functions as a reception error register group read address switching control block and a source address register group read address switching control block that switches to a signal (hereinafter referred to as the third source address read address signal) 62.

In FIG. 17, reference numeral 98O is an OR gate, which inputs an output signal 85 of a status management section 82 and an output signal 89 of a data number management section 86, which will be described later, and calculates the logical sum of both input signals. This signal is output as a reset signal 98 for the entire buffer memory.

Next, the buffer memory control system having the control means configured as described above causes certain buffers and registers in the buffer memory consisting of a plurality of buffers and registers to perform operations for storing data of the same attribute. ,
Some communication examples will be specifically explained with reference to the drawings.

20, 21, and 21 show the flow of data in the buffer memory during communication by the communication device of the present invention and the data stored in each buffer and register in the buffer memory in chronological order. This is a timing chart. In addition, in each of these communication examples, the states of the WR pointer and RD pointer indicating the state in which each data string is stored in each buffer and register, the write destination, and the read destination are shown in FIGS. 23, 24, 25, 26, Shown in FIGS. 27, 28, 29, 30, and 31. Note that FIG. 23 among these figures shows the state of the buffer memory in the initial state. Note that the lower side of FIG. 20 and the upper side of FIG. 21 are continuous, and the lower side of FIG. 21 and the upper side of FIG. 21 are continuous.

The communication examples shown in the timing charts of FIGS. 20, 21, and 21 are based on the LAN shown in FIG.
One frame of received write data input signal 15 from IF block 10, microcomputer IF block 1
There are a transmission write data input signal 18 and a transmission data output signal 13 for one frame from 1 to 1, and a reception write data input signal 15 for three frames, and then reception read data signals 20 of each frame are output in the order in which they were input. Indicates the state of

First, assume that the data string RI1 is input as the received write data signal 15, as shown in FIG. 20(d).

The data group RB1 of the received frame in the data string RI1 is input to the first reception buffer 2a as shown in FIG. 20(e), and only the source address data SAR1 is input to the first source as shown in FIG. 20(p). Data RE1, which is stored in the address register 6a and indicates the reception status in the data string RI1, is input to the first reception error register 5a as shown in FIG. 20(m), and the status data SR1
is the first status register 3 as shown in Figure 20(h).
The data is written to a and reception is completed.

Upon completion of reception of this data string RI1, the receive buffer write completion flag 25, as shown in FIG. 21(G), FIG. 21(C), and FIG.
A status write completion signal 31 and a reception error write completion signal 39 are output. Also, receive buffer WR pointer 2
6. Status WR pointer 32 and reception error WR
The pointer 36 is switched, and FIGS. 21(E) and 21
As shown in (A), the count value output signal 24 of the data number counter 21 becomes "1" and the count value output signal 30 of the status number counter 22 becomes "1".

The data storage state of the buffer memory at this point is as shown in FIG.

Next, as shown in FIG. 20(a), the data string T1 is input as the transmission write data signal 18, and as shown in FIG.
0(b), T1 is stored in the transmission buffer 1.

This data string T1 is transmitted to the LAN transmission path via the LAN IF block 10, as shown in FIG. 20(c). Thereafter, by the reception write signal 16 shown in FIG. 21(t), data TE1 indicating the transmission status of the data string T1 is stored in the transmission error register 4 as shown in FIG. 20(l). The RSP data TR1 returned from the device is shown in Figure 21 (s
) are written in the reply RSP register 7 as shown in FIG. Sending is completed.

[0143] Upon completion of transmission of this data string T1, as shown in FIG.
1(C), the status write completion signal 31
is issued, the status WR pointer 32 is switched,
As shown in FIG. 21(A), the count value output signal 30 of the status number counter 22 becomes "2".

The storage state of data in the buffer memory at this point is as shown in FIG.

Next, suppose that the data string RI2 is input as the received write data signal 15, as shown in FIG. 20(d).

The data group RB2 of the received frame in the data string RI1 is stored in the second reception buffer 2b as shown in FIG. 20(f), and only the source address data SAR2 is stored in the second reception buffer 2b as shown in FIG.
0(g) as shown in the second source address register 6b.
Then, data RE2 indicating the reception status in the data string RI2 is stored in the second reception error register 5b as shown in FIG. 20(n).
Then, the status data SR2 is input to the third status register 3c as shown in FIG. 20(j), and reception is completed.

Upon completion of reception of this data string RI2, as shown in FIGS. 21(G), 21(C), and 22(J), a receive buffer write complete signal 25, a status write complete signal 31, and a receive error write are generated. Completion 39 is output. Also, receive buffer WR pointer 2
6. Status WR pointer 32 and reception error WR
The pointer 36 is switched, and FIGS. 21(E) and 21
As shown in (F), the count value output signal 24 of the data number counter 21 becomes "2" and the reception buffer full flag 79 is set. Furthermore, as shown in FIG. 21(A),
The count value output signal 30 of the status number counter 22 becomes "3".

The storage state of data in the buffer memory at this point is as shown in FIG.

Next, suppose that data string RI3 is input as received write data, as shown in FIG. 20(d).

In this case, both reception buffers 2a and 2b of reception buffer group 2 are arranged as shown in FIGS. 20(e) and 20(f).
As shown in the figure, data has already been stored in both, but has not yet been read out. Therefore, as shown in FIG. 21(F), the receive buffer full flag 79 is set and the data string RI3 cannot be written to the receive buffers 2a and 2b. However, Fig. 21(r), Fig. 20(o)
, as shown in Figure 20(k), the data string R
Data SAR3 in I3 is input to the third source address register 6c, data RE3 is input to the third reception error register 5c, and data SR3 is input to the fourth status register 3d, thereby completing reception of the data string RI3.

Upon completion of reception of this data string RI3, a status write completion signal 31 and reception error write completion 39 are output as shown in FIGS. 21(C) and 22(J). Also, the status WR pointer 32 and the reception error WR pointer 36 are switched, and as shown in FIG. 21(E),
As shown in FIG. 21(B), the status number counter 22
The count value output signal 24 becomes "4" and the status full flag 80 is set. Also, data string RI
3, the receive buffer full flag 79 is set as shown in FIG. 21(F), so the data string RI
3, overrun data indicating that the data string RI3 itself is in an overrun state is written, and when the writing of the data string RI3 is completed, the overrun detection flag 81 is set as shown in FIG. 22(I). be done.

The storage state of data in the buffer memory at this point is as shown in FIG.

Assume that the data string RI4 is further input as received write data from the state shown in FIG. 27 as shown in FIG. 20(e).

In this case, data has already been stored in both reception buffers 2a and 2b of reception buffer group 2, and data has not yet been read out, as at the time when the above-mentioned data string RI3 was input. Therefore, since the receive buffer full flag 79 is set, the data string RI4 is not written to the receive buffers 2a and 2b. Furthermore, when the reception of the data string RI3 described above is completed, an overrun is detected in the data string RI3, and the overrun detection flag is set to 8.
Since 1 is set, data string RI4 is not written to any source address register or reception error register, and furthermore, data is stored in all status registers and status full flag 80 is set. Therefore, it will not be written to any status register. Therefore, the reception of the data string RI4 is not completed, and the reception buffer write completion signal 25, status write completion signal 31, and reception error write completion signal 39 are not output, and the reception buffer WR pointer 26, status WR pointer 32, and None of the receive error WR pointers 36 are toggled.

The data storage state of the buffer memory at this point remains as shown in FIG. 27.

[0156] As described above, the reception buffer group 2 and the status register group 3 are buffer groups and register groups each consisting of a plurality of buffers and registers.
, the reception error register group 5d, and the source address register group 6d, by simply specifying the addresses for the buffer group and the register group, without having to specify the addresses for the individual buffers and registers.
Each time a received frame is input, the addresses for the individual buffers and registers are switched in order and predetermined data is stored in each.

Furthermore, by sequentially switching the write destination for each received frame, in the case of the communication examples shown in the timing charts of FIGS. 20, 21, and 21, the first reception buffer 2a and the first reception error Register 5a, first source address register 6a, and first status register 3a
Data with the same attribute is stored as a set in the transmission buffer 1, transmission error register 4, reply RSP register 7, and second status register 3b, and data with the same attribute is stored as a set in the second reception buffer 2b. , second reception error register 5b and second source address register 6
data with the same attribute is stored as a set in the third reception error register 5c, the third source address register 6c, and the fourth status register 3d, and data with the same attribute is stored as a set in the third reception error register 5c, the third source address register 6c, and the fourth status register 3d. be done. As a result, each buffer and each register are associated with each other as described above, and data with the same attribute is always stored in each buffer.

[0158] Furthermore, when a new group of received data is input, if the data is already stored in the buffer or register that should store the data group and remains unread, the above management is not performed. Because this is done, the data will not be overwritten, and it is possible to always hold a set of data as data with the same attribute.

Next, as shown in FIG. 20(g), a series of data strings DATA-R1 having the same attribute as the one-frame reception buffer data input RI1 is received as the reception read data signal 2.
Suppose that it is read as 0.

After reading this series of data strings DATA-R1, the RX register read completion flag 78, which is a write signal to the RX register read completion register 67 indicating that the read has been completed, is output as shown in FIG. 22(L). 21(H), FIG. 21(D),
As shown in FIG. 22(K), a reception buffer read completion signal 46, a status read completion signal 51, and a reception error read completion signal 60 are output, and the reception buffer RD pointer 47, status RD pointer 52,
The reception error RD pointer 57 is switched.

At the same time, the count value output signal 24 of the data number counter 21 becomes "1" as shown in FIG. 21(E), and the count value output signal 30 of the status number counter 22 becomes "1" as shown in FIG. 21(A). It becomes 3”. Further, as shown in FIGS. 21(F) and 21(B), the receive buffer full flag 79 and status full flag 80 are reset. As a result, the first reception buffer 2a, the first status register 3a, the first reception error register 5a, and the first source address register 6a
are shown in Figure 20(e), Figure 20(h), Figure 20(m).
), and as shown in FIG. 20(p), writing becomes possible.

The storage state of data in the buffer memory at this point is as shown in FIG.

Next, 1 frame transmission write data input T
Assume that a series of data strings DATA-T1 indicating the same attribute as 1 is read out.

After reading this data string DATA-T1,
As shown in FIG. 22(L), the RX register read completion flag 78 is output, and it is determined that the data has the same attribute as the transmission write data T1 based on the contents of DATA-T1, and the status is read as shown in FIG. 21(D). Only the completion signal 51 is output. Then, the status RD pointer 35 is switched, and the second
Status register 3b becomes writable. at the same time,
The count value output signal 30 of the status number counter 22 becomes "2" as shown in FIG. 21(A).

The storage state of data in the buffer memory at this point is as shown in FIG.

Next, as shown in FIG. 20(g), a series of data strings DATA-R2 having the same attribute as the one-frame reception buffer data input RI2 is received as the reception read data signal 2.
Suppose that it is read to 0.

After reading this data string DATA-R2,
The RX register read completion flag 78 is output as shown in FIG. 22(L), and it is determined that the data has the same attribute as the received write data RI2 based on the contents of DATA-R2. D), Figure 22 (
K) A reception buffer read completion signal 46, a status read completion signal 51, and a reception error read completion signal 60 are output as shown in FIG. Then, receive buffer RD pointer 47, status RD pointer 52
, the reception error RD pointer 57 is switched, as shown in FIG.
0(f), Figure 20(j), Figure 20(n),
As shown in FIG. 20(q), the second reception buffer 2b, third status register 3c, second reception error register 5b, and second source address register 6b become writable. At the same time, the count value output signal 24 of the data number counter 21 is "0" as shown in FIG. 21(E).
”, and the count value output signal 30 of the status number counter 22 becomes “1” as shown in FIG. 21(A).

The data storage state of the buffer memory at this point is as shown in FIG.

Further, in the same manner as described above, suppose that a series of data strings DATA-R3 having the same attribute as the one-frame reception buffer data input RI3 is read out to the reception read data signal 20, as shown in FIG. 20(g).

After outputting this data string DATA-R3, the RX register read completion flag 78 is set as shown in FIG. 22(M), and the contents of DATA-R3 indicate that the data has the same attribute as the received write data RI3. be judged. Furthermore, since there is data indicating an overrun state in the data string RI3, as shown in FIGS. 21(D) and 22(K), the status read completion signal 51 and reception Only the error read completion signal 60 is output. Then, the status RD pointer 52 and reception error RD pointer 57 are switched,
Figure 20(k), Figure 20(o), Figure 21(r)
As shown in FIG. 4, the fourth status register 3d,
The third reception error register 5c and the third source address register 6c become writable. At the same time, the count value output signal 30 of the status number counter 22 becomes "0" as shown in FIG. 21(A).

The storage state of data in the buffer memory at this point is as shown in FIG.

[0172] As described above, the reception buffer group 2 and the status register group 3 are a buffer group and a register group each consisting of a plurality of buffers and registers.
, the reception error register group 5d, and the source address register group 6d, by simply specifying the addresses for the buffer group and register group, the addresses for the individual buffers and registers can be set to 1 without the need to specify the addresses for the individual buffers and registers. Switches every frame.

Furthermore, since the read destination is switched every frame, in the case of the communication examples shown in the timing charts of FIGS. 20, 21, and 21, the first reception buffer 2a and the first reception error register 5a are Data is read out as a set from the first source address register 6a and the first status register 3a as data with the same attribute, and data is read out from the transmission buffer 1, transmission error register 4, reply RSP register 7, and second status register 3b. Data with the same attribute is read out as a set, and data is read out as data with the same attribute as a set from the second reception buffer 2b, second reception error register 5b, second source address register 6b, and third status register 3c. , third reception error register 5c and third source address register 6
Data is read out as a set from c and fourth status register 3d as data having the same attribute. That is, the data stored in each buffer and each register are correlated and read out as a set of data with the same attribute.

By controlling and managing the buffer memory as described above, certain buffers and registers within the buffer memory consisting of a plurality of buffer memories and registers act as buffers and registers that store data of the same attribute.

Next, the control of the buffer memory by the status number counter 22 described above will be explained.

FIG. 32 is a block diagram showing a configuration for controlling the status number counter 22 and the status register group 3.

[0177] Reference numeral 82 is a status management section;
Count value output signal 30 of status number counter 22,
A status write completion signal 31, a status read completion signal 51, an output signal 83 of the status RD pointer 52 which is a ternary counter, and an output signal 84 of the status WR pointer 32 which is a ternary counter are input. The status management section 82 outputs a status number management output signal 85 to the aforementioned OR gate 98O.

[0178] The status management unit 82 stores the status WR
The value of the output signal 84 of the pointer 32 is "L", and the value of the output signal 83 of the status RD pointer 52 is "M".
When the value of the count value output signal 30 of the status number counter 22 is "N", if N+M≦4, it is determined whether N+M=L. Further, if N+M≧5, it is determined whether N+M-4=L.

In either case, if the equal sign is established, "0" is output as the status number management output signal 85, and if not, "1" is output.

[0180] In the explanation of this embodiment, for convenience of explanation, the values of N and M are both set to "1" in the output values of the status WR pointer 32 and the status RD pointer 52.
” to explain.

The operation of the status management section 82 will be explained below with reference to the timing chart of FIG. 33.

Each time data writing to the status register group 3 is completed, a status writing completion signal 31 shown in FIG. 33(a) is output. After this status write completion signal 31 is output, the output signal 8 of the status WR pointer 32 shown in FIG. 33(c)
4 (=L) is added by "1". However, since the output signal 84 of this status WR pointer 32 does not take a value higher than "4", it returns to the initial state of "1" after the status write completion signal 31 which is a multiple of "4" is output from the initial state. .

Similarly, each time data reading from the status register group 3 is completed, a status reading completion signal 51 shown in FIG. 33(b) is output. After this status read completion signal 51 is output, the status RD pointer 5 shown in FIG. 33(d)
"1" is added to the output signal 83 (=M) of No. 2. However, since the output signal 83 of this status RD pointer 52 does not take a value higher than "4", it is "4" from the initial state.
After the status read completion signal 51 which is a multiple of is output, it returns to the initial state of "1".

The count value output signal 30 (=N) of the status number counter 22 shown in FIG.
1” is added, and “1” is subtracted by the output of the status read completion signal 51.

From the above relationship, the count value output signal 30 of the status number counter 22, which is “N”, is “L”.
” is the output signal 84 of the status WR pointer 32,
The following relational expressions (1) and (2) hold between the output signals 83 of the status RD pointer 52 that are "M". M+N=L (M+N≦4) …(1) M+N-4
=L (M+N≧4) …(2)

For example, considering time A in FIG. 33, the status write completion signal 31 has already been generated twice, so the value "L" of the output signal 84 of the status WR pointer 32 is "3". Also, since the status read completion signal 51 has already been generated once, the value "M" of the output signal 83 of the status RD pointer 52 is "2".

Furthermore, at this point, the count value output signal 30 of the status number counter 22 has been added twice and subtracted once, so its value "N" is "1". Therefore, "L", "M", and "N" are "3", "2", and "1", respectively, and satisfy the above formula (1).

Next, considering time B in FIG. 33,
Since the status write completion signal 31 has already been generated five times, the value "L" of the output signal 84 of the status WR pointer 32 is "2", and the status read completion signal 51 has already been generated twice. Therefore, the value "M" of the output signal 83 of the status RD pointer 52 is "3". Also, at this point, the count value output signal 30 of the status number counter 22 has been added five times and subtracted two times, so the value "N" is "
3". Therefore, "L", "M", and "N" are "2", "3", and "3", respectively.
The above formula (2) is satisfied.

[0189] The status management section 82 performs the above-mentioned determination, but more specifically performs the following operations.

Reference numeral 82C in FIG. 33 is a clock generated by the status management unit 82, and is generated when either the status write completion signal 31 or the status read completion signal 51 is input to the status management unit 82. Then, the status management section 82 executes the above equations (1) and (2) in synchronization with the generation of this clock 82C.
) is determined whether the values of each signal 30, 83, 84 are satisfied or not, and if it is satisfied, "0" is outputted, and if not, "1" is outputted as the status number management output signal 85.

Status number management output signal 85 is sent to OR gate 98O to generate buffer memory reset signal 98, as described above.

Next, the control of the buffer memory by the data number counter 21 described above will be explained.

FIG. 34 is a block diagram showing a configuration for controlling the data number counter 21 and the reception buffer group 2. As shown in FIG.

Reference numeral 86 is a data number management unit, which controls the count value output signal 24 of the data number counter 21, the reception buffer write completion signal 25, the reception buffer read completion signal 46, and the reception buffer RD pointer 47 which is a binary counter. An output signal 87 and an output signal 88 of the reception buffer WR pointer 26, which is a binary counter, are input. The data number management section 86 outputs a data number management output signal 89 to the aforementioned OR gate 98O.

[0195] The data number management section 86 manages the reception buffer WR.
The value of the output signal 88 of the pointer 26 is "I", and the value of the output signal 87 of the reception buffer RD pointer 47 is "J".
and the count value output signal 2 of the data number counter 21
When the value of 4 is "K", if J+K≦2, it is determined whether J+K=I. Moreover, if J+K≧3, it is determined whether J+K-2=I.

In either case, if the equal sign is established, "0" is output as the data number management output signal 89, and if not, "1" is output.

In the explanation of this embodiment, for convenience of explanation, the values of I and J will be explained by adding "1" to the output values of the reception buffer RD pointer 47 and the reception buffer WR pointer 26. .

The operation of the data number management section 86 will be explained below with reference to the timing chart of FIG.

Each time data writing to the receiving buffer group 2 is completed, a receiving buffer writing completion signal 25 shown in FIG. 35(a) is output. After this receive buffer write completion signal 25 is output, the output signal 8 of the receive buffer WR pointer 26 shown in FIG. 35(c)
8 (=L) is added by "1". However, since the output signal 88 of this receive buffer WR pointer 26 does not take a value greater than "2", it changes from the initial state to "1" after the receive buffer write completion signal 25 which is a multiple of "2" is output. Return to

Similarly, each time data writing to the receiving buffer group 2 is completed, a receiving buffer read completion signal 46 shown in FIG. 35(b) is output. After this receive buffer read completion signal 46 is output, as shown in FIG.
(d) Receive buffer RD pointer 47 shown in
"1" is added to the output signal 87 (=J). However, since the output signal 87 of this reception buffer RD pointer 47 does not take a value of "2" or more, it is set to "2" from the initial state.
After the receive buffer read completion signal 46 which is a multiple of is output, it returns to the initial state of "1".

The count value output signal 24 (=K) of the data number counter 21 shown in FIG.
" is added, and "1" is subtracted by the output of the reception buffer read completion signal 46. From the above relationship, the data number counter 21 that is "K"
The following relational expression holds between the count value output signal 24 of , the output signal 88 of the reception buffer WR pointer 26 which is "I", and the output signal 87 of the reception buffer RD pointer 47 which is "J". J+K=I (J+K≦2) …(3) J+K-2
=I (J+K≧2) …(4)

For example, considering time C in FIG. 35, the receive buffer write completion signal 25 has already been generated once, so the value of the output signal 88 of the receive buffer WR pointer 26 is "I".
is "2", and the receive buffer read completion signal 46 has already been generated once, so the value "J" of the output signal 87 of the receive buffer RD pointer 47 is "2".
" It has become.

[0203] Also, at this point, the data number counter 21
Since the count value output signal 24 has been subjected to one addition and one subtraction, its value "K" is "0". Therefore, “I”, “J”, and “K” are respectively”
1”, “1”, “0”, and the above formula (3
) satisfies.

Next, considering time D in FIG. 35,
Since the reception buffer write completion signal 25 has already been generated five times, the output signal 8 of the reception buffer WR pointer 26
Since the value "I" of 8 is "2" and the receive buffer read completion signal 46 has already been generated three times, the value of the output signal 87 of the receive buffer RD pointer 47 is "2".
J” is “2”.

[0205] Also, at this point, the data number counter 21
Since the count value output signal 24 has been added five times and subtracted three times, its value "K" is "2". Therefore, “I”, “J”, and “K” are respectively”
2”, “2”, “2”, and the above formula (3
) satisfies.

[0206] The data number management unit 86 makes the above-mentioned determination, but more specifically performs the following operations.

Reference numeral 86C in FIG. 35 is a clock generated by the data number management section 86.
It is generated when either the receive buffer write completion signal 25 or the receive buffer read completion signal 46 is input to the input buffer. Then, the data number management section 86 uses this clock 8.
In synchronization with the occurrence of 6C, the above equations (3) and (4)
It is determined whether the values of the signals 24, 87, and 88 satisfy, and if so, "0" is output as the data number management output signal 89, and if not, "1" is output as the data number management output signal 89.

The data number management output signal 89 is as described above.
O to generate the buffer memory reset signal 98
Sent to R gate 98O.

Therefore, the buffer memory reset signal 9
8, when either the status number management output signal 85 or the data number management output signal 89 is "1", that is, the status number counter 22 or the data number counter 21
If the count value of 1 is incorrect, or if both count values are incorrect, it becomes the active level "1" and resets the entire buffer memory.

[0210] Next, a case will be described in which the buffer memory configured as described above is connected to a microcomputer via a parallel bus.

FIG. 36 is a block diagram showing the configuration when the communication device 8 of the present invention and the microcomputer 91 are connected via a parallel bus.

In FIG. 36, reference numeral 300 is a data bus, 301 is an address bus, 302 is a write strobe signal, 303 is a read strobe signal, and 310 is a TX register write completion register 64 and RX register readout in the buffer memory block 9. Areas other than the completion register 67 are shown.

FIG. 37 is a timing chart showing the states of data and signals when writing data from the microcomputer 91 to the buffer memory block 9.

The data bus 300 is connected from the microcomputer 91 to the buffer memory block 9 as shown in FIG. 37(a).
As shown in the data strings “03”, “F2”, “01”
", "AA", "55", and "FF" are output. These respective data are output as addresses "00" and "," which are output to the address bus 301 as shown in FIG. 37(b).
01", "02", "03", "04", "7
37(d) in the buffer memory area corresponding to “E”.
The write strobe signal 302 is stored in synchronization with the timing of the write strobe signal 302 shown in FIG.

[0215] In this example, the addresses "00", "01", "02",
“03” and “04” are allocated to the transmission buffer 1 in the area referenced 310 in the buffer memory block 9. Therefore, the data "03", "F2", "01", "AA" corresponding to each address signal
", "55" are stored in each address area of the transmission buffer 1. Since the address "7E" is assigned to the TX register write completion register 64, the data "FF" corresponding to the address signal "7E" is stored in the TX register write completion register 64.

That is, when each data of the transmission data string is stored in each area of the transmission buffer 1, data indicating that writing of the transmission data string has been completed is written to the TX register write completion register 64 at the end. By this, the buffer memory block 9 is transferred from the microcomputer 91.
The process of writing the transmission data string to is completed. The operation in buffer memory block 9 after writing data to address "7E" is as described above.

FIG. 38 is a timing chart showing the states of data and signals when the received data group stored in buffer memory block 9 is read to microcomputer 91.

The data bus 300 is connected from the microcomputer 91 to the buffer memory block 9 as shown in FIG. 38(b).
As shown in the figure, the addresses “30”, “10”, “11”, “12”, ” are output to the address bus 301.
13'', ``14'', and ``7F'' are output.The data stored in the area of the buffer memory corresponding to each of these address signals is determined by the timing of the read strobe signal 303 shown in FIG. 38(c). in sync with
As shown in Figure 38(a), “0C”, “03”, “
F2'', ``01'', ``AA'', and ``55'' are read out in this order and read into the microcomputer 91. At this time, the read strobe signal 303 is set to the address signal ``5''.
5” and is output only in response to the address signal “7F”.
”, the write strobe signal 302 is output. At the same time, the microcomputer 91 outputs the data bus 3.
Since the data "FF" is output to 00, this data "
FF" is stored in the RX register read completion register 67 to which address "7F" is assigned.

That is, after each data of the received data string is read from each area of one of the receive buffers 2a and 2b of the receive buffer group 2, data indicating that reading of the received data string has been completed is read out from the RX register. By writing to the completion register 67, the process of reading the received data string from the buffer memory block 9 to the microcomputer 91 is completed. The operation in buffer memory block 9 after writing data to address "7F" is as described above.

[0220]

As described above in detail, in the communication device of the present invention, the address of the buffer memory specifies one of a plurality of transmitting buffers and receiving buffers using the upper bits, and the address within each buffer is specified using the lower bits. It is allocated to sequentially specify each storage area, and has a counter that automatically generates the lower bits in sequence when the upper bits of the address are given, and the higher bits are assigned from the outside. The present invention is equipped with an address generating means that can access each storage area of one buffer of the buffer memory with address allocation as described above by outputting the bit and the lower bit generated by the counter as an address signal. , each buffer is specified and each storage area within that buffer is accessed by simply providing the upper bits of the address from the outside.

Furthermore, in the communication device of the present invention, when information to be transmitted or information to be received is stored in each buffer, the number of storage areas used to store the information is stored in the first storage area. Therefore, when information is read from each buffer, the number of storage areas that actually need to be read is known at the time the first data of that information is read, and this value and the lower bit address signal mentioned above are used. By comparing the output value of the counter that outputs the information each time the information is read,
If they match, reading of information is stopped.

Furthermore, in the communication device of the present invention, when information to be received is stored in each buffer, the information is stored in the storage area next to the last storage area used for storing the information.
Since the CRC check data is stored, it becomes possible for the receiving side to compare the CRC data generated at the time of transmitting the information with the CRC data generated for the received data again.

[Brief explanation of drawings]

FIG. 1 is a block diagram schematically showing the configuration of a buffer memory of a communication device according to the present invention.

FIG. 2 is a schematic diagram showing a specific configuration of a buffer memory of the communication device of the present invention.

FIG. 3 is a schematic diagram showing a specific configuration of a buffer memory of the communication device of the present invention.

FIG. 4 is a block diagram showing the overall configuration of a communication device of the present invention.

FIG. 5 is a schematic diagram showing the address structure of a sending buffer and a receiving buffer group of the buffer memory of the communication device of the present invention.

FIG. 6 is a schematic diagram showing the address structure of a portion of the buffer memory of the communication device of the present invention other than the transmission buffer and reception buffer group.

FIG. 7 is a schematic diagram showing data constituting a transmission frame stored in a transmission buffer and its arrangement.

FIG. 8 is a schematic diagram showing data and data arrangement of a received frame stored in a reception buffer.

FIG. 9 is a block diagram showing the configuration of main parts of an address generation mechanism including a transmission buffer and a group of reception buffers.

10 is a timing chart showing the state of output signals of each component in the block diagram of FIG. 9 and the state of writing data to a transmission buffer; FIG.

11 is a flowchart showing the state of output signals of each component in the block diagram of FIG. 9 and the procedure for writing data to a transmission buffer; FIG.

FIG. 12 is a block diagram showing a configuration when two sets of communication devices of the present invention are connected to a LAN transmission path and communicate with each other.

FIG. 13 is a schematic diagram showing a state when a received frame in which the communication data group is 5 bytes is stored in the first reception buffer.

FIG. 14 is a schematic diagram showing the input/output relationship of address signals and data signals within the communication device of the present invention.

FIG. 15 is a schematic diagram showing the relationship between input and output of data to and from the buffer memory.

FIG. 16 is a schematic diagram mainly showing the input/output relationship of control signals and address signals of the buffer memory.

FIG. 17 is a schematic diagram mainly showing the input/output relationship of control signals and address signals of the buffer memory.

FIG. 18 is a block diagram showing a specific configuration of a first control section.

FIG. 19 is a block diagram showing a specific configuration of a second control section.

FIG. 20 is a timing chart showing the flow of data in the buffer memory during communication by the communication device of the present invention and the data stored in each buffer and register in the buffer memory in chronological order.

FIG. 21 is a timing chart showing, in chronological order, the flow of data in the buffer memory and data stored in each buffer and register in the buffer memory during communication by the communication device of the present invention.

FIG. 22 is a timing chart showing, in chronological order, the flow of data in the buffer memory and data stored in each buffer and register in the buffer memory during communication by the communication device of the present invention.

[Figure 23] WR indicating the state in which each data string is stored in each buffer and register during communication, and the write destination and read destination
It is a schematic diagram which shows the state of a pointer and RD pointer.

[Figure 24] WR indicating the state in which each data string is stored in each buffer and register during communication, and the write destination and read destination
It is a schematic diagram which shows the state of a pointer and RD pointer.

[Figure 25] WR indicating the state in which each data string is stored in each buffer and register during communication, and the write destination and read destination
It is a schematic diagram which shows the state of a pointer and RD pointer.

[Figure 26] WR indicating the state in which each data string is stored in each buffer and register during communication, and the write destination and read destination
It is a schematic diagram which shows the state of a pointer and RD pointer.

[Figure 27] WR indicating the state in which each data string is stored in each buffer and register during communication, and the write destination and read destination
It is a schematic diagram which shows the state of a pointer and RD pointer.

[Figure 28] WR indicating the state in which each data string is stored in each buffer and register during communication, and the write destination and read destination
It is a schematic diagram which shows the state of a pointer and RD pointer.

[Figure 29] WR indicating the state where each data string is stored in each buffer and register during communication, and the write destination and read destination
It is a schematic diagram which shows the state of a pointer and RD pointer.

[Figure 30] WR indicating the state in which each data string is stored in each buffer and register and the write destination and read destination during communication
It is a schematic diagram which shows the state of a pointer and RD pointer.

[Figure 31] WR indicating the state in which each data string is stored in each buffer and register during communication, and the write destination and read destination
It is a schematic diagram which shows the state of a pointer and RD pointer.

FIG. 32 is a block diagram showing a configuration for controlling a status number counter and a group of status registers.

FIG. 33 is a timing chart illustrating the operation of the status management section.

FIG. 34 is a block diagram showing a configuration for controlling a data number counter and a reception buffer group.

FIG. 35 is a timing chart illustrating the operation of the data number management section.

FIG. 36 is a block diagram showing a configuration when a communication device of the present invention and a microcomputer are connected via a parallel bus.

FIG. 37 is a timing chart showing the states of data and signals when writing data from a microcomputer to a buffer memory block.

FIG. 38 is a timing chart showing data and signal states when a received data group stored in a buffer memory block is read to a microcomputer.

[Explanation of symbols]

1 Transmission buffer 2a First reception buffer 2b Second reception buffer 2 Reception buffer group 3a First status register 3b Second status register 3c Third status register 3d Fourth status register 3 Status register group 4 Transmission error register 5a First reception error Register 5b Second reception error register 5c Third reception error register 5d Reception error register group 6a First source address register 6b
Second source address register 6c Third source address register 6d Source address register group 7 Reply RSP register 8 Communication device 9 Buffer memory block 100 Transmitted data group 101 Message length field 150 Decoder 151 Counter 160 Decoder 161 Counter 200 Received data group 201 Message length Field 203 CRC field

Claims (6)

[Claims] Claim 1: n transmission buffers each storing one unit of information to be transmitted to another communication device, and m each storing one unit of information to be received from another communication device.
information to be transmitted to another communication device is temporarily stored in the transmission buffer and then transmitted to the outside, and information to be received from the other communication device is temporarily stored in the reception buffer. In a communication device configured to receive data after storing, each of the transmission buffers has a storage area for storing each of a plurality of pieces of data constituting one unit of information to be transmitted, and each storage area is 1. A communication device characterized in that an address is assigned so as to designate one of the buffers and sequentially designate all areas within each buffer using lower bits. Claim 2: n transmission buffers each storing one unit of information to be transmitted to another communication device, and m each storing one unit of information to be received from another communication device.
information to be transmitted to another communication device is temporarily stored in the transmission buffer and then transmitted to the outside, and information to be received from the other communication device is temporarily stored in the reception buffer. In a communication device configured to receive data after storing, each of the receiving buffers has a storage area for storing each of a plurality of pieces of data constituting one unit of information to be received, and each storage area is configured to receive information by upper bits. 1. A communication device characterized in that an address is assigned so as to designate one of the buffers and sequentially designate all areas within each buffer using lower bits. Claim: n transmission buffers each storing one unit of information to be transmitted to another communication device, and m each storing one unit of information to be received from another communication device.
information to be transmitted to another communication device is temporarily stored in the transmission buffer and then transmitted to the outside, and information to be received from the other communication device is temporarily stored in the reception buffer. In the communication device configured to receive data after storing the data, each of the sending buffer and the receiving buffer has a storage area for storing each of a plurality of pieces of data constituting one unit of information to be transmitted and one unit of information to be received. Each storage area is characterized in that addresses are assigned such that the upper bits specify one of the buffers and the lower bits sequentially specify all of the areas within each buffer. communication equipment. 4. The communication device according to claim 3, further comprising a counting means that is activated when a signal of the upper bits of an address is applied from the outside and outputs a sequentially incremented value. 1. A communication device comprising address generating means for outputting a generated count value signal as lower bits of an address together with the upper bit signal. 5. n transmission buffers each storing one unit of information to be transmitted to another communication device, and m each storing one unit of information to be received from another communication device.
information to be transmitted to another communication device is temporarily stored in the transmission buffer and then transmitted to the outside, and information to be received from the other communication device is temporarily stored in the reception buffer. In the communication device configured to receive data after storing the data, each of the transmitting buffer and the receiving buffer has a storage area for storing a plurality of data constituting one unit of information to be transmitted and one unit of information to be received, respectively. 1. A communication device comprising: a storage area at the head of each buffer to store the number of areas used by information stored in each buffer. 6. n transmission buffers each storing one unit of information to be transmitted to another communication device, and m each storing one unit of information to be received from another communication device.
information to be transmitted to another communication device is temporarily stored in the transmission buffer and then transmitted to the outside, and information to be received from the other communication device is temporarily stored in the reception buffer. In a communication device configured to receive data after storing, each of the receiving buffers has a storage area for storing each of a plurality of pieces of data constituting one unit of information to be received, and the receiving buffer stored in each receiving buffer A communication device characterized in that CRC check information of the information to be processed is stored in an area next to the area in which the last data of the information to be processed is stored.