JPH04309241A - Manufacture of ii-vi compound semiconductor thin film - Google Patents

Manufacture of ii-vi compound semiconductor thin film

Info

Publication number
JPH04309241A
JPH04309241A JP7508391A JP7508391A JPH04309241A JP H04309241 A JPH04309241 A JP H04309241A JP 7508391 A JP7508391 A JP 7508391A JP 7508391 A JP7508391 A JP 7508391A JP H04309241 A JPH04309241 A JP H04309241A
Authority
JP
Japan
Prior art keywords
group
elements
compound semiconductor
thin film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7508391A
Other languages
Japanese (ja)
Inventor
Hiroshi Kawanami
博 河南
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP7508391A priority Critical patent/JPH04309241A/en
Publication of JPH04309241A publication Critical patent/JPH04309241A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate the etching of a substrate, by supplying group VI element material prior to group II element material, when a II-VI compound semiconductor thin film is selectively crystal-growth on the III-V compound semiconductor substrate by an organic metal vapor growth method. CONSTITUTION:When a II-VI compound semiconductor thin film 203 is crystal- growth on a III-VI compound semiconductor substrate 202 by an metal organic vapor deposition method, group VI elements are supplied prior to group II element. Hence, when the group II elements enter a reaction tube, the group VI elements surely exits, so that the group II element. Hence, when the group II elements surely exist VI elements, and the reaction of the group II elements with group III elements or group V elements is restrained. Further the surface of the III-V compound semiconductor substrate 202 is covered with the group VI elements, so that the reaction of the group II elements with the group III elements or the group V elements is also restrained. Thereby the etching of the substrate can be eliminated.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、II−VI族化合物半
導体薄膜の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a II-VI compound semiconductor thin film.

【0002】0002

【従来の技術】II−VI族化合物半導体薄膜の製造方
法としては有機金属気相成長法(以下、MOVPE法と
称する)、分子線エピタキシー法(以下、MBEと称す
る。)等があるが、近年原料純度の向上および装置の簡
便さから、前者MOVPE法が急速に普及してきた。こ
こでMOVPE法の原料としては一般に、II族元素原
料としてII族元素の有機金属が用いられ、VI族元素
原料としてVI族元素の水素化物が用いられてきた。と
ころがVI族元素の水素化物は毒性が強く使用に際して
は十分な安全対策と細心の注意が必要であった。これに
対し水素化物より毒性の低い有機金属の開発が進められ
、また純度の面からも半導体原料として使用に耐え得る
ものがでてきたことにより、これらVI族元素原料にお
いても有機金属を用いるようになってきている。
[Prior Art] Methods for manufacturing II-VI group compound semiconductor thin films include metal organic vapor phase epitaxy (hereinafter referred to as MOVPE) and molecular beam epitaxy (hereinafter referred to as MBE). The former MOVPE method has rapidly become popular due to improved raw material purity and simplicity of equipment. As raw materials for the MOVPE method, organic metals of group II elements have generally been used as raw materials for group II elements, and hydrides of group VI elements have been used as raw materials for group VI elements. However, hydrides of group VI elements are highly toxic and require sufficient safety measures and extreme caution when used. In response, progress has been made in the development of organic metals that are less toxic than hydrides, and with the emergence of products that can withstand use as raw materials for semiconductors in terms of purity, organic metals are also being used as raw materials for these Group VI elements. It is becoming.

【0003】0003

【発明が解決しようとする課題】ところが従来の技術に
記載のVI族の有機金属は同一元素の水素化物より反応
性が低く、これをII−VI族化合物半導体薄膜の原料
として使用した場合、III−V族化合物半導体基板上
にII−VI族化合物が形成される前にII族元素とI
II族元素あるいはV族元素が反応脱離し基板がエッチ
ングされるといった現象がある。
[Problems to be Solved by the Invention] However, the group VI organic metals described in the prior art have lower reactivity than the hydrides of the same element, and when used as a raw material for a group II-VI compound semiconductor thin film, - Group II elements and I before forming a Group II-VI compound on a Group V compound semiconductor substrate
There is a phenomenon in which a group II element or a group V element reacts and desorbs, and the substrate is etched.

【0004】この現象を図3に示す。ここで(301)
はSiO2 を、(302)は半絶縁性のGaAs基板
を、(303)はII−VI族化合物半導体薄膜層を示
す。(301)上には(303)は結晶成長せず、選択
的に(302)上のみに結晶成長する。この際、II族
元素の原料ガスによるエッチングで結晶成長の前後でメ
サ形状が変化してしまっていることがわかる。この原料
ガスによる基板のエッチングという現象は、SiO2 
等によりマスクパターンが形成されたIII−V族化合
物半導体基板上の選択的結晶成長時に微細なパターンが
形成できないといった問題点をするだけでなく、II族
元素とIII族元素あるいはV族元素の反応生成物がI
I−VI族化合物半導体薄膜中に取り込まれる可能性も
あり、これは結晶界面の急峻性を低下させることになり
デバイス応用の面からも好ましくない現象である。
This phenomenon is shown in FIG. Here (301)
indicates SiO2, (302) indicates a semi-insulating GaAs substrate, and (303) indicates a II-VI group compound semiconductor thin film layer. Crystals of (303) do not grow on (301), but crystals grow selectively only on (302). At this time, it can be seen that the mesa shape changes before and after crystal growth due to etching with the group II element source gas. The phenomenon of substrate etching by this raw material gas is caused by SiO2
In addition to the problem of not being able to form a fine pattern during selective crystal growth on a III-V compound semiconductor substrate with a mask pattern formed thereon, there is also the problem of reactions between group II elements and group III elements or group V elements. The product is I
There is also a possibility that it may be incorporated into the I-VI group compound semiconductor thin film, which reduces the steepness of the crystal interface and is an undesirable phenomenon from the viewpoint of device applications.

【0005】本発明は以上の課題に鑑みなされたもので
、その目的は、MOVPE法によるII−VI族化合物
半導体薄膜形成時の基板となるIII−V族化合物半導
体のII族元素原料ガスによるエッチングを抑制した製
造方法を提供するところにある。
The present invention has been made in view of the above-mentioned problems, and its purpose is to improve etching of a III-V compound semiconductor, which is a substrate during formation of a II-VI compound semiconductor thin film by MOVPE, using a group II element raw material gas. The purpose of the present invention is to provide a manufacturing method that suppresses this.

【0006】[0006]

【課題を解決するための手段】本発明によれば、III
−V族化合物半導体基板上に有機金属気相成長法にてI
I−VI族化合物半導体薄膜を結晶成長させる際、VI
族元素原料の供給をII族元素原料に時間的に先行させ
ることとした。
[Means for Solving the Problems] According to the present invention, III.
- I by organometallic vapor phase epitaxy on a group V compound semiconductor substrate
When crystal-growing an I-VI group compound semiconductor thin film, VI
It was decided that the group element raw material was supplied temporally before the group II element raw material.

【0007】[0007]

【作用】本発明によれば、III−V族化合物半導体基
板上に有機金属気相成長法にてII−VI族化合物半導
体薄膜を結晶成長させる際、VI族元素原料をII族元
素原料に時間的に先行させ供給することとしたことによ
り、II族元素が反応管中に入ってきた時点で必ずVI
元素が存在することで、II族元素は直ちにVI元素と
反応し、II族元素とIII族元素あるいはV族元素の
反応が抑制され、従って基板がエッチングされるといっ
た現象がなくなる。さらにVI族元素をII族元素に先
行して供給することにより、III−V族化合物半導体
基板表面がVI族元素に覆われて、これによってもII
族元素とIII族元素あるいはV族元素の反応が抑制さ
れ、従って基板がエッチングされるといった現象がなく
なる。
[Operation] According to the present invention, when crystal-growing a II-VI group compound semiconductor thin film on a III-V group compound semiconductor substrate by organometallic vapor phase epitaxy, the group VI element raw material is mixed with the group II element raw material over a period of time. By supplying the Group II elements in advance, the Group VI element is always supplied when it enters the reaction tube.
Due to the presence of the element, the group II element immediately reacts with the VI element, and the reaction between the group II element and the group III element or the group V element is suppressed, thereby eliminating the phenomenon that the substrate is etched. Furthermore, by supplying the Group VI element before the Group II element, the surface of the III-V group compound semiconductor substrate is covered with the Group VI element, and thereby the Group II element is also supplied.
The reaction between group elements and group III elements or group V elements is suppressed, and therefore the phenomenon of etching of the substrate is eliminated.

【0008】[0008]

【実施例】図1に本発明の実施例における原料供給のタ
イムチャートを示す。
Embodiment FIG. 1 shows a time chart of raw material supply in an embodiment of the present invention.

【0009】図2に本発明の実施例による結晶成長基板
の断面図を示す。
FIG. 2 shows a cross-sectional view of a crystal growth substrate according to an embodiment of the present invention.

【0010】以下にその実施例の詳細を述べる。[0010] The details of the embodiment will be described below.

【0011】半絶縁性GaAs基板(202)上にSi
O2 (201)をモノシランを原料とした通常の熱C
VD法により形成し、後に、該SiO2 (201)を
通常のフォトリソ工程によりパターンニングした。Si
O2 (201)のパターンニングにより一部GaAs
の露出した基板を硫酸系エッチング液にて処理すること
により、SiO2 パターンに沿ったパターンにGaA
s基板(202)を掘り下げた。以上の操作により処理
した基板をMOVPE法の反応管内にセットし結晶成長
を行なった。II族元素原料としてジメチル亜鉛(以下
、DMZnと称する。)、VI族元素としてジメチルセ
レナイド(以下、DMSeと称する。)を用いた。基板
温度は550℃、成長圧力は80Torrとした。DM
Znの供給量は30μmol/min、DMSeの供給
量は120μmol/minとした。原料ガス供給の時
間軸に沿ったタイミングは図1に示す通りである。DM
Seの供給をDMZnの供給に2秒先行させて行なった
。このようにして作成されたセレン化亜鉛(以下、Zn
Seと称する。)層(203)成長基板の断面図は図2
に示してある。図からわかるように、結晶成長の前後で
メサ形状が保存されており、原料ガスによるエッチング
が抑制されていることがわかる。
Si on the semi-insulating GaAs substrate (202)
Ordinary thermal C using O2 (201) as monosilane raw material
It was formed by the VD method, and later the SiO2 (201) was patterned by a normal photolithography process. Si
By patterning O2 (201), some GaAs
By treating the exposed substrate with a sulfuric acid-based etching solution, GaA is formed in a pattern along the SiO2 pattern.
The s substrate (202) was dug. The substrate treated by the above operations was placed in a reaction tube of the MOVPE method, and crystal growth was performed. Dimethyl zinc (hereinafter referred to as DMZn) was used as a group II element raw material, and dimethyl selenide (hereinafter referred to as DMSe) was used as a group VI element. The substrate temperature was 550° C. and the growth pressure was 80 Torr. DM
The supply amount of Zn was 30 μmol/min, and the supply amount of DMSe was 120 μmol/min. The timing of raw material gas supply along the time axis is as shown in FIG. DM
The supply of Se was performed 2 seconds before the supply of DMZn. Zinc selenide (hereinafter referred to as Zn
It is called Se. ) layer (203) growth substrate is shown in Figure 2.
It is shown in As can be seen from the figure, the mesa shape is preserved before and after crystal growth, indicating that etching by the source gas is suppressed.

【0012】本発明の実施例においては、ZnSeの結
晶成長の場合のみを紹介したが、ZnSe、硫化亜鉛(
以下、ZnSと称する。)の混晶結晶成長時、ZnSe
−ZnS超格子結晶成長時においてもVI族元素(Se
あるいはS)をII族元素(Zn)に先行して供給する
ことにより同様の効果が得られる。
In the examples of the present invention, only the case of ZnSe crystal growth was introduced, but ZnSe, zinc sulfide (
Hereinafter, it will be referred to as ZnS. ), ZnSe
Even during the -ZnS superlattice crystal growth, group VI elements (Se
Alternatively, the same effect can be obtained by supplying S) before the Group II element (Zn).

【0013】[0013]

【発明の効果】以上実施例に述べたように本発明によれ
ば、以下のような効果が得られる。III−V族化合物
半導体基板上にMOVPE法にてII−VI族化合物半
導体薄膜を結晶成長させる際、VI族元素原料の供給を
II族原料に時間的に先行させることとしたことにより
II族元素による基板のガスエッチングが抑制され、こ
れにより基板の微細パターンが結晶成長後も再現良く保
存される。またガスエッチングの際にII族元素と反応
するIII族元素およびV族元素が成長層であるII−
VI族化合物半導体薄膜中に取り込まれるのが抑制され
、従って界面の急峻性が確保される。
[Effects of the Invention] As described in the embodiments above, according to the present invention, the following effects can be obtained. When crystal-growing a II-VI compound semiconductor thin film on a III-V compound semiconductor substrate by MOVPE, the Group VI element raw material is supplied temporally before the Group II raw material. Gas etching of the substrate is suppressed, and as a result, fine patterns on the substrate are preserved with good reproducibility even after crystal growth. In addition, II-
Incorporation into the Group VI compound semiconductor thin film is suppressed, thus ensuring the steepness of the interface.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明における、II族元素原料ガス、VI族
元素原料ガス供給のタイミングを示す図。
FIG. 1 is a diagram showing the timing of supplying group II element raw material gas and group VI element raw material gas in the present invention.

【図2】本発明における、ZnSe結晶成長基板の断面
を示す図。
FIG. 2 is a diagram showing a cross section of a ZnSe crystal growth substrate in the present invention.

【図3】従来の技術における、II−VI族化合物半導
体薄膜結晶成長基板の断面を示す図。
FIG. 3 is a diagram showing a cross section of a II-VI group compound semiconductor thin film crystal growth substrate according to the prior art.

【符号の説明】[Explanation of symbols]

201  SiO2 202  半絶縁性のGaAs基板 203  セレン化亜鉛 301  SiO2 302  半絶縁性のGaAs基板 201 SiO2 202 Semi-insulating GaAs substrate 203 Zinc selenide 301 SiO2 302 Semi-insulating GaAs substrate

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】III−V族化合物半導体基板上に有機金
属気相成長法にてII−VI族化合物半導体薄膜を結晶
成長させる際、VI族元素原料をII族元素原料に時間
的に先行させ供給することを特徴とするII−VI族化
合物半導体薄膜の製造方法。
Claim 1: When crystal-growing a II-VI group compound semiconductor thin film on a III-V group compound semiconductor substrate by organometallic vapor phase epitaxy, a group VI element raw material is temporally preceded by a group II element raw material. A method for producing a II-VI group compound semiconductor thin film, comprising: supplying a thin film of a II-VI compound semiconductor.
JP7508391A 1991-04-08 1991-04-08 Manufacture of ii-vi compound semiconductor thin film Pending JPH04309241A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7508391A JPH04309241A (en) 1991-04-08 1991-04-08 Manufacture of ii-vi compound semiconductor thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7508391A JPH04309241A (en) 1991-04-08 1991-04-08 Manufacture of ii-vi compound semiconductor thin film

Publications (1)

Publication Number Publication Date
JPH04309241A true JPH04309241A (en) 1992-10-30

Family

ID=13565933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7508391A Pending JPH04309241A (en) 1991-04-08 1991-04-08 Manufacture of ii-vi compound semiconductor thin film

Country Status (1)

Country Link
JP (1) JPH04309241A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018152457A (en) * 2017-03-13 2018-09-27 株式会社デンソー Semiconductor substrate and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018152457A (en) * 2017-03-13 2018-09-27 株式会社デンソー Semiconductor substrate and method for manufacturing the same

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