JPH04306849A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04306849A
JPH04306849A JP3071230A JP7123091A JPH04306849A JP H04306849 A JPH04306849 A JP H04306849A JP 3071230 A JP3071230 A JP 3071230A JP 7123091 A JP7123091 A JP 7123091A JP H04306849 A JPH04306849 A JP H04306849A
Authority
JP
Japan
Prior art keywords
semiconductor chip
bonding
wire
size
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3071230A
Other languages
Japanese (ja)
Inventor
Tatsumi Imoto
達美 井本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP3071230A priority Critical patent/JPH04306849A/en
Publication of JPH04306849A publication Critical patent/JPH04306849A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable a semiconductor device to be mounted with various bonding materials different in size, to set a bonding wire excellent in form at wire bonding, and to be easily controlled in quantity. CONSTITUTION:An insulating layer 5 is formed on a mount 2 of a lead frame 1 where a die is bonded. A large number of electrodes 6 are provided to the upside of the insulating layer 5 at a certain interval.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は半導体装置に係り、詳し
くはダイボンディクのための基材に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a base material for a die bonding device.

【０００２】0002

【従来の技術】従来、ダイボンディクにおいて、半導体
チップ等の被ボンディング材を載置する基材はその被ボ
ンディング材の大きさに合わせて製作されている。そし
て、その基材の大きさに合わせてパッケージ用フレーム
等も製作されている。2. Description of the Related Art Conventionally, in a die bonding disk, a base material on which a material to be bonded such as a semiconductor chip is placed is manufactured to match the size of the material to be bonded. Package frames and the like are also manufactured to match the size of the base material.

【０００３】0003

【発明が解決しようとする課題】従って、多品種少量化
が進むなかで被ボンディング材の大きさに合わせて、基
材及びパッケージ用フレームをその数だけ揃えることは
品種管理が複雑となり経済的ではなかった。そこで、ダ
イボンディクエリアの大きい基材を予め１つ用意し、サ
イズの小さい被ボンディング材をそのエリアの大きい基
材にボンディングすることが考えられる。[Problem to be Solved by the Invention] Therefore, as the number of products and products decreases, it is difficult to prepare base materials and packaging frames according to the size of the material to be bonded because it complicates product management and is not economical. There wasn't. Therefore, it is conceivable to prepare in advance one base material with a large die-bonding area, and bond a small-sized bonding target material to the base material with a large die-bonding area.

【０００４】しかしながら、ワイヤボンディングを実施
する際、基材のサイズが大きいことから、被ボンディン
グ材と基材の外側に配置される内部リードとの間隔が大
きくなる。その結果、ワイヤの長さが長くなり過ぎ良好
なループ形状が得られない問題があった。本発明は上記
問題点を解消するためになされたものであって、その目
的はサイズの異なる各種被ボンディング材を搭載するこ
とができるとともに、ワイヤボンディングにおいて良好
なワイヤ形状を得ることができ、品種管理を簡単にする
ことができる半導体装置を提供することにある。However, when performing wire bonding, since the size of the base material is large, the distance between the material to be bonded and the internal leads disposed outside the base material becomes large. As a result, there was a problem in that the length of the wire became too long and a good loop shape could not be obtained. The present invention has been made to solve the above problems, and its purpose is to be able to mount various bonding materials of different sizes, to obtain a good wire shape in wire bonding, and to An object of the present invention is to provide a semiconductor device that can be easily managed.

【０００５】[0005]

【課題を解決するための手段】上記目的を達成するため
、本発明はダイボンディグするための基材上にワイヤボ
ンディク可能な複数の中継電極を形成した半導体装置を
その要旨とする。SUMMARY OF THE INVENTION In order to achieve the above objects, the gist of the present invention is a semiconductor device in which a plurality of wire bondable relay electrodes are formed on a base material for die bonding.

【０００６】[0006]

【作用】基材上にワイヤボンディク可能な電極を形成し
たことにより、被ボンディング材と電極及び該電極と内
部リードとをそれぞれワイヤボンディングすることがで
きる。その結果、被ボンディング材と基材の外側に配置
された内部リードとの間隔が大きくても、確実にワイヤ
ボンディングできる。しかも、個々のワイヤの長さは短
いので、良好なワイヤ形状を形成することができる。[Operation] By forming a wire-bondable electrode on the base material, it is possible to wire-bond the material to be bonded to the electrode and the electrode to the internal lead. As a result, even if the distance between the material to be bonded and the internal lead arranged outside the base material is large, wire bonding can be performed reliably. Moreover, since the length of each wire is short, a good wire shape can be formed.

【０００７】[0007]

【実施例】（第一実施例）以下、本発明の半導体装置を
具体化した第一実施例を図１〜図４に従って説明する。 図１はリードフレームの要部正面図であって、リードフ
レーム１はその中央部に形成された四角形状のマウント
部２と、そのマウント部２の外側に配置され外方に延び
る多数のリード３から構成されている。図３，図４に示
すように前記マウント部２は同マウント部２に搭載され
る半導体チップ４のサイズより数倍大きなサイズであっ
て、その上面は絶縁層５が形成されている。そして、本
実施例ではこのマウント部２と絶縁層５とで基材を構成
している。前記絶縁層５の上面には四角形状のアルミ電
極６が上下左右方向に等間隔に多数形成されている。絶
縁層５及びアルミ電極６が形成されたマウント部２の中
央位置には半導体チップ４が搭載され、同チップ４は絶
縁層５に対してボンディングされている。Embodiments (First Embodiment) A first embodiment embodying the semiconductor device of the present invention will be described below with reference to FIGS. 1 to 4. FIG. 1 is a front view of the main parts of a lead frame. The lead frame 1 includes a rectangular mount portion 2 formed in the center thereof, and a large number of leads 3 arranged outside the mount portion 2 and extending outward. It consists of As shown in FIGS. 3 and 4, the mount portion 2 is several times larger in size than the semiconductor chip 4 mounted on the mount portion 2, and an insulating layer 5 is formed on its upper surface. In this embodiment, the mount portion 2 and the insulating layer 5 constitute a base material. A large number of rectangular aluminum electrodes 6 are formed on the upper surface of the insulating layer 5 at equal intervals in the vertical and horizontal directions. A semiconductor chip 4 is mounted at the center of the mount portion 2 on which the insulating layer 5 and the aluminum electrode 6 are formed, and the chip 4 is bonded to the insulating layer 5.

【０００８】半導体チップ４が半田にてボンディングさ
れると、半導体チップ４の電極取り出し口とリードとの
間でワイヤボンディングが行われる。このとき、半導体
チップ４のサイズがマウント部２のサイズより小さいの
で、半導体チップ４の電極取り出し口とリード３との間
隔が非常に大きくなる。そのため、このワイヤボンディ
ングでは前記絶縁層５に形成したアルミ電極６を利用し
て行う。つまり、図３図４に示すように、ワイヤの長さ
が良好な形状を形成する長さになる位置のアルミ電極６
を選択する。そして、半導体チップ４の電極取り出し口
とその選択したアルミ電極６との間でワイヤボンディン
グを行う。次に、そのワイヤボンディングされたアルミ
電極６とリード３との間でワイヤボンディングを行う。 従って、半導体チップ４の電極取り出し口とアルミ電極
６及びアルミ電極６とリード３との間にそれぞれ形成さ
れたボンディングワイヤ７，８は直接半導体チップ４の
電極取り出し口とリード３とをボンディングするワイヤ
に比べてはるかに短くなり良好なループ形状を構成する
ことになる。When the semiconductor chip 4 is bonded with solder, wire bonding is performed between the electrode outlet of the semiconductor chip 4 and the leads. At this time, since the size of the semiconductor chip 4 is smaller than the size of the mount portion 2, the distance between the electrode outlet of the semiconductor chip 4 and the leads 3 becomes very large. Therefore, this wire bonding is performed using the aluminum electrode 6 formed on the insulating layer 5. In other words, as shown in FIGS.
Select. Then, wire bonding is performed between the electrode outlet of the semiconductor chip 4 and the selected aluminum electrode 6. Next, wire bonding is performed between the wire-bonded aluminum electrode 6 and the lead 3. Therefore, the bonding wires 7 and 8 formed between the electrode outlet of the semiconductor chip 4 and the aluminum electrode 6 and between the aluminum electrode 6 and the lead 3 are wires that directly bond the electrode outlet of the semiconductor chip 4 and the lead 3. This results in a much shorter loop than the previous one, creating a good loop shape.

【０００９】そして、アルミ電極６を利用して半導体チ
ップ４の各電極取り出し口とリード３との間のワイヤボ
ンディングが終了されると、半導体チップ４は図３，図
４に示すようにその周囲をモールド樹脂９にて封止され
る。このように本実施例においては、マウント部２のサ
イズが大きいリードフレームを用意し、そのマウント部
２上に絶縁層５を介してアルミ電極６を形成し、その電
極６を利用して同マウント部２に搭載された半導体チッ
プ４とリード３とのワイヤボンディングを行うようにし
たので、マウント部２のサイズより小さいサイズの半導
体チップ４であるならばどんなサイズのものでも搭載で
き、しかも良好なループ形状のボンディングワイヤ７，
８を形成することができる。従って、チップ４のサイズ
に合わせてリードフレームを揃える必要がなくなり、品
種管理が簡単になる。When the wire bonding between each electrode outlet of the semiconductor chip 4 and the leads 3 is completed using the aluminum electrode 6, the semiconductor chip 4 is bonded around the semiconductor chip 4 as shown in FIGS. 3 and 4. are sealed with mold resin 9. In this way, in this embodiment, a lead frame with a large mount part 2 is prepared, an aluminum electrode 6 is formed on the mount part 2 via an insulating layer 5, and the electrode 6 is used to connect the mount part 2 to the lead frame. Since wire bonding is performed between the semiconductor chip 4 mounted on the mount section 2 and the leads 3, any size semiconductor chip 4 smaller than the size of the mount section 2 can be mounted. loop-shaped bonding wire 7,
8 can be formed. Therefore, there is no need to align lead frames according to the size of the chip 4, and product management becomes easier.

【００１０】（第二実施例）次に本発明の第二実施例を
図５，図６に従って説明する。図５，図６において、基
材としてのセラミックパッケージ１１はセラミックにて
成形され、上面が凹設されてキャビティ１２を形成して
いる。キャビティ１２の底面には四角形状のアルミ電極
１３が上下左右方向に等間隔に多数形成されている。ア
ルミ電極１３が形成されたキャビティ１２底面の中央位
置には半導体チップ１４が搭載され、同チップ１４はボ
ンディングされている。このとき、セラミックパッケー
ジ１１は絶縁体なのでキャビティ１２の底面に絶縁層を
形成する必要はない。(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. 5 and 6. In FIGS. 5 and 6, a ceramic package 11 serving as a base material is molded from ceramic, and has a concave upper surface to form a cavity 12. A large number of rectangular aluminum electrodes 13 are formed on the bottom surface of the cavity 12 at equal intervals in the vertical and horizontal directions. A semiconductor chip 14 is mounted at the center of the bottom surface of the cavity 12 where the aluminum electrode 13 is formed, and the chip 14 is bonded. At this time, since the ceramic package 11 is an insulator, there is no need to form an insulating layer on the bottom surface of the cavity 12.

【００１１】半導体チップ１４がボンディングされると
、セラミックパッケージ１１の上部周辺に配置したリー
ド１５との間でワイヤボンディングが行われる。このと
き、半導体チップ１４のサイズがパッケージ１１のサイ
ズより小さいとき、半導体チップ１４の電極取り出し口
とリード１５との間隔が非常に大きくなる。そのため、
このワイヤボンディングでは前記実施例と同様にアルミ
電極１３を利用して行う。まず、ワイヤ１６，１７の長
さが良好な形状を形成する長さになる位置のアルミ電極
１３を選択する。そして、半導体チップ１４の電極取り
出し口とその選択したアルミ電極１３との間でワイヤボ
ンディングを行う。次に、そのワイヤボンディングされ
たアルミ電極１３とリード３との間でワイヤボンディン
グを行うようにしている。When the semiconductor chip 14 is bonded, wire bonding is performed between it and the leads 15 arranged around the upper part of the ceramic package 11. At this time, when the size of the semiconductor chip 14 is smaller than the size of the package 11, the distance between the electrode outlet of the semiconductor chip 14 and the leads 15 becomes very large. Therefore,
This wire bonding is performed using the aluminum electrode 13 as in the previous embodiment. First, the aluminum electrode 13 is selected at a position where the lengths of the wires 16 and 17 form a good shape. Then, wire bonding is performed between the electrode outlet of the semiconductor chip 14 and the selected aluminum electrode 13. Next, wire bonding is performed between the wire-bonded aluminum electrode 13 and the lead 3.

【００１２】従って、本実施例においても、前記実施例
と同様にパッケージ１１のサイズより小さいサイズの半
導体チップ１４であるならばどんなサイズのものでも搭
載でき、しかも良好なループ形状のボンディングワイヤ
１６，１７を形成することができる。従って、チップ１
４のサイズに合わせてセラミックパッケージ及びリード
フレームを揃える必要がなくなり、品種管理が非常に簡
単になる。Therefore, in this embodiment as well, as in the previous embodiment, any size semiconductor chip 14 can be mounted as long as it is smaller than the size of the package 11, and the bonding wire 16, which has a good loop shape, can be mounted. 17 can be formed. Therefore, chip 1
There is no need to arrange ceramic packages and lead frames according to the size of No. 4, making product product management very easy.

【００１３】なお、本発明は前記実施例に限定されるも
のではなく、例えば前記各実施例において基材としてリ
ードフレームのマウント部及びセラミックパッケージに
具体化したが、半導体チップを搭載しその上でワイヤボ
ンディングが行われるものであるならばなんでもよい。 また、前記実施例では電極をアルミにて形成したが、こ
れを金等のその他金属にて形成してもよい。さらに、電
極を上下左右に等間隔に配置したが、これに限定される
ものではなく電極の数、大きさ、形状及び配置位置を適
宜変更して実施してもよい。Note that the present invention is not limited to the above-mentioned embodiments; for example, in each of the above-mentioned embodiments, the mount portion of a lead frame and a ceramic package are used as the base material; Any material may be used as long as wire bonding is performed. Furthermore, although the electrodes were made of aluminum in the above embodiments, they may be made of other metals such as gold. Further, although the electrodes are arranged at equal intervals vertically and horizontally, the present invention is not limited to this, and the number, size, shape, and arrangement position of the electrodes may be changed as appropriate.

【００１４】[0014]

【発明の効果】以上詳述したように本発明によれば、サ
イズの異なる各種被ボンディング材を搭載できるととも
に、ワイヤボンディングにおいて良好なワイヤ形状を得
ることができ、品種管理を簡単にすることができる優れ
た効果がある。[Effects of the Invention] As described in detail above, according to the present invention, it is possible to mount various bonding materials of different sizes, obtain a good wire shape in wire bonding, and simplify product management. It has great effects.

【図面の簡単な説明】[Brief explanation of drawings]

【図１】モールドパッケージに使用されるリードフレー
ムの正面図である。FIG. 1 is a front view of a lead frame used in a molded package.

【図２】モールドパッケージに使用されるリードフレー
ムの側断面面である。FIG. 2 is a side cross-sectional view of a lead frame used in a molded package.

【図３】リードフレームに半導体チップを搭載した状態
を示す正面図である。FIG. 3 is a front view showing a state in which a semiconductor chip is mounted on a lead frame.

【図４】半導体チップにワイヤボンディングした状態を
示す側断面面である。FIG. 4 is a side cross-sectional view showing a state in which wire bonding is performed to a semiconductor chip.

【図５】第二実施例を説明するためのセラミックパッケ
ージの正面図である。FIG. 5 is a front view of a ceramic package for explaining a second embodiment.

【図６】セラミックパッケージの側断面図である。FIG. 6 is a side sectional view of the ceramic package.

【符号の説明】[Explanation of symbols]

１…リードフレーム、２…マウント部、３…リード、４
…半導体チップ、５…絶縁層、６…アルミ電極、７，８
…ボンディングワイヤ、９…モールド樹脂、１１…セラ
ミックパッケージ、１２…キャビティ、１３…アルミ電
極、１４…半導体チップ、１５…リード、１６，１７…
ボンディングワイヤ1...Lead frame, 2...Mount part, 3...Lead, 4
...Semiconductor chip, 5...Insulating layer, 6...Aluminum electrode, 7,8
...Bonding wire, 9...Mold resin, 11...Ceramic package, 12...Cavity, 13...Aluminum electrode, 14...Semiconductor chip, 15...Lead, 16, 17...
bonding wire

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】　　ダイボンディグするための基材上にワ
イヤボンディク可能な複数の中継電極を形成したことを
特徴とする半導体装置。1. A semiconductor device characterized in that a plurality of relay electrodes capable of wire bonding are formed on a base material for die bonding.
JP3071230A 1991-04-03 1991-04-03 Semiconductor device Pending JPH04306849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3071230A JPH04306849A (en) 1991-04-03 1991-04-03 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3071230A JPH04306849A (en) 1991-04-03 1991-04-03 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04306849A true JPH04306849A (en) 1992-10-29

Family

ID=13454685

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3071230A Pending JPH04306849A (en) 1991-04-03 1991-04-03 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04306849A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011187841A (en) * 2010-03-10 2011-09-22 Renesas Electronics Corp Electronic device, relay member, mounting substrate, and method of manufacturing electronic device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61161730A (en) * 1985-01-11 1986-07-22 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61161730A (en) * 1985-01-11 1986-07-22 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011187841A (en) * 2010-03-10 2011-09-22 Renesas Electronics Corp Electronic device, relay member, mounting substrate, and method of manufacturing electronic device

Similar Documents

Publication Publication Date Title
US6603196B2 (en) Leadframe-based semiconductor package for multi-media card
US6130474A (en) Leads under chip IC package
CN100452441C (en) Optical sensor package
CN100595912C (en) Multi-row lead frame
KR20010039537A (en) semiconductor package and its manufacturing method
JPH08148644A (en) Resin-sealed semiconductor device
JPH08111491A (en) Semiconductor device
JPH04302164A (en) Semiconductor device
JPH04306849A (en) Semiconductor device
JPH04340751A (en) Plastic molded type semiconductor device
JPH01187841A (en) Semiconductor device
JPS59154051A (en) Semiconductor device
KR100239684B1 (en) Multi chip package fabrication method and structure thereof
JPH0621305A (en) Semiconductor device
JP2001127233A (en) Resin-sealed semiconductor device
JP2001185567A (en) Semiconductor device and manufacturing method therefor
JPH06132475A (en) Semiconductor package
KR100729028B1 (en) Lead frame of tape formation and semiconduct package using it
JP2752803B2 (en) Method for manufacturing semiconductor device
JP2702182B2 (en) Semiconductor device and manufacturing method thereof
KR0184061B1 (en) Semiconductor package
JPH07283358A (en) Packaged integrated circuit and method of packaging integrated circuit
JPH08107178A (en) Resin molded semiconductor device and manufacturing method thereof
JPS62128550A (en) Lead frame for semiconductor device
KR950008852B1 (en) Pccd type leadframe and method