JPH04306804A - Laminated type varistor - Google Patents

Laminated type varistor

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Publication number
JPH04306804A
JPH04306804A JP3099519A JP9951991A JPH04306804A JP H04306804 A JPH04306804 A JP H04306804A JP 3099519 A JP3099519 A JP 3099519A JP 9951991 A JP9951991 A JP 9951991A JP H04306804 A JPH04306804 A JP H04306804A
Authority
JP
Japan
Prior art keywords
varistor
added
rare earth
voltage
earth element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3099519A
Other languages
Japanese (ja)
Inventor
Akiyoshi Nakayama
晃慶 中山
Kazuyoshi Nakamura
和敬 中村
Yasunobu Yoneda
康信 米田
Yukio Sakabe
行雄 坂部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP3099519A priority Critical patent/JPH04306804A/en
Publication of JPH04306804A publication Critical patent/JPH04306804A/en
Withdrawn legal-status Critical Current

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Abstract

PURPOSE:To obtain a laminated type varistor on which a leakage current can be decreased without deterioration of varistor voltage and surge resistivity. CONSTITUTION:A laminated body 4 is formed by alternately stacking a semiconductor ceramic layer 2 and an inner electrode 3, and a laminated type varistor 1 is constituted in such a manner that non-linear voltage characteristics obtained on the interface between the aforesaid inner conductive film 3 and the semiconductor ceramic layer 2. In this case, an oxide of element, which is selected from at least one or more kinds of Co and rare-earth element, and an Mn oxide are added to the above-mentioned inner electrode 3. Also, the adding quantity of the aforesaid Co or rare-earth element should be 0.01 to 20wt.% in terms of Co2O3, or R2O3, (R indicates rare-earth element), and the adding quantity of Mn should be 0.01 to 20wt.% in termas of Mn3O4.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、電圧非直線抵抗体とし
て機能する積層型バリスタに関し、特に内部電極と半導
体セラミックス層との界面で電圧非直線特性を得るよう
にした場合の、漏れ電流の改善に関する。
[Industrial Field of Application] The present invention relates to a multilayer varistor that functions as a voltage nonlinear resistor, and in particular, the present invention relates to a multilayer varistor that functions as a voltage nonlinear resistor. Regarding improvement.

【0002】0002

【従来の技術】一般に、印加電圧に応じて抵抗値が非直
線的に変化する電圧非直線抵抗体(以下、バリスタと称
す)は、サージ吸収素子,電圧安定化素子として広く採
用されている。このようなバリスタの電気的特性は、I
/i=(V/Vi )a で表される。上記Iは素子に
流れる電流,Vは印加電圧,Vi は素子にiAの電流
が流れたときの端子間電圧で、通常1mAの値をとりバ
リスタ電圧V1mA と称されている。また、上記aは
電圧非直線係数であり、バリスタを電気回路に組み込ん
だ際に電圧がいかに制御されるかを示すもので、このa
値が大きいほど電圧制御に優れている。また、近年の通
信機等に採用される電子機器の分野においては、小型化
,IC化,集積化が急速に進んでおり、これに伴ってバ
リスタにおいても実装密度の向上を図るための超小型化
,あるいは低電圧化の要求が強くなっている。このよう
な要求に対応するものとして、従来、ディスク型に代わ
る積層型バリスタが提案されている(例えば、特公昭5
8−23921号公報参照) 。この積層型バリスタは
、半導体セラミックス層と内部電極とを交互に重ねて積
層体を形成するとともに、該積層体の両端面に上記各内
部電極の一端面に接続される外部電極を形成した構造の
ものである。この積層型バリスタによれば、上記半導体
セラミックス層の結晶粒子を巨大に成長させることなく
内部電極間の粒界数を小さくすることが可能であること
から、動作電圧の低電圧化が実現でき、小型化にも対応
できる。また、上記積層型バリスタの改良型として、上
記内部電極間のセラミックス層内に上記外部電極に接続
されない非接続内部電極を配設してなる積層型バリスタ
(特願平1−302496 号参照) 、さらに上記内
部電極に希土類元素を添加してなる積層型バリスタ(特
願平1−304296 号参照) が提案されている。 上記内部電極間に非接続内部電極を配設した構造のもの
は、該電極間に挟まれたセラミックスの粒界数を2以下
としたことから、上述の従来公報に比べてバリスタ電圧
のばらつきを低減でき、さらにバリスタ電圧が4〜16
V の低電圧でありながらサージ耐量を向上できる。ま
た上記内部電極に希土類元素を添加してなる構造のもの
は、この希土類酸化物が焼成時にセラミックスの結晶粒
界に拡散し、これによって酸素の拡散速度が大きくなり
、ひいては電気的特性を向上できる。
2. Description of the Related Art Generally, voltage nonlinear resistors (hereinafter referred to as varistors) whose resistance value changes nonlinearly in accordance with applied voltage are widely used as surge absorbing elements and voltage stabilizing elements. The electrical characteristics of such a varistor are I
/i=(V/Vi)a. The above I is the current flowing through the element, V is the applied voltage, and Vi is the voltage between the terminals when a current of iA flows through the element, which usually takes a value of 1 mA and is called the varistor voltage V1 mA. In addition, the above a is a voltage nonlinear coefficient, which indicates how the voltage is controlled when the varistor is incorporated into an electric circuit.
The larger the value, the better the voltage control. In addition, in the field of electronic equipment used in communication equipment and other devices in recent years, miniaturization, IC integration, and integration are progressing rapidly. There is a growing demand for higher voltage or lower voltage. To meet these demands, laminated type varistors have been proposed to replace the disk type (for example,
(See Publication No. 8-23921). This multilayer varistor has a structure in which semiconductor ceramic layers and internal electrodes are alternately stacked to form a laminate, and external electrodes are formed on both end faces of the laminate to be connected to one end face of each of the internal electrodes. It is something. According to this multilayer varistor, it is possible to reduce the number of grain boundaries between the internal electrodes without causing the crystal grains of the semiconductor ceramic layer to grow to a large size, so it is possible to realize a lower operating voltage. It can also be made smaller. Furthermore, as an improved version of the multilayer varistor, there is a multilayer varistor in which unconnected internal electrodes that are not connected to the external electrodes are disposed within the ceramic layer between the internal electrodes (see Japanese Patent Application No. 1-302496); Furthermore, a multilayer varistor (see Japanese Patent Application No. 1-304296) has been proposed in which a rare earth element is added to the internal electrodes. The structure in which non-connected internal electrodes are disposed between the internal electrodes has two or less grain boundaries in the ceramic sandwiched between the electrodes, so the variation in varistor voltage is reduced compared to the above-mentioned conventional publication. Furthermore, the varistor voltage can be reduced from 4 to 16
Although the voltage is as low as V, the surge resistance can be improved. In addition, in the structure in which a rare earth element is added to the internal electrode, this rare earth oxide diffuses into the grain boundaries of the ceramic during firing, which increases the oxygen diffusion rate and improves the electrical characteristics. .

【0003】0003

【発明が解決しようとする課題】ところで、上記内部電
極,あるいは非接続内部電極とセラミックス層との界面
でバリスタ特性を得るようにした従来の積層型バリスタ
では、電圧制限能力は優れているものの、漏れ電流が大
きいという問題点がある。ここで、積層型バリスタにお
ける漏れ電流を改善するには、例えば酸化ビスマスの添
加量を増加することが一般的に知られている。しかしな
がら、この酸化ビスマスの添加量を増加させて素子の組
成を改良するだけでは、それほど漏れ電流の改善効果が
得られない。
[Problems to be Solved by the Invention] By the way, conventional multilayer varistors in which varistor characteristics are obtained at the interface between the internal electrodes or the non-connected internal electrodes and the ceramic layer have excellent voltage limiting ability; There is a problem in that the leakage current is large. Here, in order to improve leakage current in a multilayer varistor, it is generally known to increase the amount of bismuth oxide added, for example. However, simply improving the composition of the element by increasing the amount of bismuth oxide added does not significantly improve the leakage current.

【0004】本発明は上記従来の状況に鑑みてなされた
もので、バリスタ電圧の低電圧化を図りながら、漏れ電
流を低減できる積層型バリスタを提供することを目的と
している。
The present invention has been made in view of the above-mentioned conventional situation, and an object of the present invention is to provide a multilayer varistor that can reduce leakage current while lowering the varistor voltage.

【0005】[0005]

【課題を解決するための手段】本件発明者らは、上記漏
れ電流が生じる原因について検討したことろ、内部電極
,あるいは非接続内部電極間に挟まれたセラミックスの
結晶粒界数が2以下であること、また焼成時に希土類酸
化物が結晶粒界に拡散することによって内部電極とセラ
ミックス層との界面付近にポア等が生じ、このポアに放
電が生じることにより漏れ電流を増大させていることを
見出した。ここで、上記結晶粒界数を増やすとバリスタ
電圧のばらつきや低電圧化を劣化させるおそれがあり、
粒界数の増大は困難である。一方、上記希土類元素の分
布状態を波長分散型X線マイクロアナライザーで分析し
たところ、この希土類の分布状態と素子に含有するMn
の分布状態とは略一致していることが判明した。即ち、
希土類元素はMnに向かって素子中を移動し、Mn−希
土類元素の反応相を形成している。そこで本件発明者ら
は、この分析結果から、Mnを予め希土類元素とともに
内部電極に添加すれば、希土類元素は素子中に拡散する
ことなく界面付近に存在するのではないかと考え、実際
に実験を行った。その結果、Mnを添加すると希土類元
素は拡散することなく内部電極とセラミックス層との界
面,つまりポア中に存在していることが確認された。こ
れにより得られた積層型バリスタの電気的特性を測定し
たことろ、内部電極に希土類元素だけを添加した場合と
比べて漏れ電流の大幅な改善が認められた。しかも、バ
リスタ電圧,制限電圧,サージ耐量は略同一のレベルで
あり、静電容量は2分の1以下に低減している。 従って、静電容量を同じ値にすると内部電極の電極面積
は従来の2倍以上確保できることとなり、その結果サー
ジ耐量を2倍程度向上できる。また上記実験では、希土
類元素の代わりにCoを添加した場合も同様の結果が得
られた。
[Means for Solving the Problems] The inventors of the present invention have investigated the causes of the above-mentioned leakage current and found that the number of grain boundaries of ceramics sandwiched between internal electrodes or unconnected internal electrodes is 2 or less. We also know that pores are created near the interface between the internal electrode and the ceramic layer due to rare earth oxides diffusing into the grain boundaries during firing, and that discharge occurs in these pores, increasing leakage current. I found it. Here, increasing the number of grain boundaries mentioned above may cause variations in varistor voltage and deteriorate the ability to lower voltage.
It is difficult to increase the number of grain boundaries. On the other hand, when the distribution state of the rare earth elements was analyzed using a wavelength dispersive X-ray microanalyzer, it was found that the distribution state of the rare earth elements and the Mn contained in the element were
It was found that the distribution state of That is,
The rare earth element moves toward Mn in the device, forming a Mn-rare earth element reaction phase. Based on this analysis result, the inventors thought that if Mn was added to the internal electrode together with the rare earth element in advance, the rare earth element would exist near the interface without diffusing into the element, and conducted an actual experiment. went. As a result, it was confirmed that when Mn was added, the rare earth element did not diffuse and was present at the interface between the internal electrode and the ceramic layer, that is, in the pores. When the electrical characteristics of the multilayer varistor thus obtained were measured, it was found that the leakage current was significantly improved compared to the case where only rare earth elements were added to the internal electrodes. Furthermore, the varistor voltage, limiting voltage, and surge resistance are at approximately the same level, and the capacitance is reduced to less than half. Therefore, if the capacitance is set to the same value, the electrode area of the internal electrode can be secured more than twice that of the conventional one, and as a result, the surge resistance can be improved by about twice. Furthermore, in the above experiment, similar results were obtained when Co was added instead of the rare earth element.

【0006】そこで請求項1の発明は、半導体セラミッ
クス層と内部電極とを交互に重ねて積層体を形成し、上
記内部電極と半導体セラミックス層との界面で電圧非直
線特性を得るようにした積層型バリスタにおいて、上記
内部電極にCo又は希土類元素から選ばれた少なくとも
1種類以上の元素の酸化物と、Mnの酸化物とを添加し
たことを特徴としている。また、請求項2の発明は、上
記Co又は希土類元素の添加量をCo2 O3,R2 
O3(R:希土類元素)に換算して0.01〜20重量
%とし、かつMnの添加量をMn3 O4 に換算して
0.01〜20重量%としたことを特徴としている。こ
こで、上記Co,希土類元素の添加量、及びMnの添加
量を限定した理由について説明する。上記Co,希土類
元素の添加量が0.01重量%を下回ると漏れ電流の改
善効果が得られ難く、しかも静電容量も低減できないか
らである。また20重量%を越えるとこれらの元素とM
nとの反応相が界面に厚く形成され、この結果制限電圧
が非常に大きくなるからである。また、上記Mnの添加
量が0.01重量%を下回ると、Co,希土類元素の拡
散を阻止できなくなり、ひいては漏れ電流の改善効果が
小さくなるからである。また20重量%を越えると上記
と同様に界面に反応相が厚くなるからである。また、本
発明の積層型バリスタには、内部電極の一端面を交互に
積層体の端面に露出したもの、あるいは上記内部電極間
のセラミックス層内に外部電極に接続されない非接続内
部電極を内蔵したものが含まれ、要は半導体セラミック
ス層と内部電極との界面で電圧非直線性特性を得るよう
にしたものであればいずれにも適用できる。
[0006] Accordingly, the invention of claim 1 provides a laminate in which semiconductor ceramic layers and internal electrodes are alternately stacked to form a laminate, and voltage nonlinear characteristics are obtained at the interface between the internal electrodes and the semiconductor ceramic layer. The type varistor is characterized in that an oxide of at least one element selected from Co or rare earth elements and an oxide of Mn are added to the internal electrode. Further, the invention of claim 2 provides that the amount of Co or the rare earth element added is set to Co2 O3, R2
It is characterized in that the amount of Mn added is 0.01 to 20% by weight in terms of O3 (R: rare earth element), and the amount of Mn added is 0.01 to 20% by weight in terms of Mn3O4. Here, the reason why the amounts of Co and rare earth elements added and the amount of Mn added are limited will be explained. This is because if the amount of Co and rare earth elements added is less than 0.01% by weight, it is difficult to obtain the effect of improving leakage current, and furthermore, the capacitance cannot be reduced. Moreover, if it exceeds 20% by weight, these elements and M
This is because a thick reaction phase with n is formed at the interface, resulting in a very large limiting voltage. Furthermore, if the amount of Mn added is less than 0.01% by weight, it becomes impossible to prevent the diffusion of Co and rare earth elements, and as a result, the effect of improving leakage current becomes smaller. Moreover, if the amount exceeds 20% by weight, the reaction phase will become thick at the interface as described above. Furthermore, the multilayer varistor of the present invention has one end surface of the internal electrodes exposed alternately on the end surface of the laminate, or a non-connected internal electrode that is not connected to the external electrode and is built into the ceramic layer between the internal electrodes. In short, it can be applied to any device that obtains voltage nonlinearity characteristics at the interface between the semiconductor ceramic layer and the internal electrode.

【0007】[0007]

【作用】本発明に係る積層型バリスタによれば、内部電
極にCo又は希土類元素を添加するとともにMnを添加
したので、焼成時にCo,希土類元素が拡散することな
くMnとともに内部電極とセラミックス層との界面付近
に存在してポアを埋めることとなり、その結果放電によ
る漏れ電流を低減できる。この場合、セラミックスの結
晶粒界数を最小値にした状態で漏れ電流を低減できるか
ら、バリスタ電圧のばらつきや低電圧化を劣化させるこ
とはない。また、本発明では、上述の構成で説明したよ
うに、バリスタ電圧,制限電圧,サージ耐量等の特性を
劣化させることなく、静電容量を1/2 以下にできる
ことから、従来の積層型バリスタと同じ静電容量となる
よう電極面積を設定した場合は、2倍以上の電極面積を
確保することができ、それだけサージ耐量を向上できる
という相乗効果が得られる。
[Function] According to the multilayer varistor of the present invention, since Co or rare earth elements are added to the internal electrodes and Mn is also added, the Co and rare earth elements do not diffuse during firing and are bonded together with Mn to the internal electrodes and the ceramic layer. It exists near the interface of the pores and fills the pores, and as a result, leakage current due to discharge can be reduced. In this case, since leakage current can be reduced with the number of crystal grain boundaries of the ceramic being minimized, variations in varistor voltage and deterioration of voltage reduction will not occur. In addition, as explained in the above-mentioned configuration, the present invention can reduce the capacitance by half or less without deteriorating the characteristics such as varistor voltage, limiting voltage, and surge resistance. When the electrode area is set so that the capacitance is the same, the electrode area can be doubled or more, and a synergistic effect can be obtained in that the surge resistance can be improved accordingly.

【0008】[0008]

【実施例】以下、本発明の実施例を図について説明する
。 実施例1 図1ないし図3は本発明の第1実施例による積層型バリ
スタを説明するための図である。図において、1は本実
施例の積層型バリスタである。このバリスタ1は直方体
状のもので、ZnOを主成分とする半導体セラミックス
層2とPtからなる内部電極3とを交互に積層し、これ
を一体焼成してなる焼結体4の左, 右端面4a,4b
にAgからなる外部電極5を形成して構成されている。 また、上記各内部電極3の一端面3aは焼結体4の左,
 右端面4a,4bに交互に導出されており、この端面
3aは上記外部電極5に電気的に接続されている。さら
に上記各内部電極3の他の部分はセラミックス層2の内
側に位置して焼結体4内に封入されている。なお、上記
焼結体4の上,下面にはダミーとしてのセラミックス層
6が配設されている。また、上記内部電極3間に挟まれ
た各半導体セラミックス層2の厚さ方向における結晶粒
子7の数は2以下となっている。
Embodiments Hereinafter, embodiments of the present invention will be explained with reference to the drawings. Embodiment 1 FIGS. 1 to 3 are diagrams for explaining a multilayer varistor according to a first embodiment of the present invention. In the figure, numeral 1 indicates a multilayer varistor of this embodiment. This varistor 1 has a rectangular parallelepiped shape, and has left and right end surfaces of a sintered body 4 made by alternately laminating semiconductor ceramic layers 2 mainly composed of ZnO and internal electrodes 3 made of Pt, and firing them together. 4a, 4b
It is constructed by forming an external electrode 5 made of Ag. Further, one end surface 3a of each internal electrode 3 is located on the left side of the sintered body 4,
The right end faces 4a and 4b are alternately led out, and this end face 3a is electrically connected to the external electrode 5. Furthermore, other parts of each internal electrode 3 are located inside the ceramic layer 2 and enclosed within the sintered body 4. Note that ceramic layers 6 as dummy are provided on the upper and lower surfaces of the sintered body 4. Furthermore, the number of crystal grains 7 in the thickness direction of each semiconductor ceramic layer 2 sandwiched between the internal electrodes 3 is 2 or less.

【0009】そして、上記各内部電極3には、Co,又
は希土類元素の酸化物が添加されており、これの添加量
はCo2 O3,又はR2O3 (R:希土類元素)に
換算して0.01〜20重量%の範囲内となっている。 また上記内部電極3にはMnの酸化物が添加されており
、このMnの添加量はMn3 O4 に換算して0.0
1〜20重量%の範囲内となっている。なお、上記各添
加物の添加量は全体で30wt%を越えないように設定
されている。これにより、図3に示すように、上記Co
,希土類元素の酸化物8,及びMnの酸化物9は内部電
極3の各セラミックス層2との界面付近に存在している
Co or an oxide of a rare earth element is added to each of the internal electrodes 3, and the amount of this added is 0.01 in terms of Co2 O3 or R2O3 (R: rare earth element). It is within the range of ~20% by weight. Further, an oxide of Mn is added to the internal electrode 3, and the amount of Mn added is 0.0 in terms of Mn3O4.
The content is within the range of 1 to 20% by weight. Note that the amount of each of the above additives added is set so as not to exceed 30 wt% in total. As a result, as shown in FIG.
, rare earth element oxide 8 , and Mn oxide 9 are present near the interface with each ceramic layer 2 of the internal electrode 3 .

【0010】次に本実施例の積層型バリスタ1の製造方
法について説明する。まず、ZnO,Bi2 O3 ,
Co2 CO3 ,MnO,Sb2 O3 ,及びCr
2O3 をそれぞれ97.9mol %,0.5mol
 %,0.5mol %,0.5mol %,0.3m
ol %, 及び0.3 mol %の組成比率となる
ように秤量し、イオン交換水を用いてボールミルで24
時間混合してセラミックス材料を作成した。次に、これ
をろ過した後,乾燥し、800 ℃で2時間仮焼し、こ
の後再度粉砕してセラミックス原料粉を作成した。次に
、上記粉砕したセラミックス原料粉に有機バインダを添
加混合し、リバースローラ方式により厚さ20μm の
グリーンシートを形成し、これを所定の大きさ, 形状
に打ちぬいて多数のセラミックス層2,6を作成した(
図2参照) 。また、Ptにビヒクルを混合してなるペ
ーストに、希土類元素から選択したPr2 O3 を5
重量%添加し、さらにMn3 O4 を5重量%添加し
て導電ペーストを作成した。この導電ペーストを、図2
に示すように、各セラミックスシート2の上面に印刷し
て内部電極3を形成した。次に、上記各内部電極3の一
端面3aが交互に位置するよう順次積層し、これの上面
,下面にそれぞれセラミックス層6を重ね、これの厚さ
方向に2ton/cm2 の圧力を加えて積層体を形成
し、所定寸法に切断した。これにより、内部電極3の一
端面3aのみ積層体の両端面に交互に露出し、他の部分
は積層体内に埋設した構造となる。次に、上記積層体を
、空気中にて1200℃の温度で2時間焼成し、焼結体
4を得た。この焼成時に希土類元素,Mnがセラミック
ス層2と内部電極3との界面付近に析出し、ポアを埋め
ることとなる。最後に、上記焼結体4の、内部電極3の
一端面3aが露出した左, 右端面4a,4bにAgペ
ーストを塗布した後、700 ℃の温度で10分間焼き
付けて外部電極5を形成し、これにより本実施例の積層
型バリスタ1を製造した。
Next, a method for manufacturing the multilayer varistor 1 of this embodiment will be explained. First, ZnO, Bi2 O3,
Co2 CO3, MnO, Sb2 O3, and Cr
97.9 mol% and 0.5 mol of 2O3, respectively
%, 0.5 mol %, 0.5 mol %, 0.3 m
It was weighed so that the composition ratio was 0.3 mol % and 0.3 mol %, and was heated in a ball mill using ion-exchanged water for 24 hours.
A ceramic material was created by time mixing. Next, this was filtered, dried, and calcined at 800° C. for 2 hours, and then ground again to produce ceramic raw material powder. Next, an organic binder is added to and mixed with the pulverized ceramic raw material powder, and a green sheet with a thickness of 20 μm is formed using a reverse roller method. This is punched into a predetermined size and shape to form a large number of ceramic layers 2 and 6. It was created(
(See Figure 2). In addition, 5% of Pr2O3 selected from rare earth elements was added to a paste made by mixing Pt with a vehicle.
A conductive paste was prepared by adding 5% by weight of Mn3O4. This conductive paste is shown in Figure 2.
As shown in FIG. 2, internal electrodes 3 were formed by printing on the top surface of each ceramic sheet 2. Next, the internal electrodes 3 are laminated one after another so that the one end surfaces 3a are alternately located, and the ceramic layers 6 are laminated on the upper and lower surfaces respectively, and the layers are laminated by applying a pressure of 2 ton/cm2 in the thickness direction. A body was formed and cut to size. This results in a structure in which only one end surface 3a of the internal electrode 3 is exposed alternately on both end surfaces of the laminate, and the other portions are buried within the laminate. Next, the laminate was fired in air at a temperature of 1200° C. for 2 hours to obtain a sintered body 4. During this firing, the rare earth element, Mn, precipitates near the interface between the ceramic layer 2 and the internal electrode 3, filling the pores. Finally, after applying Ag paste to the left and right end surfaces 4a and 4b of the sintered body 4 where one end surface 3a of the internal electrode 3 is exposed, the external electrode 5 is formed by baking at a temperature of 700° C. for 10 minutes. In this way, the multilayer varistor 1 of this example was manufactured.

【0011】[0011]

【表1】[Table 1]

【0012】このようにして得られた積層型バリスタ1
の、バリスタ電圧V1mA ,制限電圧比V2A/V1
mA ,サージ耐量A,絶縁抵抗値MΩ,及び静電容量
値pFを測定した。上記絶縁抵抗とは、バリスタ電圧の
50%の電圧を30秒間印加したときの素子の抵抗値で
ある。なお、比較するために内部電極にPr2 O3 
だけを5重量%添加した従来の積層型バリスタについて
も同様の測定を行った。
Multilayer varistor 1 thus obtained
, varistor voltage V1mA, limiting voltage ratio V2A/V1
mA, surge resistance A, insulation resistance value MΩ, and capacitance value pF were measured. The above insulation resistance is the resistance value of the element when a voltage of 50% of the varistor voltage is applied for 30 seconds. For comparison, Pr2O3 was used as the internal electrode.
Similar measurements were also performed on a conventional multilayer varistor to which 5% by weight of 5% by weight was added.

【0013】表1は、その結果を示す。同表からも明ら
かなように、本発明試料,及び従来試料ともバリスタ電
圧は4.2 〜4.1V、制限電圧比は1.5 ,サー
ジ耐量50A とほとんど差がなく、満足できる特性が
得られている。また、従来試料では、絶縁抵抗値は0.
3MΩと低く漏れ電流が大きくなっている。これに対し
て本発明試料では、絶縁抵抗値は2.2MΩと高く漏れ
電流を改善できていることがわかる。さらに静電容量で
は、本発明試料は220pF と従来試料の510pF
 と比べて1/2 以下となっている。
Table 1 shows the results. As is clear from the table, there is almost no difference between the inventive sample and the conventional sample, with varistor voltage of 4.2 to 4.1V, limiting voltage ratio of 1.5, and surge withstand capacity of 50A, and satisfactory characteristics were obtained. It is being Furthermore, in the conventional sample, the insulation resistance value was 0.
The leakage current is as low as 3MΩ and large. On the other hand, in the sample of the present invention, the insulation resistance value is as high as 2.2 MΩ, which indicates that the leakage current can be improved. Furthermore, in terms of capacitance, the inventive sample had a capacitance of 220 pF and the conventional sample had a capacitance of 510 pF.
It is less than 1/2 compared to

【0014】[0014]

【表2】[Table 2]

【0015】表2は、本実施例の内部電極3におけるP
r2 O3,及びMn3 O4 の各添加量を0 〜3
0wt%の範囲内で変化させた場合の、バリスタ電圧V
1mA ,静電容量値pF,絶縁抵抗値MΩ,サージ耐
量A,及び制限電圧比V2A/V1mA を示す。表中
、*印は本発明の範囲外である。表からも明らかなよう
に、Pr2 O3 ,及びMn3 O4の添加量が0の
場合は(試料 No.1,7,13参照)、いずれも絶
縁抵抗値が0.1 〜1.1MΩと低く漏れ電流が改善
されていない。また、上記添加量が30wt%の場合は
(試料 No.6,12参照)、漏れ電流は改善されて
いるものの、サーシ耐量が15,20Aと劣化している
。これに対してPr2 O3 ,Mn3 O4 の各添
加量が0.01〜20wt%の場合は(試料 No.2
〜5,8〜11)、いずれも絶縁抵抗値が2.1 〜2
.3MΩと高く、サージ耐量が50A と両方とも満足
できる特性が得られていることがわかる。
Table 2 shows P in the internal electrode 3 of this example.
The amounts of r2 O3 and Mn3 O4 added were 0 to 3.
Varistor voltage V when changed within the range of 0wt%
1mA, capacitance value pF, insulation resistance value MΩ, surge resistance A, and limiting voltage ratio V2A/V1mA. In the table, *marks are outside the scope of the present invention. As is clear from the table, when the amount of Pr2 O3 and Mn3 O4 added is 0 (see sample Nos. 1, 7, and 13), the insulation resistance value is low at 0.1 to 1.1 MΩ, and leakage is low. Current has not improved. Further, when the above-mentioned addition amount was 30 wt% (see Sample Nos. 6 and 12), although the leakage current was improved, the sash withstand capacity was degraded to 15 and 20 A. On the other hand, when the amounts of Pr2 O3 and Mn3 O4 added are 0.01 to 20 wt% (sample No. 2
~5,8~11), both have insulation resistance values of 2.1~2
.. It can be seen that satisfactory characteristics have been obtained for both, with a high surge resistance of 3MΩ and a surge resistance of 50A.

【0016】[0016]

【表3】[Table 3]

【0017】表3は、本実施例の内部電極3にCo2 
O3 ,及びMn3 O4 を添加し、かつこれらの添
加量を0 〜30wt%の範囲内で変化させた場合の、
バリスタ電圧V1mA,静電容量値pF,絶縁抵抗値M
Ω,サージ耐量A,及び制限電圧比V2A/V1mAを
示す。表中、*印は本発明の範囲外である。表からも明
らかなように、Co2 O3 ,及びMn3 O4 の
添加量が0の場合は(試料 No.1,7,13参照)
、いずれも絶縁抵抗値が0.1 〜1.1MΩと低い。 また、上記添加量が30wt%の場合は(試料 No.
6,12参照)、漏れ電流は改善されているものの、サ
ーシ耐量が15,20Aと劣化している。これに対して
Co2 O3,Mn3 O4 の各添加量が0.01〜
20wt%の場合は( 試料 No.2〜5,8〜11
)、いずれも絶縁抵抗値が2.0 〜2.3MΩと高く
、サージ耐量が50A と両方とも満足できる特性が得
られており、Co2 O3 を添加した場合も略同じ効
果が得られていることがわかる。
Table 3 shows that Co2 was used in the internal electrode 3 of this example.
When O3 and Mn3O4 are added and the amount of these added is varied within the range of 0 to 30 wt%,
Varistor voltage V1mA, capacitance value pF, insulation resistance value M
Ω, surge resistance A, and limiting voltage ratio V2A/V1mA are shown. In the table, *marks are outside the scope of the present invention. As is clear from the table, when the amount of Co2 O3 and Mn3 O4 added is 0 (see sample No. 1, 7, 13)
, all have low insulation resistance values of 0.1 to 1.1 MΩ. Moreover, when the above addition amount is 30 wt% (Sample No.
6, 12), and although the leakage current has been improved, the sash resistance has deteriorated to 15, 20A. On the other hand, each addition amount of Co2 O3 and Mn3 O4 is 0.01~
In the case of 20 wt% (Sample No. 2-5, 8-11
), the insulation resistance value is high at 2.0 to 2.3 MΩ, and the surge withstand capacity is 50 A, both of which have satisfactory characteristics, and almost the same effect is obtained when Co2 O3 is added. I understand.

【0018】実施例2 図4及び図5は本発明の第2実施例による積層型バリス
タを説明するための図である。本実施例の積層型バリス
タ20は、半導体セラミックス層21と内部電極22と
を交互に積層し、これを一体焼成してなる焼結体23の
左, 右端面23a,23bに外部電極24を形成し、
さらに上記各内部電極22間の半導体セラミックス層2
1内に非接続内部電極25を配設して構成されている。 この各非接続内部電極25の周端面はセラミックス層2
1の内側に位置して焼結体23内に封入されており、こ
れにより上記内部電極22間には外部電極24に接続さ
れない非接続内部電極25が介在されている。なお、2
6はダミーとしてのセラミックス層である。
Embodiment 2 FIGS. 4 and 5 are diagrams for explaining a multilayer varistor according to a second embodiment of the present invention. In the multilayer varistor 20 of this embodiment, semiconductor ceramic layers 21 and internal electrodes 22 are alternately laminated, and external electrodes 24 are formed on the left and right end surfaces 23a and 23b of a sintered body 23 that is integrally fired. death,
Furthermore, the semiconductor ceramic layer 2 between each of the internal electrodes 22 is
1, a non-connected internal electrode 25 is disposed within it. The peripheral end surface of each unconnected internal electrode 25 is covered with a ceramic layer 2.
The non-connected internal electrodes 25, which are not connected to the external electrodes 24, are interposed between the internal electrodes 22. In addition, 2
6 is a ceramic layer as a dummy.

【0019】そして、上記各内部電極22,及び非接続
内部電極25には、Co,又は希土類元素の酸化物とM
nの酸化物とが添加されており、これらの添加量はそれ
ぞれCo2 O3,又はR2 O3 (R:希土類元素
)に換算して0.01〜20重量%,0.01〜20重
量%の範囲内となっている。
Each of the internal electrodes 22 and the non-connected internal electrodes 25 are coated with Co or an oxide of a rare earth element and M.
n oxide is added, and the amounts added are in the range of 0.01 to 20% by weight and 0.01 to 20% by weight, respectively, in terms of Co2 O3 or R2 O3 (R: rare earth element). It is inside.

【0020】次に本実施例の積層型バリスタ20の製造
方法について説明する。まず、ZnO,Bi2 O3 
,Co2 CO3,MnO,Sb2 O3 ,及びCr
2O3 をそれぞれ97.9mol %,0.5mol
 %,0.5mol %,0.5mol %,0.3m
ol %, 及び0.3 mol %の組成比率となる
ように秤量し、イオン交換水を用いてボールミルで24
時間混合してセラミックス材料を作成した。次に、これ
をろ過した後,乾燥し、800 ℃で2時間仮焼し、こ
の後再度粉砕してセラミックス原料粉を作成した。次に
、上記粉砕したセラミックス原料粉に有機バインダを添
加混合し、リバースローラ方式により厚さ20μm の
グリーンシートを形成し、これを所定の大きさ, 形状
に打ちぬいて多数のセラミックスシート21a,26を
作成した(図5参照) 。また、Ptにビヒクルを混合
してなるペーストに、希土類元素から選択したPr2 
O3 を5重量%添加し、さらにMn3 O4 を5重
量%添加して導電ペーストを作成した。この導電ペース
トを、図5に示すように、各セラミックスシート21a
の上面に印刷して内部電極22,非接続内部電極25を
形成した。次に、上記各内部電極22の一端面が交互に
位置し、かつこの内部電極22の間に非接続電極25が
位置するよう順次積層し、これの上面,下面にそれぞれ
セラミックス層26を重ね、これの厚さ方向に2ton
/cm2 の圧力を加えて積層体を形成し、所定寸法に
切断した。これにより、内部電極22の一端面のみが積
層体の両端面に交互に露出しており、該内部電極22の
他の部分と非接続内部電極25とは積層体内に封入され
ている。次に、上記積層体を、空気中にて1200℃の
温度で2時間焼成し、焼結体23を得た。そして最後に
上記焼結体23の、内部電極22の一端面が露出した左
, 右端面23a,23bにAgペーストを塗布した後
、700 ℃の温度で10分間焼き付けて外部電極24
を形成し、これにより本実施例の積層型バリスタ20を
製造した。
Next, a method of manufacturing the multilayer varistor 20 of this embodiment will be explained. First, ZnO, Bi2 O3
, Co2 CO3, MnO, Sb2 O3, and Cr
97.9 mol% and 0.5 mol of 2O3, respectively
%, 0.5 mol %, 0.5 mol %, 0.3 m
It was weighed so that the composition ratio was 0.3 mol % and 0.3 mol %, and was heated in a ball mill using ion-exchanged water for 24 hours.
A ceramic material was created by time mixing. Next, this was filtered, dried, and calcined at 800° C. for 2 hours, and then ground again to produce ceramic raw material powder. Next, an organic binder is added to and mixed with the pulverized ceramic raw material powder, and a green sheet with a thickness of 20 μm is formed using a reverse roller method. This is punched out into a predetermined size and shape to form a large number of ceramic sheets 21a, 26. (see Figure 5). In addition, Pr2 selected from rare earth elements is added to the paste made by mixing Pt with a vehicle.
A conductive paste was prepared by adding 5% by weight of O3 and further adding 5% by weight of Mn3O4. This conductive paste is applied to each ceramic sheet 21a as shown in FIG.
The internal electrodes 22 and non-connected internal electrodes 25 were formed by printing on the upper surface of the . Next, the internal electrodes 22 are laminated in order so that one end surface thereof is alternately located and the non-connected electrodes 25 are located between the internal electrodes 22, and ceramic layers 26 are superimposed on the upper and lower surfaces of these, respectively. 2 tons in the thickness direction of this
A pressure of /cm2 was applied to form a laminate, which was cut into predetermined dimensions. As a result, only one end surface of the internal electrode 22 is exposed alternately on both end surfaces of the laminate, and the other portions of the internal electrode 22 and the unconnected internal electrode 25 are enclosed within the laminate. Next, the laminate was fired in air at a temperature of 1200° C. for 2 hours to obtain a sintered body 23. Finally, Ag paste is applied to the left and right end faces 23a and 23b of the sintered body 23, where one end face of the internal electrode 22 is exposed, and then baked at a temperature of 700°C for 10 minutes to form the external electrode 24.
was formed, thereby manufacturing the multilayer varistor 20 of this example.

【0021】[0021]

【表4】[Table 4]

【0022】このようにして得られた積層型バリスタ2
0の、バリスタ電圧V1mA ,制限電圧比V2A/V
1mA ,サージ耐量A,絶縁抵抗値MΩ,及び静電容
量値pFを測定した。なお、比較するために内部電極に
Pr2 O3 だけを5重量%添加した従来の積層型バ
リスタについても同様の測定を行った。表4は、その結
果を示す。同表からも明らかなように、本発明試料,及
び従来試料ともバリスタ電圧は12.0V 、制限電圧
比は1.4 ,サージ耐量50A といずれも満足でき
る特性が得られている。また、従来試料の場合は絶縁抵
抗値が5.5MΩであるのに対して、本発明試料の場合
は10 MΩと向上しており、漏れ電流を改善できてい
ることがわかる。さらに静電容量では本発明試料は10
0pF と従来試料の240pF と比べて1/2 以
下となっている。
Multilayer varistor 2 thus obtained
0, varistor voltage V1mA, limiting voltage ratio V2A/V
1 mA, surge resistance A, insulation resistance value MΩ, and capacitance value pF were measured. For comparison, similar measurements were also performed on a conventional multilayer varistor in which only 5% by weight of Pr2O3 was added to the internal electrodes. Table 4 shows the results. As is clear from the table, both the inventive sample and the conventional sample have satisfactory characteristics such as a varistor voltage of 12.0 V, a limiting voltage ratio of 1.4, and a surge withstand capacity of 50 A. Furthermore, while the conventional sample had an insulation resistance value of 5.5 MΩ, the inventive sample had an improved insulation resistance value of 10 MΩ, indicating that the leakage current was improved. Furthermore, in terms of capacitance, the sample of the present invention has a capacitance of 10
0 pF, which is less than half of the 240 pF of the conventional sample.

【0023】[0023]

【発明の効果】以上のように本発明に係る積層型バリス
タによれば、内部電極にCo又は希土類元素の酸化物を
添加するとともに、Mnの酸化物を添加したので、Co
,希土類元素がMnとともに内部電極とセラミックス層
との界面に存在してポアを埋めることとなり、バリスタ
電圧やサージ耐量を劣化させることなく漏れ電流を低減
できる効果があり、さらに従来の積層型バリスタと同じ
静電容量となるよう電極面積を設定した場合は、サージ
耐量を大幅に向上できる効果が得られる。
As described above, according to the multilayer varistor according to the present invention, since Co or a rare earth element oxide is added to the internal electrode, and an Mn oxide is also added, Co
, Rare earth elements exist together with Mn at the interface between the internal electrode and the ceramic layer and fill the pores, which has the effect of reducing leakage current without deteriorating the varistor voltage or surge resistance, and is also superior to conventional multilayer varistors. If the electrode area is set so that the capacitance is the same, the surge resistance can be significantly improved.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の第1実施例による積層型バリスタを説
明するための断面図である。
FIG. 1 is a cross-sectional view for explaining a multilayer varistor according to a first embodiment of the present invention.

【図2】上記実施例の積層型バリスタの分解斜視図であ
る。
FIG. 2 is an exploded perspective view of the multilayer varistor of the above embodiment.

【図3】上記実施例の内部電極内に希土類元素,Mnが
存在した状態を示す模式図である。
FIG. 3 is a schematic diagram showing a state in which a rare earth element, Mn, is present in the internal electrode of the above example.

【図4】本発明の第2実施例による積層型バリスタを説
明するための断面図である。
FIG. 4 is a cross-sectional view for explaining a multilayer varistor according to a second embodiment of the present invention.

【図5】上記実施例の積層型バリスタの分解斜視図であ
る。
FIG. 5 is an exploded perspective view of the multilayer varistor of the above embodiment.

【符号の説明】[Explanation of symbols]

1,20  積層型バリスタ 2,21  半導体セラミックス層 3,22  内部電極 25  非接続内部電極 4,23  焼結体(積層体) 1,20 Laminated varistor 2, 21 Semiconductor ceramic layer 3,22 Internal electrode 25 Unconnected internal electrode 4,23 Sintered body (laminate)

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  半導体セラミックス層と内部電極とを
交互に重ねて積層体を形成し、上記内部電極と半導体セ
ラミックス層との界面で電圧非直線特性を得るようにし
た積層型バリスタにおいて、上記内部電極が、Co又は
希土類元素から選ばれた少なくとも1種類以上の元素の
酸化物と、Mnの酸化物とを含有する金属材料により構
成されていることを特徴とする積層型バリスタ。
1. A multilayer varistor in which semiconductor ceramic layers and internal electrodes are alternately stacked to form a laminate, and a voltage nonlinear characteristic is obtained at the interface between the internal electrode and the semiconductor ceramic layer, A multilayer varistor, wherein the electrode is made of a metal material containing an oxide of at least one element selected from Co or rare earth elements, and an oxide of Mn.
【請求項2】  請求項1において、Co又は希土類元
素がそれぞれCo2 O3,又はR2 O3 (R:希
土類元素)に換算して0.01〜20重量%、MnがM
n3 O4 に換算して0.01〜20重量%で、かつ
全体の含有量が30重量%以下となるよう含有されてい
ることを特徴とする積層型バリスタ。
2. In claim 1, Co or the rare earth element is 0.01 to 20% by weight in terms of Co2 O3 or R2 O3 (R: rare earth element), and Mn is M
A laminated varistor characterized in that n3O4 is contained in an amount of 0.01 to 20% by weight, and the total content is 30% by weight or less.
JP3099519A 1991-04-03 1991-04-03 Laminated type varistor Withdrawn JPH04306804A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3099519A JPH04306804A (en) 1991-04-03 1991-04-03 Laminated type varistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3099519A JPH04306804A (en) 1991-04-03 1991-04-03 Laminated type varistor

Publications (1)

Publication Number Publication Date
JPH04306804A true JPH04306804A (en) 1992-10-29

Family

ID=14249497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3099519A Withdrawn JPH04306804A (en) 1991-04-03 1991-04-03 Laminated type varistor

Country Status (1)

Country Link
JP (1) JPH04306804A (en)

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