JPH04306014A - Pulse waveform generating device - Google Patents

Abstract

PURPOSE:To improve the convenience by selectively outputting any of two pulse waveform groups in the inverse relation including plural non-overlap pulse waveforms. CONSTITUTION:The device is provided with inverting circuits 81-86 and selection circuits 91-96 in addition to a non-overlap pulse generating circuit 7. Either pulse waveforms PA-PF generated by the non-overlap pulse generating circuit 7 or any the pulse waveforms, the inverse of PA- the verse of PF, generated by the inverting circuits 81-86 is selectively outputted through the selection circuits 91-96.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse waveform generating device suitable for use when generating a pulse waveform to be supplied to an inverter section constituting a drive control section of an AC servo motor.

0002

[Prior Art] Conventionally, as a pulse waveform generation device, as shown in FIG.
As shown in FIG. 2, a system has been proposed that processes three input pulse waveforms P1 to P3 and outputs six pulse waveforms PA to PF. Here, input pulse waveforms P1 to P3
have different phases. In addition, the pulse waveform PA
, PB is a processed version of the input pulse waveform P1,
At H level, there is no overlap. In addition, the pulse waveforms PC and PD are the input pulse waveform P2
, and there is no overlap at the H level. In addition, pulse waveforms PE, PF
is a processed version of the input pulse waveform P3, and does not overlap at the H level.

FIG. 6 is a diagram showing an example of the use of such a pulse waveform generating device. In the figure, 1 is an AC servo motor, 2 is an inverter unit that drives the AC servo motor 1, and 3 is an inverter unit that drives the AC servo motor 1.
is a pulse waveform generator. Here, inverter section 2
The transistors 4A to 4F constituting the
N and OFF are controlled to produce a sine wave current necessary to drive the AC servo motor 1.

0004

However, the conventional pulse waveform generating device 3 is not configured to output pulse waveforms PA-PF which are inverted versions of the pulse waveforms PA-PF. Therefore, when using the conventional pulse waveform generation device 3 in a system that requires pulse waveforms PA bar to PF bar, as shown in FIG. 7, in addition to the conventional pulse waveform generation device 3, Inverter 5A
It is necessary to prepare an extra inverting circuit 6 consisting of ~5F, which poses a problem of lack of convenience.

[0005] In view of this point, the present invention provides two pulse waveforms that include a plurality of non-overlapping pulse waveforms and are in an inverse relationship to each other.
It is an object of the present invention to provide a pulse waveform generation device that can selectively output any one of a group of pulse waveforms to improve convenience.

[0006]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of a pulse waveform generation device according to the present invention. Process pulse waveforms P1 to P3,
A plurality of pulse waveforms in which one or the other level does not overlap from each of these input pulse waveforms P1 to P3, for example, two pulse waveforms PA and PB, PC and PD, PE whose H level does not overlap. and PF, inversion circuits 81 to 86 that invert the pulse waveforms PA to PF generated by the non-overlap pulse waveform generation circuit 7, and non-overlap pulse waveform generation circuit 7. The pulse waveform PA generated by or the pulse waveform PA output from the inversion circuits 81 to 86
Selection circuits 91 to 96 for selecting bar to PF bar are provided, and the pulse waveforms PA to PF generated by the non-overlapping pulse waveform generation circuit 7 are passed through the selection circuits 91 to 96.
Or the pulse waveform PA output from the inversion circuits 81 to 86
It is configured to be able to output any one of bar to PF bar.

[0007]

[Operation] According to the present invention, either the pulse waveforms PA to PF generated by the non-overlapping pulse waveform generation circuit 7 or the pulse waveforms PA to PF output from the inversion circuits 81 to 86 can be output. Can be done. That is,
It is possible to selectively output one of two pulse waveform groups that are in an inverse relationship to each other and include a plurality of non-overlapping pulse waveforms.

[0008]

[Embodiment] Referring to FIGS. 2 to 4, an embodiment of the present invention will be described in detail. The case where it is applied to a generation device will be explained as an example.

FIG. 2 is a diagram showing an embodiment of the present invention.
In the figure, 10 is a timer, and 11 is a non-overlapping pulse waveform generation circuit. Here, the timer 10 outputs eight pulse waveforms RT00 to RT07, but in this embodiment, the pulse waveforms RT00, which have the phase relationship as shown in FIGS. RT02, RT
04 is used as an input pulse waveform to the non-overlapping pulse waveform generation circuit 11.

Further, in the non-overlapping pulse waveform generation circuit 11, 12 is a control register for storing control signals for controlling the present device, and 13 is a control register for storing control signals for controlling the present device. An operation control circuit that performs operation control, 14 is a pulse waveform RT
00 is a reload counter that is controlled to operate when the level value changes; 15 is a reload counter that is controlled to operate when the level value of pulse waveform RT02 changes; 16 is a reload counter that is controlled to operate when the level value of pulse waveform RT04 changes. Then, the reload counter is controlled to operate.

Further, 17 is a reload counter 14 to 16.
18 is a frequency divider circuit that divides the frequency of the clock supplied from the outside, and 19 selects the clock supplied from the outside and the divided clock output from the frequency divider circuit 18. , is a selector that supplies one of the reload counters 14 to 16 as a count clock.

Further, 20 is a D flip-flop whose data input terminal D is supplied with a pulse waveform RT00, and whose clock signal input terminal CK is supplied with an underflow signal from the reload counter 14; a D flip-flop whose terminal D is supplied with the pulse waveform RT02 and whose clock signal input terminal CK is supplied with the underflow signal from the reload counter 15;
22 is a D flip-flop whose data input terminal D is supplied with the pulse waveform RT04, and whose clock signal input terminal CK is supplied with the underflow signal from the reload counter 16.

Further, 23 is an inverter for inverting the pulse waveform RT00, 24 is an inverter for inverting the pulse waveform RT02, and 25 is an inverter for inverting the pulse waveform RT04.

Further, 26 is an AND circuit that performs AND processing of the pulse waveform RT00 and the Q output of the D flip-flop 20 and outputs the pulse waveform PA; 27 is the pulse waveform RT
02 and the Q output of the D flip-flop 21, and outputs the pulse waveform PC. 28 is an AND circuit that performs the AND processing of the pulse waveform RT04 and the Q output of the D flip-flop 22, and outputs the pulse waveform PE. A circuit 29 performs AND processing of the output of the inverter 23 and the Q bar output of the D flip-flop 20, and generates a pulse waveform PB.
30 is an AND circuit that performs AND processing of the output of the inverter 24 and the Q-bar output of the D flip-flop 21 and outputs a pulse waveform PD; 31 is an AND circuit that outputs the output of the inverter 25 and the Q-bar of the D flip-flop 22; AN that performs AND processing of the output and outputs the pulse waveform PF
This is the D circuit. Note that the activation and inactivation of these AND circuits 26 to 31 are controlled by an output control signal.

Further, 32 to 37 are pulse waveforms PA to P output from the non-overlapping pulse waveform generation circuit 11.
Inverter to invert F, 38 to 43 are select signals S
Pulse waveforms PA to PF controlled by L1 and output from the non-overlapping pulse waveform generation circuit 11 and pulse waveforms PA to P output from the inverters 32 to 37.
A selector for selecting F bar, 44 is a select signal SL2
This is a selector that selects the outputs of the selectors 38 to 43 and the output pulses RT00 to RT05 of the timer 10. Note that the select signal SL1 that controls the select operations of the selectors 38 to 43 may be a signal (gate signal) that is logical with other signals, or may use the value of a register. However, the signal may be supplied from outside.

FIGS. 3 and 4 are time charts for explaining the operation of this embodiment, and in this embodiment,
When the pulse waveform RT00 is inverted from the L level to the H level, the reload counter 14 performs counting as shown in FIG. 3d(x). When an underflow occurs, an underflow signal is supplied from the reload counter 14 to the clock input terminal CK of the D flip-flop 20, the H level value of the pulse waveform RT00 is latched, and the Q output of the D flip-flop 20 is As shown in 3e,
Inverted from L level to H level.

Next, when the pulse waveform RT00 is inverted from the H level to the L level, the reload counter 14 changes as shown in FIG. 3d.
Count is performed as shown in (y). When an underflow occurs, an underflow signal is supplied from the reload counter 14 to the clock input terminal CK of the D flip-flop 20, the L level value of the pulse waveform RT00 is latched, and the Q output of the D flip-flop 20 is 3
As shown in e, it is inverted from H level to L level.

Here, in the AND circuit 26, the pulse waveform RT00 and the Q output of the D flip-flop 20 are
Since the ND processing is performed, the output, ie, the pulse waveform PA, becomes as shown in FIG. 3f.

On the other hand, the output of the inverter 23 has a pulse waveform that is an inversion of the pulse waveform RT00, as shown in FIG.
As shown in h, the waveform is an inversion of the Q output of the D flip-flop 20.

Here, in the AND circuit 29, the output of the inverter 23 and the Q bar output of the D flip-flop 20 are ANDed, so the output, that is, the pulse waveform PB is as shown in FIG. 3i. The pulse waveform PA is a waveform that does not overlap at the H level.

Furthermore, when the pulse waveform RT02 is inverted from the L level to the H level, the reload counter 15 changes as shown in FIG.
Counting is performed as shown in j(x). When an underflow occurs, an underflow signal is supplied from the reload counter 15 to the clock input terminal CK of the D flip-flop 21, the H level value of the pulse waveform RT02 is latched, and the Q output of the D flip-flop 21 is As shown in 3k, it is inverted from L level to H level.

Next, when the pulse waveform RT02 is inverted from the H level to the L level, the reload counter 15 changes as shown in FIG.
Count is performed as shown in (y). When an underflow occurs, an underflow signal is supplied from the reload counter 15 to the clock input terminal CK of the D flip-flop 21, the L level value of the pulse waveform RT02 is latched, and the Q output of the D flip-flop 21 is 3
As shown in k, it is inverted from H level to L level.

Here, in the AND circuit 27, the pulse waveform RT02 and the Q output of the D flip-flop 21 are
Since the ND processing is performed, its output, ie, the pulse waveform PC, becomes as shown in FIG. 3l.

On the other hand, the output of the inverter 24 has a pulse waveform that is an inversion of the pulse waveform RT02, as shown in FIG.
As shown in n, the waveform is an inversion of the Q output of the D flip-flop 21.

Here, in the AND circuit 30, the output of the inverter 24 and the Q-bar output of the D flip-flop 21 are ANDed, so the output, that is, the pulse waveform PD, is as shown in FIG. 3o. The pulse waveform PC is a waveform that does not overlap at the H level.

Further, when the pulse waveform RT04 is inverted from the L level to the H level, the reload counter 16 is set as shown in FIG.
Counting is performed as shown in p(x). When an underflow occurs, an underflow signal is supplied from the reload counter 16 to the clock input terminal CK of the D flip-flop 22, the H level value of the pulse waveform RT04 is latched, and the Q output of the D flip-flop 22 is As shown in 3q, it is inverted from L level to H level.

Next, when the pulse waveform RT04 is inverted from the H level to the L level, the reload counter 16 changes to the value shown in FIG.
Count is performed as shown in (y). When an underflow occurs, an underflow signal is supplied from the reload counter 16 to the clock input terminal CK of the D flip-flop 22, the L level value of the pulse waveform RT04 is latched, and the Q output of the D flip-flop 22 is 3
As shown in q, it is inverted from H level to L level.

Here, in the AND circuit 28, the pulse waveform RT04 and the Q output of the D flip-flop 22 are
Since the ND processing is performed, its output, that is, the pulse waveform PE becomes as shown in FIG. 3r.

On the other hand, the output of the inverter 25 has a pulse waveform that is an inversion of the pulse waveform RT04, as shown in FIG.
As shown at t, the waveform is an inversion of the Q output of the D flip-flop 22.

Here, in the AND circuit 31, the output of the inverter 25 and the Q bar output of the D flip-flop 22 are ANDed, so the output, that is, the pulse waveform PF is as shown in FIG. 3u. The pulse waveform PE is a waveform that does not overlap at the H level.

Therefore, the outputs of the inverters 32 to 37 are not shown in FIG.
Pulse waveforms PA bar to PF bar can be obtained by inverting the pulse waveforms PA to PF shown in f, l, r, i, o, and u. Here, FIG. 4 shows pulse waveforms RT00 and RT02.
, RT04, pulse waveforms PA to PF, and pulse waveform P
It is a diagram illustrating the relationship between A bar and PF bar.

Therefore, the selector 44 selects the outputs of the selectors 38 to 43, and the selector 38
Non-overlapping pulse waveform generation circuit 1 by ~43
When selecting the output of No. 1, the pulse waveforms PA to PF shown in FIGS.
And the inverters 32 to 3 are selected by the selectors 38 to 43.
When selecting the output No. 7, the pulse waveforms PA bar to PF bar shown in FIGS. 4j to 4o can be output to the outside. In this embodiment, the pulse waveforms RT00 to RT05 of the timer 10 can also be selected.

As described above, according to this embodiment, the pulse waveforms PA to PF output by the non-overlapping pulse waveform generation circuit 11 or the inverted pulse waveforms PA to PF are selectively generated. Since it is possible to output the information to the user, the convenience can be improved.

In this embodiment, when setting the output control signal to the L level, the output of the non-overlapping waveform generation circuit 11 is fixed to the L level, and the output of the inverter 3 is fixed to the L level.
The outputs of 2 to 37 can be fixed at H level, and they can also be selectively output according to the requirements of the system used. Further, a NAND circuit can be used instead of the AND circuits 26 to 31, and in this case, when setting the output control signal to L level,
The output of the non-overlapping pulse waveform generation circuit 11 can also be fixed at H level.

[0035]

[Effects of the Invention] According to the present invention, it is possible to selectively output one of two groups of pulse waveforms that include a plurality of non-overlapping pulse waveforms and are in an inverted relationship with each other, thereby improving convenience. be able to.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a time chart for explaining the operation of an embodiment of the present invention.

FIG. 4 is a time chart for explaining the operation of an embodiment of the present invention.

FIG. 5 is a diagram showing a conventional pulse waveform generation device.

FIG. 6 is a diagram showing an example of use of a conventional pulse waveform generation device.

FIG. 7 is a diagram for explaining a problem that a conventional pulse waveform generation device has.

[Explanation of symbols]

7 Non-overlapping waveform generation circuit 81-86 Inversion circuit 91-96 Selection circuit

Claims (2)

[Claims] Claim 1: A plurality of input pulse waveforms (P1
~P3), and process the plurality of input pulse waveforms (P1~P3).
3) from each of which the levels of one or the other do not overlap (PA, PB), (PC, P
D), a non-overlapping pulse waveform generation circuit (7) that generates (PE, PF), and a pulse waveform (PA to PF) generated by the non-overlap pulse waveform generation circuit (7).
and the pulse waveform generated by the inverting circuit (81 to 86) and the non-overlapping pulse waveform generation circuit (7) or the pulse waveform (PA bar to PF bar) output from the inverting circuit (81 to 86). A selection circuit (91) that selects
- 96), and the pulse waveforms (PA to PF) generated by the non-overlapping pulse waveform generation circuit (7) or the inversion circuit (8) are provided.
1 to 86) output from the pulse waveform (PA bar to PF
1. A pulse waveform generation device characterized in that it is configured to be able to output any of the following: 2. The non-overlapping pulse waveform generation circuit (7) is configured such that all its outputs can be fixed at H level or L level by an output control signal. pulse waveform generator.