JPH04305946A - Film carrier board - Google Patents
Film carrier boardInfo
- Publication number
- JPH04305946A JPH04305946A JP3070005A JP7000591A JPH04305946A JP H04305946 A JPH04305946 A JP H04305946A JP 3070005 A JP3070005 A JP 3070005A JP 7000591 A JP7000591 A JP 7000591A JP H04305946 A JPH04305946 A JP H04305946A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- carrier substrate
- ceramic thin
- film carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010408 film Substances 0.000 claims abstract description 85
- 239000010409 thin film Substances 0.000 claims abstract description 56
- 239000000919 ceramic Substances 0.000 claims abstract description 36
- 239000004020 conductor Substances 0.000 claims abstract description 14
- 238000002156 mixing Methods 0.000 claims abstract description 10
- 238000010884 ion-beam technique Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 39
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000001678 irradiating effect Effects 0.000 abstract description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 16
- 150000002500 ions Chemical class 0.000 description 14
- 238000000034 method Methods 0.000 description 13
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 230000017525 heat dissipation Effects 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 239000002390 adhesive tape Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 3
- 229920001646 UPILEX Polymers 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- -1 ether ketone Chemical class 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000035699 permeability Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000004697 Polyetherimide Substances 0.000 description 1
- 239000004721 Polyphenylene oxide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 206010040844 Skin exfoliation Diseases 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- RTZKZFJDLAIYFH-UHFFFAOYSA-N ether Substances CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 229910052839 forsterite Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- HCWCAKKEBCNQJP-UHFFFAOYSA-N magnesium orthosilicate Chemical compound [Mg+2].[Mg+2].[O-][Si]([O-])([O-])[O-] HCWCAKKEBCNQJP-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229920000570 polyether Polymers 0.000 description 1
- 229920001601 polyetherimide Polymers 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】この発明は、ＩＣチップ等の半導
体素子を実装するのに好適に用いられるフィルムキャリ
ア基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a film carrier substrate suitably used for mounting semiconductor elements such as IC chips.
【０００２】0002
【従来の技術】従来より、ＩＣチップ等の半導体素子を
電子機器の基板に実装する場合、この実装を高速で行う
と共に、安定した性能を有する基板を得るため、テープ
状のフィルムキャリア基板にＩＣチップ等の半導体素子
をのせ、ボンディングにより、半導体素子をフィルムキ
ャリア基板に組み込むＴＡＢ（ＴａｐｅＡｕｔｏｍａｔ
ｅｄ Ｂｏｎｄｉｎｇ）方式が用いられている。2. Description of the Related Art Conventionally, when semiconductor elements such as IC chips are mounted on the substrate of electronic equipment, in order to perform the mounting at high speed and to obtain a substrate with stable performance, IC chips are mounted on a tape-shaped film carrier substrate. TAB (TapeAutomatic
ed Bonding) method is used.
【０００３】上記ＴＡＢ方式に用いられるフィルムキャ
リア基板は、ポリイミドまたはガラスエポキシからなる
ベースフィルムを有している。そして、該ベースフィル
ムに、所定形状の孔を形成した後、導体回路を形成し、
インナーリード及びアウターリードを設けたものである
。上記ベースフィルムとしては、通常厚さ５０乃至１２
５μｍ、幅３５，７０または１４０ｍｍのものが用いら
れる。また、ベースフィルムに銅箔を接着する接着剤と
しては、エポキシ系、アクリル系、ポリイミド系等の接
着剤が用いられる。そして、これら接着剤を１０乃至２
０μｍの厚みでベースフィルム上に塗布し、銅箔を貼り
合わせることにより、ベースフィルムに銅箔を接着する
。The film carrier substrate used in the TAB method has a base film made of polyimide or glass epoxy. After forming holes of a predetermined shape in the base film, forming a conductor circuit,
It is equipped with an inner lead and an outer lead. The base film usually has a thickness of 50 to 12
Those with a width of 5 μm and a width of 35, 70 or 140 mm are used. Further, as the adhesive for bonding the copper foil to the base film, an epoxy-based adhesive, an acrylic-based adhesive, a polyimide-based adhesive, or the like is used. Then, apply these adhesives for 10 to 2
The copper foil is bonded to the base film by coating the base film to a thickness of 0 μm and bonding the copper foil together.
【０００４】また、上記フィルムキャリア基板では、実
装されたＩＣチップ等に対する水蒸気や熱の影響を排除
し、信頼性を高めるため、実装されたＩＣチップ等を樹
脂等の有機物内に封入することが行われている。また、
その導体回路は、ベースフィルム上に接着剤を介して貼
り合わせた金属薄膜か、メッキや蒸着等の方法により形
成された金属層をエッチングすることにより形成される
（特開平２─１１２２４８号公報、特開平２─２０５３
３３号公報、特開平１─１３５０３６号公報、特開平６
１─１７２３６１号公報等参照）。[0004] Furthermore, in the above-mentioned film carrier substrate, in order to eliminate the effects of water vapor and heat on the mounted IC chips, etc., and to improve reliability, the mounted IC chips, etc. can be encapsulated in an organic material such as resin. It is being done. Also,
The conductor circuit is formed by etching a metal thin film bonded onto a base film via an adhesive, or a metal layer formed by a method such as plating or vapor deposition (Japanese Unexamined Patent Publication No. 2-112248, Unexamined Japanese Patent Publication No. 2-2053
Publication No. 33, JP-A-1-135036, JP-A-6
1-172361, etc.).
【０００５】[0005]
【発明が解決しようとする課題】しかし、ベースフィル
ムとして用いられるポリイミドフィルムは、吸湿性の高
いフィルムであり常態で１．５乃至２．５重量％の吸水
率を示すと共に、熱膨張係数が大きく、ＩＣチップ、導
体薄膜、シリコーン樹脂等のフィルムが接している素材
との熱膨張係数の差が大きいため、温度変化が大きな環
境や、高温多湿雰囲気中で使用した場合、導体回路が剥
離したり、特性が劣化したりするという問題があった。[Problems to be Solved by the Invention] However, the polyimide film used as the base film is a highly hygroscopic film, exhibiting a water absorption rate of 1.5 to 2.5% by weight under normal conditions, and a large coefficient of thermal expansion. , IC chips, conductor thin films, silicone resins, and other films have a large difference in thermal expansion coefficient from the materials they are in contact with, so if they are used in environments with large temperature changes or in high-temperature and humid environments, the conductor circuits may peel off. , there was a problem that the characteristics deteriorated.
【０００６】さらに、最近ではＩＣチップを高密度で実
装することが行われており、ＩＣチップからの発熱量が
大きいものとなっている。しかし、ポリイミドフィルム
は熱放散性が悪いため、ＩＣチップから発生する熱を充
分放散することができず、フィルムキャリア基板及びそ
れに実装された部品が高温となり、誤作動を生じるとい
う問題もあった。[0006]Furthermore, recently, IC chips have been mounted with high density, and the amount of heat generated from the IC chips has become large. However, since the polyimide film has poor heat dissipation properties, it cannot sufficiently dissipate the heat generated from the IC chip, resulting in a problem in that the film carrier substrate and the components mounted thereon become hot, resulting in malfunction.
【０００７】水分や温度に起因した特性の劣化を防止す
るために、フィルムキャリア基板のうち、ＩＣチップが
実装されている部分を樹脂等で被覆することが行われて
いるが、この場合、ＩＣチップを実装する際に非常に手
間がかかるという問題があった。本発明は、上記問題に
鑑みてなされたものであって、温度変化や水分の影響を
受け難く、熱放散性に優れ、且つＩＣチップを効率良く
実装することができるフィルムキャリア基板を提供する
ことを目的とする。[0007] In order to prevent deterioration of characteristics due to moisture and temperature, the portion of the film carrier substrate on which the IC chip is mounted is coated with resin or the like. There was a problem in that it took a lot of time and effort to mount the chip. The present invention has been made in view of the above problems, and an object of the present invention is to provide a film carrier substrate that is not easily affected by temperature changes and moisture, has excellent heat dissipation properties, and can efficiently mount IC chips. With the goal.
【０００８】[0008]
【課題を解決するための手段】上記問題を解決するため
の本発明に係るフィルムキャリア基板は、半導体素子を
実装するためのフィルムキャリア基板であって、ベース
フィルム表面に、セラミック薄膜が重エネルギーイオビ
ーム照射により、界面でイオンミキシングが発生した状
態で接合され、且つ上記セラミック薄膜上に導体回路が
形成されていることを特徴とする。[Means for Solving the Problems] A film carrier substrate according to the present invention for solving the above-mentioned problems is a film carrier substrate for mounting semiconductor elements, and a ceramic thin film is provided on the surface of the base film to absorb heavy energy ions. The ceramic thin film is bonded with ion mixing occurring at the interface by beam irradiation, and a conductor circuit is formed on the ceramic thin film.
【０００９】また、上記セラミック薄膜は、ベースフィ
ルム表面の半導体素子が実装される部分に形成してもよ
く、その厚さは、０．１乃至１０μｍが好ましい。The ceramic thin film may be formed on the surface of the base film at a portion where a semiconductor element is mounted, and its thickness is preferably 0.1 to 10 μm.
【００１０】0010
【作用】本発明のフィルムキャリア基板は、耐湿性及び
熱放散性に優れているセラミック薄膜がベースフィルム
表面に形成されているので、このフィルムキャリア基板
は耐湿性および熱放散性に優れている。また、セラミッ
ク薄膜は、熱膨張係数が小さいものであり、該セラミッ
ク薄膜上に導体回路が形成されているので、導体回路が
セラミック薄膜から剥離するおそれがない。[Function] The film carrier substrate of the present invention has a ceramic thin film having excellent moisture resistance and heat dissipation properties formed on the surface of the base film, so this film carrier substrate has excellent moisture resistance and heat dissipation properties. Further, since the ceramic thin film has a small coefficient of thermal expansion and the conductive circuit is formed on the ceramic thin film, there is no fear that the conductive circuit will peel off from the ceramic thin film.
【００１１】さらに、ベースフィルムとセラミック薄膜
との界面では、重エネルギーイオンビーム照射によるイ
オンミキシングが生じているので、セラミック薄膜はベ
ースフィルムに強固に接合されている。以下、本発明を
より詳細に説明する。図１は、本発明に係るフィルムキ
ャリア基板Ａの一実施例にＩＣチップ５を実装した状態
を示す平面図であり、図２はその要部断面図である。そ
して、図３はフィルムキャリア基板Ａに実装されたＩＣ
チップ５をワイヤーボンディングにより接続した状態を
示す要部断面図である。Furthermore, since ion mixing occurs at the interface between the base film and the ceramic thin film due to heavy energy ion beam irradiation, the ceramic thin film is firmly bonded to the base film. The present invention will be explained in more detail below. FIG. 1 is a plan view showing a state in which an IC chip 5 is mounted on an embodiment of a film carrier substrate A according to the present invention, and FIG. 2 is a sectional view of a main part thereof. FIG. 3 shows the IC mounted on the film carrier substrate A.
FIG. 3 is a cross-sectional view of a main part showing a state in which chips 5 are connected by wire bonding.
【００１２】このフィルムキャリア基板Ａを形成する場
合、スプロケット穴１１が形成されたベースフィルム１
の所定位置に、ドリル、レーザ等を用いて、ベースフィ
ルム１の両面に形成される導体回路３間の導通を確保す
るための貫通孔１２を形成する。次いで、ＣＶＤ法等の
従来公知の方法を用い、ベースフィルム１表面にセラミ
ック薄膜２を形成する。When forming this film carrier substrate A, a base film 1 with sprocket holes 11 formed therein is used.
A through hole 12 is formed at a predetermined position using a drill, a laser, or the like to ensure continuity between the conductor circuits 3 formed on both sides of the base film 1. Next, a ceramic thin film 2 is formed on the surface of the base film 1 using a conventionally known method such as a CVD method.
【００１３】セラミック薄膜２をＣＶＤ法等により、ベ
ースフィルム１上に形成しただけでは、該セラミック薄
膜２はベースフィルム１上に物理的に付着しているのみ
である。このため、重エネルギーイオンビームを照射し
て、セラミック薄膜２とベースフィルム１との界面でイ
オンミキシングを発生させて、セラミック薄膜２をベー
スフィルム１に強固に接合する。[0013] If the ceramic thin film 2 is simply formed on the base film 1 by the CVD method or the like, the ceramic thin film 2 is only physically attached to the base film 1. For this purpose, a heavy energy ion beam is irradiated to generate ion mixing at the interface between the ceramic thin film 2 and the base film 1, thereby firmly bonding the ceramic thin film 2 to the base film 1.
【００１４】そして、該セラミック薄膜２上に導体回路
３を形成し、フィルムキャリア基板Ａを得る。このフィ
ルムキャリア基板ＡにＩＣチップ５を実装する場合は、
図２に示すように、熱伝導性接着剤６によりＩＣチップ
５をフィルムキャリア基板Ａに接着する。Then, a conductor circuit 3 is formed on the ceramic thin film 2 to obtain a film carrier substrate A. When mounting the IC chip 5 on this film carrier substrate A,
As shown in FIG. 2, the IC chip 5 is bonded to the film carrier substrate A using a thermally conductive adhesive 6.
【００１５】そして、図３に示すように、金、アルミニ
ウム、銅等からなるワイヤー４によりＩＣチップ５の端
子と導体回路３とを接続する。この際、フィルムキャリ
ア基板Ａが、前述のように、耐湿性及び熱放散性に優れ
たものであるので、特別な工程を行う必要がない。上記
ベースフィルム１としては、例えばポリイミド、ポリエ
ーテル、ポリエーテルイミド、エーテルケトン、ガラス
エポキシ等の、厚さ５０乃至１５０μｍ程度のフィルム
を用いることができ、特にポリイミドフィルム（例えば
、デュポン社製の「カプトンフィルム」、宇部興産社製
の「ユービレックス」）を用いることが好ましい。Then, as shown in FIG. 3, the terminals of the IC chip 5 and the conductive circuit 3 are connected by wires 4 made of gold, aluminum, copper, or the like. At this time, since the film carrier substrate A has excellent moisture resistance and heat dissipation properties as described above, there is no need to perform any special process. As the base film 1, a film having a thickness of about 50 to 150 μm, such as polyimide, polyether, polyetherimide, ether ketone, glass epoxy, etc., can be used, and in particular, a polyimide film (for example, " It is preferable to use ``Kapton Film'' and ``Ubilex'' manufactured by Ube Industries, Ltd.).
【００１６】上記ベースフィルム１上に形成されるセラ
ミック薄膜２は、アルミナ（Ａｌ２ Ｏ３ ）、サファ
イヤ、フォルステライト（ＭｇＯ・ＳｉＯ２ ）、石英
（ＳｉＯ２ ）、ルチル（ＴｉＯ２ ）、窒化チタン（
ＴｉＮ）、炭化珪素（ＳｉＣ）等からなるものを挙げる
ことができる。また、上記セラミック薄膜２は、ベース
フィルム１の片面もしくは両面に形成すればよいが、防
湿性の点、フィルムキャリア基板Ａの熱膨張係数を低く
抑える上から、両面に形成することが好ましい。さらに
、セラミック薄膜１は、ベースフィルム１の表面全体に
形成してもよいが、ＩＣチップ５が実装される部分にの
み形成するのが、経済的である。The ceramic thin film 2 formed on the base film 1 is made of alumina (Al2O3), sapphire, forsterite (MgO.SiO2), quartz (SiO2), rutile (TiO2), titanium nitride (
TiN), silicon carbide (SiC), and the like. The ceramic thin film 2 may be formed on one or both sides of the base film 1, but is preferably formed on both sides from the viewpoint of moisture resistance and keeping the coefficient of thermal expansion of the film carrier substrate A low. Furthermore, although the ceramic thin film 1 may be formed on the entire surface of the base film 1, it is economical to form it only on the portion where the IC chip 5 is mounted.
【００１７】ベースフィルム１とセラミック薄膜２との
界面でイオンミキシングを発生させる場合、加速電圧０
．５乃至１０ＭｅＶ、電流１乃至１００μＡで、水素、
ヘリウム、酸素、窒素、アルゴン、硼素等のイオンを１
×１０１５乃至１×１０１８個／ｃｍ２ の割合で照射
する。照射するイオンの加速電圧は、セラミック薄膜１
の厚みを考慮して決定し、照射するイオン種や照射電流
量はイオンミキシング効果を確認しつつ選定する。例え
ば、セラミック薄膜２が、厚さ０．１５乃至５μｍのア
ルミナや窒化チタンからなる場合、加速電圧４ＭｅＶで
、アルゴンまたは硼素イオンを１×１０１７乃至５×１
０１７個／ｃｍ２ の割合で照射すれば、充分なイオン
ミキシング効果が得られ、該セラミック薄膜２をベース
フィルム１に強固に接合することができる。When ion mixing is generated at the interface between the base film 1 and the ceramic thin film 2, the acceleration voltage is 0.
．． At 5 to 10 MeV and a current of 1 to 100 μA, hydrogen,
Ions such as helium, oxygen, nitrogen, argon, boron, etc.
Irradiation is performed at a rate of ×1015 to 1×1018 particles/cm2. The acceleration voltage of the irradiated ions is
The type of ions to be irradiated and the amount of irradiation current are selected while checking the ion mixing effect. For example, when the ceramic thin film 2 is made of alumina or titanium nitride with a thickness of 0.15 to 5 μm, argon or boron ions are
By irradiating at a rate of 0.17 ions/cm2, a sufficient ion mixing effect can be obtained and the ceramic thin film 2 can be firmly bonded to the base film 1.
【００１８】セラミック薄膜２上に導体回路３を形成す
る方法としては、セラミック薄膜２の表面に接着剤を介
して金属薄膜を積層し、その金属薄膜の不要部分をエッ
チング除去するいわゆるサブストラクティブ法、セラミ
ック薄膜１表面の導体回路２として必要な部分にのみ金
属材料を堆積させるアディティブ法、サブストラクティ
ブ法とアディティブ法とを組み合わせたセミストラクテ
ィブ法等の従来公知の方法を適用することができる。特
に、スパッタリング、クラスターイオンビーム等を用い
て、銅またはアルミニウムを、導体回路が形成される部
分にのみ、０．２乃至５．０μｍの厚みで蒸着し、湿式
メッキにより１８乃至７０μｍの厚みを有する導体回路
を形成することが好ましい。The method for forming the conductor circuit 3 on the ceramic thin film 2 is a so-called substructive method in which a metal thin film is laminated on the surface of the ceramic thin film 2 via an adhesive, and unnecessary portions of the metal thin film are removed by etching. Conventionally known methods can be applied, such as an additive method in which the metal material is deposited only on the portions of the surface of the ceramic thin film 1 that are necessary for the conductor circuit 2, and a semistructural method that is a combination of a substructive method and an additive method. In particular, using sputtering, cluster ion beam, etc., copper or aluminum is deposited to a thickness of 0.2 to 5.0 μm only on the part where the conductor circuit is formed, and wet plating is used to deposit copper or aluminum to a thickness of 18 to 70 μm. Preferably, a conductor circuit is formed.
【００１９】[0019]
【実施例】実施例
厚さ７５μｍのユーピレックスフィルム（宇部興産株式
会社製）の表面に、ＣＶＤ装置を用いて厚さ２０００Å
のアルミナ薄膜を形成した。このままの状態では、フィ
ルムを屈曲したところ、薄膜にクラックが入った。また
、粘着テープをアルミナ薄膜表面に粘着させ、粘着テー
プを剥がしたところ、アルミナ薄膜が全面的に剥離した
。[Example] The surface of a 75 μm thick Upilex film (manufactured by Ube Industries, Ltd.) was coated with a 200 Å thick film using a CVD device.
An alumina thin film was formed. In this state, when the film was bent, cracks appeared in the thin film. Furthermore, when adhesive tape was attached to the surface of the alumina thin film and the adhesive tape was peeled off, the alumina thin film was completely peeled off.
【００２０】蒸着したアルミナ薄膜に、１ＭｅＶイオン
照射装置を用いて、Ａｒイオンを１０μＡの条件で５×
１０１６個／ｃｍ２ の割合で照射した。その結果、ア
ルミナ薄膜のアルミニウム原子が、ユーピレックスフィ
ルム中に侵入しているとともに、ユーピレッスルフィル
ム中の炭素原子がアルミナ薄膜中に侵入していることが
確認され、ユーピレックスフィルムとアルミナ薄膜との
界面付近でイオンミキシングが生じていることがわかっ
た。The deposited alumina thin film was irradiated with Ar ions 5× at 10 μA using a 1 MeV ion irradiation device.
Irradiation was performed at a rate of 1016 particles/cm2. As a result, it was confirmed that the aluminum atoms in the alumina thin film had penetrated into the Upilex film, and that the carbon atoms in the Upilex film had penetrated into the alumina thin film. It was found that ion mixing occurred near the interface with the thin film.
【００２１】次いで、粘着テープをアルミナ薄膜表面に
粘着させ、粘着テープを剥がしたところ、アルミナ薄膜
は全く剥離しなかった。このことより、ベースフィルム
にアルミナ薄膜が強固に接合していることがわかる。そ
して、アルミナ薄膜表面に、エポキシ系接着剤を塗布し
、乾燥させた後、インアーリードとアウターリードとが
取れるように、前記フィルムを金型で打抜きその後３５
μｍの圧延銅箔を熱ラミネートし、接着剤を硬化させた
。[0021] Next, an adhesive tape was attached to the surface of the alumina thin film, and when the adhesive tape was peeled off, the alumina thin film did not peel off at all. This shows that the alumina thin film is firmly bonded to the base film. After applying an epoxy adhesive to the surface of the alumina thin film and drying it, the film was punched out with a die so that the inner leads and outer leads could be removed.
The μm rolled copper foil was heat laminated and the adhesive was cured.
【００２２】次いで、銅箔面に回路パターンを形成し、
フィルムキャリア基板をえた。このフィルムキャリア基
板の水蒸気透過率と熱膨張率を測定したことろ、水蒸気
透過率は、フィルム本体が２．１ｇ／ｍ２ ／日／ｍｍ
であるのに対し、上記フィルムキャリア基板は０．０３
２ｇ／ｍ２ ／日／ｍｍであった。また、熱膨張率はフ
ィルム本体が１．２×１０−５／℃であるのに対し、上
記フィルムキャリア基板は０．８×１０−５／℃であっ
た。Next, a circuit pattern is formed on the copper foil surface,
I got a film carrier board. The water vapor permeability and thermal expansion coefficient of this film carrier substrate were measured, and it was found that the film body had a water vapor permeability of 2.1 g/m2/day/mm.
On the other hand, the film carrier substrate is 0.03
It was 2g/m2/day/mm. Further, the coefficient of thermal expansion of the film body was 1.2 x 10-5/°C, while that of the film carrier substrate was 0.8 x 10-5/°C.
【００２３】また、上記実施例で得たフィルムキャリア
基板、およびアルミナ薄膜を形成していない他は、実施
例と同様に形成したフィルムキャリア基板にＩＣチップ
のそれぞれにＩＣチップを実装し、ＩＣチップ表面に熱
電対を接続し、ＩＣへの負荷電流を流して，それぞれの
場合についてＩＣチップの温度上昇を調べた。その結果
、アルミナ薄膜のないフィルムキャリア基板に実装した
ＩＣチップは、アルミナ薄膜が蒸着された上記実施例の
フィルムキャリア基板にくらべて、５０〜７０℃昇温し
た。Further, IC chips were mounted on each of the IC chips on the film carrier substrate obtained in the above example and the film carrier substrate formed in the same manner as in the example except that the alumina thin film was not formed. A thermocouple was connected to the surface, a load current was applied to the IC, and the temperature rise of the IC chip was investigated in each case. As a result, the temperature of the IC chip mounted on the film carrier substrate without the alumina thin film increased by 50 to 70° C. compared to the film carrier substrate of the above example on which the alumina thin film was deposited.
【００２４】さらに、上記実施例で得たフィルムキャリ
ア基板に、−６０乃至１２５℃の冷熱サイクル試験を実
施した結果、冷熱サイクルを１０００回行った後でも、
誤作動は起こらなかった。Furthermore, the film carrier substrate obtained in the above example was subjected to a thermal cycle test at -60 to 125°C, and as a result, even after 1000 thermal cycles,
No malfunctions occurred.
【００２５】[0025]
【発明の効果】以上のように、本発明のフィルムキャリ
ア基板は、ベースフィルム表面に、耐湿性に優れたセラ
ミック薄膜が強固に接合されているので、水分の影響を
受け難い。また、上記セラミック薄膜は熱膨張係数が小
さく、該セラミック薄膜上に導体回路が形成されている
ので、導体回路の剥離が生じる虞れがない。さらに、セ
ラミック薄膜は、熱放散性に優れており、このフィルム
キャリア基板に実装されたＩＣチップ等から発生した熱
を効率良く放散することができるので、当該ＩＣチップ
等が誤作動することを防止できる。As described above, the film carrier substrate of the present invention has a ceramic thin film with excellent moisture resistance firmly bonded to the surface of the base film, and therefore is not easily affected by moisture. Furthermore, since the ceramic thin film has a small coefficient of thermal expansion and the conductive circuit is formed on the ceramic thin film, there is no risk of peeling of the conductive circuit. Furthermore, ceramic thin films have excellent heat dissipation properties and can efficiently dissipate heat generated from IC chips etc. mounted on this film carrier substrate, thereby preventing malfunctions of the IC chips etc. can.
【００２６】また、ＩＣチップ等を実装する際に特別な
工程を行う必要がないので、効率良くＩＣチップの実装
を行うことができる。[0026] Furthermore, since there is no need to perform any special process when mounting an IC chip or the like, the IC chip can be mounted efficiently.
【図１】本発明のフィルムキャリア基板にＩＣを実装し
た状態を示す平面図である。FIG. 1 is a plan view showing a state in which an IC is mounted on a film carrier substrate of the present invention.
【図２】図１に示したフィルムキャリア基板を示す要部
断面図である。FIG. 2 is a sectional view of a main part of the film carrier substrate shown in FIG. 1;
【図３】ボンデイングワイヤによりＩＣチップを実装し
たフィルムキャリア基板を示す断面図である。FIG. 3 is a cross-sectional view showing a film carrier substrate on which an IC chip is mounted using bonding wires.
１ ベースフィルム ２ セラミック薄膜 ３ 導体回路 ５ ＩＣチップ Ａ フィルムキャリア基板 1 Base film 2 Ceramic thin film 3 Conductor circuit 5 IC chip A Film carrier substrate
Claims (3)
リア基板であって、ベースフィルム表面に、セラミック
薄膜が重エネルギーイオビーム照射により、界面でイオ
ンミキシングが発生した状態で接合され、且つ上記セラ
ミック薄膜上に導体回路が形成されていることを特徴と
するフィルムキャリア基板。1. A film carrier substrate for mounting a semiconductor element, wherein a ceramic thin film is bonded to a base film surface by heavy energy ion beam irradiation with ion mixing occurring at the interface, and the ceramic thin film is bonded to the base film surface with ion mixing occurring at the interface. A film carrier substrate having a conductor circuit formed thereon.
れる部分に、セラミック薄膜が形成されている請求項１
記載のフィルムキャリア基板。Claim 2: Claim 1, wherein a ceramic thin film is formed on a portion of the surface of the base film where a semiconductor element is mounted.
The film carrier substrate described.
を有する請求項１記載のフィルムキャリア基板。3. The film carrier substrate according to claim 1, comprising a ceramic thin film having a thickness of 0.1 to 10 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3070005A JPH04305946A (en) | 1991-04-02 | 1991-04-02 | Film carrier board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3070005A JPH04305946A (en) | 1991-04-02 | 1991-04-02 | Film carrier board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04305946A true JPH04305946A (en) | 1992-10-28 |
Family
ID=13419059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3070005A Pending JPH04305946A (en) | 1991-04-02 | 1991-04-02 | Film carrier board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04305946A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010225943A (en) * | 2009-03-24 | 2010-10-07 | Toshiba Corp | Semiconductor device |
-
1991
- 1991-04-02 JP JP3070005A patent/JPH04305946A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010225943A (en) * | 2009-03-24 | 2010-10-07 | Toshiba Corp | Semiconductor device |
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