JPH0430564A - High power hybrid integrated circuit device - Google Patents
High power hybrid integrated circuit deviceInfo
- Publication number
- JPH0430564A JPH0430564A JP2138747A JP13874790A JPH0430564A JP H0430564 A JPH0430564 A JP H0430564A JP 2138747 A JP2138747 A JP 2138747A JP 13874790 A JP13874790 A JP 13874790A JP H0430564 A JPH0430564 A JP H0430564A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- power
- substrates
- board
- lead terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 230000002093 peripheral effect Effects 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims description 34
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 239000011889 copper foil Substances 0.000 claims description 6
- 239000004020 conductor Substances 0.000 abstract 4
- 230000010354 integration Effects 0.000 abstract 1
- 239000011347 resin Substances 0.000 description 18
- 229920005989 resin Polymers 0.000 description 18
- 239000004065 semiconductor Substances 0.000 description 9
- 238000007789 sealing Methods 0.000 description 8
- 239000004593 Epoxy Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910001374 Invar Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Combinations Of Printed Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
(イ)産業上の利用分野
本発明は高出力用回路基板とそれを制御する制御用回路
基板とがケース材を介して一体化された高出力用混成集
積回路装置に関し、更に詳しくは高出力用混成集積回路
装置のパッケージ構造に関する。Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a high-output hybrid integrated circuit device in which a high-output circuit board and a control circuit board for controlling the same are integrated via a case material. More specifically, the present invention relates to a package structure of a high-output hybrid integrated circuit device.
(ロ)従来の技術
一般的にインバータエアコンの室外器などの電力駆動制
御用として電力半導体装置が使用きれるが、従来のこの
種の電力半導体装置では、電力用半導体素子が接si!
された電力回路基板と各種の電気部品が接続された制御
回路基板とが夫々別個に独立して制御パネル等に配置さ
れていた。このため、装置の小形化や簡単に交換可能な
モジュール形態とすることが困難であった。(b) Conventional technology In general, power semiconductor devices can be used for power drive control of outdoor units of inverter air conditioners, etc., but in conventional power semiconductor devices of this type, power semiconductor elements are not connected to each other!
A power circuit board and a control circuit board to which various electrical components are connected are separately and independently arranged on a control panel or the like. For this reason, it has been difficult to downsize the device and to form it into an easily replaceable module.
そこで近年では上述した問題を解決するために電力回路
基板と制御回路基板とを1つのパッケージに集積化した
電力半導体装置なるものが存在する。Therefore, in recent years, in order to solve the above-mentioned problems, there has been a power semiconductor device in which a power circuit board and a control circuit board are integrated into one package.
第7図は例えば1つの従来の電力半導体装置を示した断
面図である。FIG. 7 is a sectional view showing, for example, one conventional power semiconductor device.
第7図に示すように、電力回路基板(51)と制御回路
基板(52)とを備え、電力回路基板(51)がモール
ド用樹脂外枠(54)内にシリコンゲル等の内部注入樹
脂(56)により固定され、また、制御回路基板(52
)がモールド用樹脂外枠(54)に嵌合されると共にエ
ポキシ樹脂等の封止樹脂(58)の注入硬化により固定
されて、両回路基板(51)< 52)がモールド用樹
脂外枠〈54〉に互いに平行に積層保持されている。そ
して、電力回路基板(51)上に形成された配線パター
ンにトランジスタやダイオード等の電力用半導体素子(
110)が、制御回路基板(52)上に形成された配線
パターンに各種の電気部品(112)が夫々接続されて
いる。更に、電力回路基板(51〉には、外部入出力用
端子(114)が半田付けされ、この外部入出力用端子
(114)が封止樹脂(58)および制御回路基板(5
2)を貫通して上部に導出されている。また、制御回路
基板〈52)には外部接続用コネクタ(116)が接続
され、この外部接続用コネクタ(116)が封止樹脂(
58)で固定されて上部に突出されている。そして、電
力回路基板(51〉と制御回路基板(52)とは、基板
接続用コネクタ(118)により互いに電気的に接続さ
れている。As shown in FIG. 7, it is equipped with a power circuit board (51) and a control circuit board (52). 56), and the control circuit board (52
) is fitted into the molding resin outer frame (54) and fixed by injection hardening of a sealing resin (58) such as epoxy resin, so that both circuit boards (51)<52) are fitted into the molding resin outer frame<54> are stacked and held parallel to each other. Then, power semiconductor elements (such as transistors and diodes) are connected to the wiring pattern formed on the power circuit board (51).
110), various electrical components (112) are respectively connected to wiring patterns formed on the control circuit board (52). Further, external input/output terminals (114) are soldered to the power circuit board (51>), and these external input/output terminals (114) are connected to the sealing resin (58) and the control circuit board (5).
2) and is led out to the top. Further, an external connection connector (116) is connected to the control circuit board (52), and this external connection connector (116) is connected to the sealing resin (
58) and protrudes from the top. The power circuit board (51>) and the control circuit board (52) are electrically connected to each other by a board connection connector (118).
(ハ)発明が解決しようとする課題
上述の如く説明した従来の電力半導体装置では以下に示
す種々の不具合がある。(c) Problems to be Solved by the Invention The conventional power semiconductor device described above has various problems as shown below.
先ず、この様な電力半導体装置は、小形化や交換可能な
モジュール形態を実現できたものの、電力回路基板(5
1)と制御回路基板(52)との間が内部注入樹脂(5
6)と封止樹脂(58)とによって充填きれているので
、電力回路基板(51)上に配置された電力用半導体素
子(110)から発生する熱が内部注入樹脂(56)お
よび封止樹脂(58)を介して制御回路基板(52)上
に配置された各種の電気部品(112)に伝わり、この
ため、各種電気部品(112)が熱の影響を受けて特性
が変化するなどして誤動作の原因となり、電力回路基板
(51)上に形成されるパワー回路の大きな制約原因と
なっていた。そのため、50A〜200Aクラスのハイ
パワー回路対応の装置が実現できないという大きな問題
がある。First of all, although such power semiconductor devices have been able to achieve miniaturization and replaceable module form, the power circuit board (5
1) and the control circuit board (52) is an internally injected resin (5).
6) and the sealing resin (58), the heat generated from the power semiconductor element (110) placed on the power circuit board (51) is transferred to the internal injection resin (56) and the sealing resin. (58) to the various electrical components (112) arranged on the control circuit board (52), and as a result, the various electrical components (112) are affected by heat and their characteristics change. This causes malfunction and is a major constraint on the power circuit formed on the power circuit board (51). Therefore, there is a big problem that a device compatible with high power circuits of 50A to 200A class cannot be realized.
次に、制御回路基板(52)は樹脂系の基板で形成され
且つ、基板(52)上に搭載された電気部品(112)
が上面側に配置された構造となるために、耐ノイズ性が
著しく悪いため、ノイズによる誤動作が発生する。Next, the control circuit board (52) is formed of a resin-based board, and includes electrical components (112) mounted on the board (52).
Since the structure is such that the noise is disposed on the top surface side, the noise resistance is extremely poor, resulting in malfunctions due to noise.
更に、電力回路基板(51)と制御回路基板(52)と
の接続は、先に外枠(54)に電力回路基板(51)を
固着しあらかじめ、基板(51)上に固着諮れた接続コ
ネクタ(11g)なるものを基板(52)の表面上に突
出部せて、その突出部を半田付けしなければならず作業
性および信頼性が著しく低下すると共に自動化が行えな
い問題がある。Furthermore, the connection between the power circuit board (51) and the control circuit board (52) is made by first fixing the power circuit board (51) to the outer frame (54) and making the connections on the board (51) in advance. The connector (11g) must be protruded from the surface of the board (52) and the protrusion must be soldered, which significantly reduces workability and reliability and also precludes automation.
更に入出力用端子(114)およびコネクタ(116)
の全ての端子が本体より上面方向に突出されているため
、完成時の積重ねが行えず梱包作業の能率が低下する問
題がある。Furthermore, input/output terminals (114) and connectors (116)
Since all of the terminals protrude upward from the main body, there is a problem in that stacking cannot be performed when completed, which reduces the efficiency of packaging work.
(ニ)課題を解決するための手段
本発明は上述した課題を鑑みて為されたものであり、少
なくとも一方の基板の表面が露出する様に対向配置され
た二枚の金属基板と前記両基板上に形成された所望形状
の導電路と前記一方の基板上の導電路と接続された複数
の制御系の回路素子と前記他方の基板上の導電路と接続
された複数のパワー系の回路素子と前記側基板を固着一
体化するケース材とを備え、前記一方の基板の少なくと
も一側辺周端部から小信号用リード端子を導出させ、前
記他方の基板の周端部に固着されたパワー用リード端子
の外部接続部を前記一方の基板の露出面と同一面に配置
したことを特徴とする。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and includes two metal substrates that are arranged facing each other so that the surface of at least one of the substrates is exposed, and both of the substrates. a plurality of control system circuit elements connected to the conductive path on the one substrate, and a plurality of power system circuit elements connected to the conductive path on the other substrate. and a case material for fixing and integrating the side substrates, a small signal lead terminal is led out from the peripheral edge of at least one side of the one substrate, and a power source is fixed to the peripheral edge of the other substrate. The external connection portion of the lead terminal for use is arranged on the same surface as the exposed surface of the one substrate.
り*)作用
この様に本発明に依れば、二枚の金属基板の一方の基板
表面を露出する様にケース材を介して対向配置させ、一
方の基板から小信号用のリード端子をその基板表面から
突出することなく導出させ、他方の基板上に固着された
パワー用リード端子をケース材に沿って延在ネせその接
続部を一方の基板の露出面と路間−面になる様に配置す
ることにより、両基板に固着されたリード端子が突出し
ない高出力用混成集積回路装置を提供できる。*) Function As described above, according to the present invention, two metal substrates are arranged facing each other with a case material in between so that the surface of one of the substrates is exposed, and a small signal lead terminal is connected from one of the substrates. The power lead terminal fixed on the other board is led out without protruding from the surface of the board, and is extended along the case material so that the connection part is between the exposed surface of one board and the surface. By arranging the lead terminals on both substrates, it is possible to provide a high-output hybrid integrated circuit device in which the lead terminals fixed to both substrates do not protrude.
また、本発明の高出力用混成集積回路装置ではその表面
が露出して配置される一方の基板上に制御系のトランジ
スタ、IC,チップコンデンサ、チップ抵抗等の回路素
子がチップ状のものが使用されているので高集積化され
た制御基板を提供することができる。Furthermore, in the high-output hybrid integrated circuit device of the present invention, circuit elements such as control system transistors, ICs, chip capacitors, and chip resistors are used in the form of chips on one of the substrates, the surface of which is exposed. This makes it possible to provide a highly integrated control board.
更に両基板は夫々の基板周端部分で接続されるので両基
板の接続が極めて容易に行えるメリットを有する。Furthermore, since the two substrates are connected at the peripheral edge portions of each substrate, there is an advantage that the connection between the two substrates can be performed extremely easily.
更に両基板はその裏面が露出きれ且つ夫々の回路素子が
対向する様に配置されているため外来ノイズに対して著
しく遮蔽効果が向上する。Furthermore, since both substrates are arranged so that their back surfaces are fully exposed and their respective circuit elements face each other, the shielding effect against external noise is significantly improved.
(へ)実施例
以下に第1図乃至第3図に示した実施例に基づいて本発
明の高出力用混成集積回路装置を詳述に説明する。(F) Embodiment The high-output hybrid integrated circuit device of the present invention will be explained in detail below based on the embodiment shown in FIGS. 1 to 3.
第1図は本発明の高出力用混成集積回路装置を示す断面
図、第2図は平面図、第3図は正面図である。FIG. 1 is a sectional view showing a high-output hybrid integrated circuit device of the present invention, FIG. 2 is a plan view, and FIG. 3 is a front view.
本発明の高出力用混成集積回路装置は第1図乃至第3図
に示す如く、二枚の金属基板(la)(lb)と、両基
板(la)(lb)上に搭載された複数の制御系および
パワー系の回路素子(2a)(2b)と、両基板(1a
)(lb)の周端辺に固着された小信号用およびパワー
用のリード端子(3a)(3b)と、二枚の基板(1a
)(1b)を離間させて固着一体化するケース材(4〉
とから構成される。As shown in FIGS. 1 to 3, the high-output hybrid integrated circuit device of the present invention includes two metal substrates (LA) (LB) and a plurality of Control system and power system circuit elements (2a) (2b), both boards (1a
) (lb), small signal and power lead terminals (3a) (3b) fixed to the peripheral edge of the board (lb), and two boards (1a
) (1b) separated and fixedly integrated (4)
It consists of
金属基板としては例えば0.5〜5 、0 mm厚のア
ルミニウム基板を用いる。その両基板(ia)(lb)
の表面には、周知の陽極酸化により酸化アルミニウム膜
(アルマイト層)が形成され、その−主面側に10〜7
0μ厚のエポキシあるいはポリイミド等の絶縁樹脂層が
貼着される。更に絶縁樹脂層上には10〜105μ厚の
銅箔が絶縁樹脂層と同時にローラーあるいはホットプレ
ス等の手段により貼着されている。As the metal substrate, for example, an aluminum substrate with a thickness of 0.5 to 5.0 mm is used. Both boards (ia) (lb)
An aluminum oxide film (alumite layer) is formed on the surface by well-known anodic oxidation, and a 10 to 7
An insulating resin layer such as epoxy or polyimide with a thickness of 0 μm is pasted. Further, a copper foil having a thickness of 10 to 105 .mu.m is adhered onto the insulating resin layer simultaneously with the insulating resin layer by means such as a roller or hot press.
両基板(la)(lb)の−主面上に設けられた銅箔表
面上にはスクリーン印刷によって所望形状の導電路を露
出してレジストでマスクされ、貴金属(金、銀、白金)
メツキ層が銅箔表面にメツキされる。然る後、レジスト
を除去して貴金属メツキ層をマスクとして銅箔のエツチ
ングを行い所望の導電路が形成される。ここでスクリー
ン印刷による導電路の細さは0 、5 mmが限界であ
るため、極細配線パターンを必要とするときは周知の写
真蝕刻技術に依り約2μルールまでの極細導電路の形成
が可能となる。On the surface of the copper foil provided on the main surfaces of both substrates (la) and (lb), a conductive path of a desired shape is exposed by screen printing and masked with a resist, and precious metals (gold, silver, platinum) are coated.
A plating layer is plated on the surface of the copper foil. Thereafter, the resist is removed and the copper foil is etched using the noble metal plating layer as a mask to form a desired conductive path. Here, the limit for the thinness of the conductive path by screen printing is 0.5 mm, so when an ultra-fine wiring pattern is required, it is possible to form an ultra-fine conductive path of up to about 2μ rule using well-known photo-etching technology. Become.
第4図は上述した技術を用いて形成された二枚の基板(
la)(lb)の一方の基板〈1a)、即ち、制御回路
基板の平面図であり、第4図から明らかな如く、一方の
基板(1a)上には制御用、即ち、信号線用の導電路(
5a)が略基板(1a)の全面に形成されている。その
導電路(5a)が延在される基板(1a)の周端部には
複数のリード固着用パッド(6a)が設けられている。Figure 4 shows two substrates (
la) This is a plan view of one board (1a) of (lb), that is, the control circuit board.As is clear from FIG. Conductive path (
5a) is formed substantially over the entire surface of the substrate (1a). A plurality of lead fixing pads (6a) are provided at the peripheral end of the substrate (1a) along which the conductive path (5a) extends.
基板(1a)の対向する周端部に設けられたパッド(6
a)には外部回路と接続を行う小信号用のリード端子(
3a)が固着されている。このリード端子(3a)は各
図からでは明らかにされてないがその先端部は水平方向
より上向きとなる様に配置され、更にそのリード端子(
3a)の先端部は一方の基板(1a〉の基板露出面(反
対面)より突出しない様に考慮されている。また、一方
の基板(1a)のもう−側辺に設けられた固着パッド(
6a’)は後述する他方の基板(1b)と接続するため
の固着用パッドである。Pads (6) provided on opposing peripheral edges of the substrate (1a)
a) has a small signal lead terminal (
3a) is fixed. This lead terminal (3a) is not clearly shown in each figure, but its tip is arranged so that it faces upwards from the horizontal direction, and the lead terminal (3a)
The tip of 3a) is designed so that it does not protrude beyond the exposed surface (opposite surface) of one substrate (1a).In addition, the fixing pad (1a) provided on the other side of one substrate (1a)
6a') is a fixing pad for connecting to the other substrate (1b) which will be described later.
上述した制御系の基板(1a)上に発熱を有さないトラ
ンジスタ、ICおよびチップコンデンサ、チップ抵抗等
のチップ状の回路素子(2a)が所定位置にダイ状で搭
載されている。Chip-shaped circuit elements (2a) such as transistors, ICs, chip capacitors, and chip resistors that do not generate heat are mounted in the form of a die at predetermined positions on the control system board (1a) described above.
一方、第5図は他方の基板〈1b)、即ち、パワー出力
用基板の平面図であり、第5図の如く、基板(1b)上
にはパワー用の太い導電路(5b)が主に形成きれてい
る。その導電路(5b)から延在された基板(1b)の
−周端辺にはパワー用リード端子固着用の複数のパッド
(6b)が設けられ、そのパッド〈6b〉にパワー用リ
ード端子〈3b〉が固着されている。また、他方の基板
(1b)上にはパワー用の導電路〈5b)のみならず一
部の信号系の導電路が形成されており、その導電路の先
端部分はパワー用リード端子〈3b〉が固着された反対
側に延在形成され、上述した一方の基板(1a)の接続
パッド(6a’)と接続されるパッド(6b’)となる
。On the other hand, Fig. 5 is a plan view of the other board (1b), that is, the power output board, and as shown in Fig. 5, there are mainly thick conductive paths (5b) for power on the board (1b). Completely formed. A plurality of pads (6b) for fixing power lead terminals are provided on the peripheral edge of the substrate (1b) extending from the conductive path (5b), and the power lead terminals are attached to the pads (6b). 3b> is fixed. In addition, on the other substrate (1b), not only a power conductive path (5b) but also some signal system conductive paths are formed, and the tip of the conductive path is connected to a power lead terminal (3b). A pad (6b') is formed to extend on the opposite side to which is fixed, and is connected to the connection pad (6a') of the one substrate (1a) described above.
この他方の基板〈1b〉上にはパワートランジスタ、パ
ワーMO8,IGBT等のパワー素子および、大電流検
出用抵抗を含むパワー系の保護回路を構成すべき複数の
回路素子(2b)が搭載されている。説明するまでもな
いがパワー素子で必要とされるものはCu、インバー等
のいわゆるヒートシンク材(7)を介して基板(1b)
上に搭載される。On this other board <1b> are mounted power elements such as a power transistor, power MO8, IGBT, and a plurality of circuit elements (2b) that constitute a power system protection circuit including a large current detection resistor. There is. Needless to explain, what is required for a power element is a substrate (1b) via a so-called heat sink material (7) such as Cu or Invar.
mounted on top.
尚、本実施例での他方の基板(1b)の銅箔の厚みは1
05μのため、100A〜200Aクラスの大軍流を最
小限の発熱で流すことが可能となっている。In addition, the thickness of the copper foil of the other board (1b) in this example is 1
05μ, it is possible to flow a large current of 100A to 200A class with minimal heat generation.
他方の基板(1b)上に固着されたパワー用のリード端
子〈3b)は第1図および第2図に示す如く、固着パッ
ド(6b)に固着され、いったん水平方向に導出されて
所定のところで折曲げ形成されている。The power lead terminal (3b) fixed on the other board (1b) is fixed to the fixing pad (6b) as shown in Figs. It is formed by bending.
この折曲げされた部分は後述するケース材(4)の表面
に沿う様に折曲げされるが、本実施例では略直角になる
様に折曲げ形成されている。更に詳しく述べると本実施
例のパワー用リード端子(3b)はその接続部が一方の
基板(1a)の露出面と同一面となる様に折曲げ配置さ
れている。即ち、夫々のリード端子(3a)(3b)は
両方とも上面側に突出することなく配置されることにな
る。This bent portion is bent along the surface of a case material (4), which will be described later, but in this embodiment, it is bent at a substantially right angle. More specifically, the power lead terminal (3b) of this embodiment is bent so that its connecting portion is flush with the exposed surface of one of the substrates (1a). That is, both lead terminals (3a) and (3b) are arranged without protruding to the upper surface side.
ところで、二枚の基板(la)(lb)のパワー系の他
方の基板(1b)の太ききは制御系の一方の基板(1a
)より大きくなる様に設計時に考慮されている。それら
の二枚の基板(la)(lb)は夫々の回路素子(2a
)(2b〉が対向する様にケース材(4)によって所定
間隔離間して固着一体化される。By the way, of the two boards (la) and (lb), the other board (1b) for the power system is thicker than the one board (1a) for the control system.
) This was taken into consideration during the design so that it would be larger. Those two boards (la) (lb) are connected to the respective circuit elements (2a
) (2b) are fixedly integrated with each other with a predetermined distance between them by the case material (4) so that they face each other.
本実施例で用いられるケース材(4)を第6図A乃至第
6図Cを用いて説明する。The case material (4) used in this example will be explained using FIGS. 6A to 6C.
第6図Aはケース材(4)の正面図、同図Bは平面図、
同図Cは底面図である。Figure 6A is a front view of the case material (4), Figure B is a plan view,
Figure C is a bottom view.
第6図A乃至同図Cに示す如く、ケース材(4)は両基
板(la)(lb)を離間させるために枠状に形成され
た枠部(10)と、枠部(10)の両端部から導出され
た翼状の係止部(11)と、パワー用リード端子(3b
)が実質的に当接され外部回路と接続する外部接続部材
(12)を主要部分として構成されている。As shown in FIG. 6A to FIG. A wing-shaped locking part (11) led out from both ends and a power lead terminal (3b
) is comprised as a main part of an external connection member (12) which is substantially abutted and connected to an external circuit.
更に本実施例のケース材(4)では上述した主要構成部
以外に両基板(la)(lb)を接続するための領域を
形成する突出部(13)と射出成形後にケース材(4)
のひずみ(反り)を防止するための補強部(19)とが
ケース材(4)と一体形成されている。Furthermore, in the case material (4) of this embodiment, in addition to the above-mentioned main components, there is a protrusion (13) that forms a region for connecting both substrates (la) and (lb), and a case material (4) after injection molding.
A reinforcing portion (19) for preventing distortion (warping) of the case material (4) is integrally formed with the case material (4).
ケース材(4)の特徴とするところは、外部接続部材(
12)にある。即ち、外部接続部材(12)はパワー用
リード端子(3b〉の接続部分が装置の側面と上面に設
定される様にケース材(4)の垂直面と水平面に夫々設
けられ、この外部接続部材(12)にはネジ止め用のナ
ツトを挿入する孔<19’)が設けられている。The characteristic of the case material (4) is that the external connection member (
12). That is, the external connection member (12) is provided on the vertical and horizontal surfaces of the case material (4) so that the connection portion of the power lead terminal (3b) is set on the side and top surfaces of the device, respectively. (12) is provided with a hole <19') into which a nut for screwing is inserted.
また、複数の外部接続部材〈12)は所定の深を有した
スリット(14’)によって各ブロック毎に仕切られて
いる。このスリット(14’)には絶縁体(図示しない
)が挿入され隣接して配置きれるパワー用リード端子間
の絶縁距離を一定に保持することに用いることができる
様に設計詐れている。Further, the plurality of external connection members (12) are partitioned into blocks by slits (14') having a predetermined depth. This slit (14') is designed so that an insulator (not shown) can be inserted into the slit (14') to maintain a constant insulation distance between adjacent power lead terminals.
斯るケース材(4)を用いて両基板(1a)(lb)は
ケース材(4)と一体化される。Both substrates (1a) and (lb) are integrated with the case material (4) using such a case material (4).
制御系回路基板となる一方の基板(1a)はケース材(
4)の上面側に、パワー系回路基板となる他方の基板(
1b)はケース材(4)の下面側に配置きれ、夫々の基
板(la)(lb)上に搭載諮れた回路素子(2a)(
2b)が対向する様に考慮されている。ところで、ケー
ス材(4)と夫々の基板(1g)(lb)との接着は接
着性シート(Jシート:商品名)となるもので熱加圧着
方法によって固着一体化される。One board (1a) that will become the control system circuit board is made of case material (
4) Place the other board (which will become the power circuit board) on the top side.
1b) is arranged on the bottom side of the case material (4), and the circuit elements (2a) (
2b) are considered to be opposite to each other. Incidentally, the case material (4) and the respective substrates (1g) (lb) are bonded together using an adhesive sheet (J sheet: trade name) by a hot press bonding method.
ケース材(4)に一体止された内基板(1g>(lb)
は、ケース材(4)の突出部(13〉と内基板(la)
(lb)の周端部で形成される空間内で互いに電気的に
接続される。その接続手段としては、フィルム、金属製
リード等のいくつかの方法があるが、本実施例では金属
製リード〈15)を用いて接続するものとする0両基板
(la)(lb)を接続した後、上述した空間部にはエ
ポキシ系の封止樹脂〈17)が充填され、夫々の接続領
域が保護される。また、内基板(1a)(1b)と突出
部(13)とで形成された空間部内に樹脂〈17)を充
填する必要のために内基板(la)(lb)の基板周端
辺は略一致する様に設計されている。Inner board (1g>(lb) integrally fixed to case material (4)
is the protrusion (13) of the case material (4) and the inner board (la)
(lb) are electrically connected to each other within the space formed by the peripheral end portion. There are several ways to connect them, such as film and metal leads, but in this example, metal leads (15) are used to connect both boards (la) and (lb). After that, the above-mentioned space is filled with an epoxy sealing resin (17) to protect each connection area. In addition, since it is necessary to fill the space formed by the inner substrates (1a) (1b) and the protrusion (13) with resin (17), the peripheral edges of the inner substrates (la) (lb) are approximately Designed to match.
ケース材(4)の上面に配置諮れた一方の基板(1a)
から導出された小信号用のリード端子(3a)は第2図
に示す如く、上面側に配置され且つ、そのリード端子(
3a)の先端部は第3図に示す如く基板(1a)の表面
より突出することはない。One board (1a) arranged on the top surface of the case material (4)
As shown in FIG. 2, the small signal lead terminal (3a) derived from the
As shown in FIG. 3, the tip of 3a) does not protrude from the surface of the substrate (1a).
一方、ケース材(4)の下面に配置された他方の基板(
1b)に固着されたパワー用リード端子(3b)は第1
図乃至第31150に示す如く、ケース材(4)の外部
接続部材(12)に沿って折曲げ配置されリード端子(
3b)の接続部は一方の基板(1a)の露出面と同一面
になる様に折曲げ形成される。ケース材(4)の外部接
続部材(12)の孔(13’)にはナツト(16)があ
らかじめ配置されているので、ナツト(16)は折曲げ
されたリード端子〈3b)によって封止された状態とな
る。説明するまでもないがリード端子(3b)には穴が
設けられており、その穴にネジ(18)を挿入してネジ
(18)とナツト(16)とをネジ止めし、パワー用リ
ード端子〈3b)と外部回路との接続を行う。On the other hand, the other board (
The power lead terminal (3b) fixed to the first
As shown in Figure 31150, the lead terminal (
The connecting portion 3b) is bent so as to be flush with the exposed surface of one substrate (1a). Since the nut (16) is placed in advance in the hole (13') of the external connection member (12) of the case material (4), the nut (16) is sealed by the bent lead terminal (3b). The state will be as follows. Needless to explain, the lead terminal (3b) has a hole, insert the screw (18) into the hole, and screw the screw (18) and nut (16) together to connect the power lead terminal. Connect <3b) with the external circuit.
本実施例では、他方の基板(1b)の表面に第3の基板
となるマザー基板(20)が固着一体止される。In this embodiment, a mother board (20) serving as a third board is fixedly and integrally fixed to the surface of the other board (1b).
マザー基板(20)は放熱性および絶縁性を向上させる
ことを目的とするために、金属基板が用いられ、且つそ
の主面にはポリイミド樹脂等の絶縁性樹脂層(図示され
ない)が設けられている。このマザー基板<20〉は第
1図から明らかな様に他方の基板(1b)より大きく形
成され、二枚の基板(la)(1b〉と同様にケース材
(4)内に収納される。For the purpose of improving heat dissipation and insulation, the motherboard (20) is a metal substrate, and its main surface is provided with an insulating resin layer (not shown) such as polyimide resin. There is. As is clear from FIG. 1, this mother board <20> is formed larger than the other board (1b), and is housed in the case material (4) like the two boards (la) and (1b>).
即ち、マザー基板〈20)は第6図C(ケース材の底面
を示す図)に示す様に一点鎖線で示した領域に配置され
る。このとき、マザー基板(20)はケース材(4)の
両端部に設けられた翼状の係止部(11)によって位置
規制が行われるために他方の基板(lb)とマザー基板
(20)とを固着する際に位置ズレ等の問題が発生する
恐れはない。That is, the mother board (20) is arranged in the area indicated by the dashed line as shown in FIG. 6C (a diagram showing the bottom surface of the case material). At this time, the position of the mother board (20) is regulated by the wing-shaped locking parts (11) provided at both ends of the case material (4), so that the other board (lb) and the mother board (20) There is no risk of problems such as misalignment when fixing.
マザー基板(20)と他方の基板(1b)とを固着しケ
ース材(4)と一体止すると、第1図および第3図に示
す様にマザー基板(20)とケース材(4)の接続部材
(12)とで形成された空間部にはエポキシ系の封止樹
脂(17)が充填され、パワー用リード端子(3b)の
囲者接続部分が封止保護される。When the mother board (20) and the other board (1b) are fixed and integrally connected to the case material (4), the connection between the mother board (20) and the case material (4) is established as shown in Figures 1 and 3. The space formed by the member (12) is filled with an epoxy sealing resin (17), and the enclosure connection portion of the power lead terminal (3b) is sealed and protected.
斯る本発明に依れば、二枚の金属基板の一方の基板表面
を露出する様にケース材を介して対向配置させ、一方の
基板から小信号用のリード端子をその基板表面から突出
することなく導出させ、他方の基板上に固着されたパワ
ー用リード端子をケース材に沿って延在させその接続部
を一方の基板の露出面と路間−面になる様に配置するこ
とにより、内基板に固着されたリード端子が突出しない
高出力用混成集積回路装置を提供できる。その結果、薄
型でしかも取扱い性の優れた高出力用混成集積回路装置
を実現することができる。According to the present invention, two metal substrates are arranged facing each other with a case material in between so that the surface of one of the substrates is exposed, and a lead terminal for a small signal is protruded from the surface of one of the substrates. By extending the power lead terminal fixed on the other board along the case material and arranging the connection part so that it is on the surface between the exposed surface of one board and the path, It is possible to provide a high-output hybrid integrated circuit device in which the lead terminals fixed to the inner substrate do not protrude. As a result, a high-output hybrid integrated circuit device that is thin and easy to handle can be realized.
(ト)発明の効果
以上に詳述した如く、本発明に依れば、内基板(la)
(lb)に固着された夫々のリード端子(3a)(3b
)の外部接続部は一方の基板(1a)側、即ち、上面側
にしかも突出することなく配置されるので薄型の取扱い
性の優れた装置を提供することができる。(G) Effects of the Invention As detailed above, according to the present invention, the inner substrate (la)
The respective lead terminals (3a) (3b) fixed to (lb)
) is arranged on one substrate (1a) side, that is, on the top surface side without protruding, so that a thin device with excellent handling properties can be provided.
更に本発明に依れば一方の基板(1a)の基板表面が露
出する様に配flれているのでパワー用の他方の基板(
1b)からの熱の影響を受けることは従来構造のものと
比較すると著しく低減する。その結果、他方の基板(1
b)上に大出力用の回路を形成したとしても熱によって
制御系の一方の基板(1a)上に設けられた回路素子(
2a)の信頼性を向上することができる。Furthermore, according to the present invention, since the surface of one substrate (1a) is exposed, the other substrate (1a) for power
1b) is significantly reduced compared to the conventional structure. As a result, the other board (1
b) Even if a high output circuit is formed on the circuit board (1a) of the control system, heat may damage the circuit elements (
The reliability of 2a) can be improved.
更に本発明に依れば、内基板(la)(lb)上にチッ
プ状の回路素子(2a ) (2b )が搭載きれてい
るので高集積化した高出力用の混成集積回路装置を提供
することができる。Further, according to the present invention, since the chip-shaped circuit elements (2a) (2b) are fully mounted on the inner substrates (la) (lb), it is possible to provide a highly integrated, high-output hybrid integrated circuit device. be able to.
第1図は本発明を示す断面図、第2図は第1図の平面図
、第3図は第1図の正面図、第4図、第5図は基板を示
す平面図、第6図A乃至Cは本実施例で用いられるケー
ス材を示す図、および第7図は従来例を示す断面図であ
る。
(1g>(lb)は基板、(2a)(2b)は回路素子
、(3a)(3b)はリード端子、(4)はケース材、
(5a)(5b)は導電路、(6a)(6b)はリード
端子固着用パッド、(7)はヒートシンク、(10)は
枠部、(11)は係止部、(12)は外部接続部材、(
13)は突出部、<14)は補強部、(15)は金属製
リード、(16)はナツト、(17)は封止樹脂、(1
8)はネジ、(20)はマザー基板である。FIG. 1 is a sectional view showing the present invention, FIG. 2 is a plan view of FIG. 1, FIG. 3 is a front view of FIG. 1, FIGS. 4 and 5 are plan views showing the substrate, and FIG. A to C are views showing the case material used in this embodiment, and FIG. 7 is a sectional view showing a conventional example. (1g>(lb) is the board, (2a) (2b) are the circuit elements, (3a) (3b) are the lead terminals, (4) is the case material,
(5a) (5b) are conductive paths, (6a) (6b) are pads for fixing lead terminals, (7) are heat sinks, (10) are frame parts, (11) are locking parts, (12) are external connections Element,(
13) is a protruding part, <14) is a reinforcing part, (15) is a metal lead, (16) is a nut, (17) is a sealing resin, (1
8) is a screw, and (20) is a motherboard.
Claims (5)
配置された二枚の金属基板と 前記両基板上に形成された所望形状の導電路と前記一方
の基板上の導電路と接続された複数の制御系の回路素子
と 前記他方の基板上の導電路と接続された複数のパワー系
の回路素子と 前記両基板を固着一体化するケース材とを備え、 前記一方の基板の少なくとも一側辺周端部から小信号用
リード端子を導出させ、前記他方の基板の周端部に固着
されたパワー用リード端子の外部接続部を前記一方の基
板の露出面と同一面に配置したことを特徴とする高出力
用混成集積回路装置。(1) Two metal substrates placed opposite each other so that the surface of at least one of the substrates is exposed, a conductive path formed on both substrates having a desired shape, and a conductive path on the one substrate connected to the conductive path. At least one side of the one substrate, comprising a plurality of control system circuit elements, a plurality of power system circuit elements connected to conductive paths on the other substrate, and a case material that fixes and integrates both the substrates. The small signal lead terminal is led out from the peripheral edge, and the external connection part of the power lead terminal fixed to the peripheral edge of the other board is arranged on the same surface as the exposed surface of the one board. A hybrid integrated circuit device for high output.
項1記載の高出力用混成集積回路装置。(2) The high output hybrid integrated circuit device according to claim 1, wherein the conductive path is made of copper foil.
、夫々の基板は互いに電気的に接続されていることを特
徴とする請求項1記載の高出力用混成集積回路装置。(3) The high-output hybrid integrated circuit device according to claim 1, wherein the other substrate is larger than the one substrate, and the respective substrates are electrically connected to each other.
辺は実質的に一致されていることを特徴とする請求項3
記載の高出力用混成集積回路装置。(4) Claim 3, wherein the peripheral edges of the respective substrates to which the two substrates are electrically connected are substantially aligned.
The high output hybrid integrated circuit device described above.
いることを特徴とする請求項1記載の高出力用混成集積
回路装置。(5) The high output hybrid integrated circuit device according to claim 1, wherein the power lead terminal is bent upward.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2138747A JPH0766955B2 (en) | 1990-05-28 | 1990-05-28 | High power hybrid integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2138747A JPH0766955B2 (en) | 1990-05-28 | 1990-05-28 | High power hybrid integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0430564A true JPH0430564A (en) | 1992-02-03 |
JPH0766955B2 JPH0766955B2 (en) | 1995-07-19 |
Family
ID=15229234
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2138747A Expired - Fee Related JPH0766955B2 (en) | 1990-05-28 | 1990-05-28 | High power hybrid integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0766955B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014175545A (en) * | 2013-03-11 | 2014-09-22 | Nippon Inter Electronics Corp | Power semiconductor module |
-
1990
- 1990-05-28 JP JP2138747A patent/JPH0766955B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014175545A (en) * | 2013-03-11 | 2014-09-22 | Nippon Inter Electronics Corp | Power semiconductor module |
Also Published As
Publication number | Publication date |
---|---|
JPH0766955B2 (en) | 1995-07-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6396136B2 (en) | Ball grid package with multiple power/ground planes | |
US4941033A (en) | Semiconductor integrated circuit device | |
JP2509969B2 (en) | Electronic equipment | |
US5869889A (en) | Thin power tape ball grid array package | |
KR970003991B1 (en) | Double sided memory board and memory module using the board | |
JPH07153903A (en) | Semiconductor device package | |
JPH09283695A (en) | Semiconductor mounting structure | |
JP3251323B2 (en) | Electronic circuit device | |
JP3016910B2 (en) | Semiconductor module structure | |
JP3695458B2 (en) | Semiconductor device, circuit board and electronic equipment | |
US5422515A (en) | Semiconductor module including wiring structures each having different current capacity | |
JPH0430566A (en) | High output power hybrid integrated circuit device | |
JP2524482B2 (en) | QFP structure semiconductor device | |
JPH09199665A (en) | Mounting device | |
JPH0430564A (en) | High power hybrid integrated circuit device | |
JPH0430565A (en) | High power output hybrid integrated circuit device | |
JP3232723B2 (en) | Electronic circuit device and method of manufacturing the same | |
JP2001344587A (en) | Printed wiring board and module for ic card using the same and method for manufacturing the same | |
JPH0430459A (en) | High output power hybrid integrated circuit device | |
JPH0430458A (en) | High output power hybrid integrated circuit device | |
JP3737093B2 (en) | Semiconductor device | |
JP2771575B2 (en) | Hybrid integrated circuit | |
JPH0739244Y2 (en) | Hybrid integrated circuit device | |
JPH0613535A (en) | Electronic part mounting apparatus | |
JPH11102991A (en) | Semiconductor element mounting frame |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080719 Year of fee payment: 13 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080719 Year of fee payment: 13 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090719 Year of fee payment: 14 |
|
LAPS | Cancellation because of no payment of annual fees |