JPH0430461A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH0430461A
JPH0430461A JP13595290A JP13595290A JPH0430461A JP H0430461 A JPH0430461 A JP H0430461A JP 13595290 A JP13595290 A JP 13595290A JP 13595290 A JP13595290 A JP 13595290A JP H0430461 A JPH0430461 A JP H0430461A
Authority
JP
Japan
Prior art keywords
bonding pad
damping resistor
resistor
semiconductor integrated
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13595290A
Other languages
Japanese (ja)
Inventor
Minoru Matsushima
松島 実
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP13595290A priority Critical patent/JPH0430461A/en
Publication of JPH0430461A publication Critical patent/JPH0430461A/en
Pending legal-status Critical Current

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Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To improve a semiconductor integrated circuit in degree of integration without enlarging a printed board in area and to prevent a ringing waveform from occurring by a method wherein a damping resistor is provided just under a bonding pad. CONSTITUTION:A damping resistor 2 such as a diffusion resistor or a polysilicon wiring formed of material possessed of a resistive component realized in a semiconductor manufacturing process is provided under a bonding pad 1 formed of an aluminum film. A contact window 3 used for connecting the electrode of the bonding pad 1 to the the damping resistor 2 is provided protruding outside of the edge of the bonding pad 1 so as to protect the edge of the damping resistor 2 against damage caused by the impact of wire bonding or to protect an interlaminar film against damage caused by impact induced by the nonuniform step of the interlaminar film between the damping resistor and the bonding pad 1.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は例えば、C0M5.TTL等の論理出力回路に
おいて、出力波形に生じるリンギングを有効に防止する
ダンピング抵抗を用いた半導体集積回路に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to, for example, C0M5. The present invention relates to a semiconductor integrated circuit using a damping resistor that effectively prevents ringing that occurs in an output waveform in a TTL or other logic output circuit.

従来の技術 電子機器の高速化に伴って半導体集積回路の動作周波数
も高くなってきており、出力段の出力波形においても1
〜2nsにも達する高速な立上がり、立下がり波形が要
求されてきている。その結果、従来は問題とならなかっ
た、または微少であった高レベル(High)から低レ
ベル(Low)または低レベル(Low)から高レベル
(High)への論理出力波形のオーバーシュート、ア
ンダーシュート、つまりリンギングが問題となってきた
。その問題とは、リンギング時に空間に向けて発射され
る不要副射や、リンギング波形が次段に伝達された時に
生じる次段の論理回路への誤動作である。
Conventional technology As the speed of electronic devices increases, the operating frequency of semiconductor integrated circuits also increases, and the output waveform of the output stage also increases.
High-speed rising and falling waveforms reaching up to 2 ns are now required. As a result, overshoot and undershoot of the logic output waveform from high level (High) to low level (Low) or from low level (Low) to high level (High), which previously did not pose a problem or was very slight. In other words, ringing has become a problem. The problems are unnecessary side radiation emitted into space during ringing, and malfunctions in the next stage logic circuit that occur when the ringing waveform is transmitted to the next stage.

第4図に、ダンピング抵抗がない時にリンギングが生じ
た出力波形を示す。オーバーシュートが次段の入力スレ
ッショルドを起えると誤動作が生じ、更に急峻なオーバ
ーシュート、アンダーシュート波形が、妨害ノイズの原
因となる不要副射を発生させることになる。
FIG. 4 shows an output waveform in which ringing occurs when there is no damping resistor. If the overshoot causes the input threshold of the next stage, a malfunction will occur, and furthermore, the steep overshoot and undershoot waveforms will generate unnecessary side radiation that causes interference noise.

従来の技術では、このリンギングを防ぐダンピング抵抗
を半導体集積回路の外側のプリント基板上へ設置してい
た。
In conventional technology, a damping resistor to prevent this ringing is installed on a printed circuit board outside the semiconductor integrated circuit.

発明が解決しようとする課題 従来の技術では、外部に追加の抵抗を必要とし、余分な
コストを必要とする。マイクロコンピュータの出力バス
などの例では、そのビット幅に応じて必要であり、最新
のコンピュータでは32本程度も必要となる。この抵抗
群は、それ自身のコストアップのみでなく、プリント基
板上にも余分な面積を必要とし、コストアップと機器の
小型化の妨げとなる。
Problems to be Solved by the Invention Conventional techniques require an additional external resistor, which requires extra cost. For example, in the case of an output bus of a microcomputer, the number of buses required depends on the bit width, and the latest computers require about 32 buses. This resistor group not only increases its own cost, but also requires extra area on the printed circuit board, which increases cost and hinders miniaturization of the device.

本発明はこのような課題を解決した半導体集積回路を提
供することを目的とするものである。
An object of the present invention is to provide a semiconductor integrated circuit that solves these problems.

課題を解決するための手段 本発明の半導体集積回路はリンギングを防ぐダンピング
抵抗を半導体集積回路内のボンディングパッド直下に設
け、特別にダンピング抵抗専用の形成領域を設けない構
造のものである。
Means for Solving the Problems The semiconductor integrated circuit of the present invention has a structure in which a damping resistor for preventing ringing is provided directly under a bonding pad within the semiconductor integrated circuit, and no special formation region exclusively for the damping resistor is provided.

作用 本発明の半導体集積回路によれば、ダンピング抵抗専用
の形成領域を設ける必要がな(出力波形のリンギングを
防止することができる。
Effect: According to the semiconductor integrated circuit of the present invention, there is no need to provide a formation region exclusively for the damping resistor (ringing of the output waveform can be prevented).

実施例 以下、発明の実施例を図面を参照して説明する。Example Embodiments of the invention will be described below with reference to the drawings.

第1図は本発明の半導体集積回路の構成を示す平面図で
ある。アルミニウム膜で形成されたボンディングパッド
1の直下に、絶縁膜を介して拡散抵抗またはポリシリコ
ン配線など、半導体製造工程にて実現できる抵抗成分を
有する物質にて構成されたダンピング抵抗2を形成する
。このダンピング抵抗2のエツジがワイヤーボンド時の
衝撃により破壊されることや、エツジ部に生じるダンピ
ング抵抗とボンディングパッド1間の眉間膜の不均一段
差に起因する上記衝撃による層間膜破壊を避けるように
、ボンディングパッド1の電極とダンピング抵抗2を接
続するためのコンタクト窓3がボンディングパッドエツ
ジより外側にはみ出すよう工夫している。チップ4の内
部の出力トランジスタの信号はアルミニウム電極配線層
5から入力され、ダンピング抵抗2とのコンタクト窓3
を通過し、ボンディングパッド1直下のタンピング抵抗
2を通過し、チップ4端側のダンピング抵抗2とボンデ
ィングパッド1間のコンタクト窓3を通過し、ボンディ
ングパッド1に達する。第2図に第1図の平面図に相当
する回路図を示す。抵抗7が第1図のダンピング抵抗2
に、出力ターミナル6がボンディングパッド1に相当す
る。ただし、出力トランジスタ7は、第1図上には、明
記されておらず、アルミニウム電極配線5の引出し延長
線上にあると考えることができる。
FIG. 1 is a plan view showing the configuration of a semiconductor integrated circuit according to the present invention. Directly below the bonding pad 1 formed of an aluminum film, a damping resistor 2 made of a material having a resistance component that can be realized in a semiconductor manufacturing process, such as a diffused resistor or a polysilicon wiring, is formed via an insulating film. In order to avoid the edges of the damping resistor 2 being destroyed by the impact during wire bonding, and the interlayer film being destroyed by the impact caused by the uneven step of the glabellar membrane between the damping resistance generated at the edge and the bonding pad 1. The contact window 3 for connecting the electrode of the bonding pad 1 and the damping resistor 2 is designed to protrude outside the bonding pad edge. The signal of the output transistor inside the chip 4 is input from the aluminum electrode wiring layer 5, and the contact window 3 with the damping resistor 2 is input.
, passes through the tamping resistor 2 directly below the bonding pad 1 , passes through the contact window 3 between the damping resistor 2 on the end side of the chip 4 and the bonding pad 1 , and reaches the bonding pad 1 . FIG. 2 shows a circuit diagram corresponding to the plan view of FIG. 1. Resistor 7 is damping resistor 2 in Figure 1.
In this case, the output terminal 6 corresponds to the bonding pad 1. However, the output transistor 7 is not clearly shown in FIG. 1, and can be considered to be on the extension line of the aluminum electrode wiring 5.

第3図にダンピング抵抗を挿入した時の出力波形を示す
。ダンピング抵抗により、リンギングが押さえられてい
る。
Figure 3 shows the output waveform when a damping resistor is inserted. Ringing is suppressed by damping resistance.

発明の詳細 な説明したように、本発明の半導体集積回路によれば、
ボンディングパッド直下にダンピング抵抗を形成するこ
とにより、集積度を高めるとともに、ICの外部へダン
ピング抵抗を付加した場合よりもプリント板面積の増大
もな(、それに伴う抵抗プリント板面積の増大によるコ
スト増もなく、リンギング波形を防止することができる
As described in detail, according to the semiconductor integrated circuit of the present invention,
By forming a damping resistor directly under the bonding pad, the degree of integration is increased, and the printed board area does not increase compared to the case where the damping resistor is added outside the IC (and the cost increases due to the corresponding increase in the resistor printed board area). Therefore, ringing waveforms can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体集積回路の一実施例を示す平面
図、第2図は本発明の一実施例にかかる出力部回路図、
第3図はダンピング抵抗を設けたときの出力波形図、第
4図は従来例の出力波形図である。 1・・・・・・ボンディングパッド、2・・・・・・ダ
ンピング抵抗、3・・・・・・コンタクト窓、4・・・
・・・チップ、5・・・・・・アルミニウム電極配線層
、6・・・・・・ボンディングパッドに相当する出力タ
ーミナル、7・・・・・・ダンピング抵抗、8・・・・
・・出力トランジスタ。 代理人の氏名 弁理士 粟野重孝 はが1名第 図 第 図 箆 あ
FIG. 1 is a plan view showing an embodiment of a semiconductor integrated circuit according to the present invention, FIG. 2 is a circuit diagram of an output section according to an embodiment of the present invention,
FIG. 3 is an output waveform diagram when a damping resistor is provided, and FIG. 4 is an output waveform diagram of a conventional example. 1... Bonding pad, 2... Damping resistor, 3... Contact window, 4...
... Chip, 5 ... Aluminum electrode wiring layer, 6 ... Output terminal corresponding to bonding pad, 7 ... Damping resistor, 8 ...
...Output transistor. Name of agent: Patent attorney Shigetaka Awano

Claims (1)

【特許請求の範囲】[Claims]  ボンディングパッド直下に絶縁膜を介して抵抗体が形
成され、前記ボンディングパッドと前記抵抗体を接続さ
せるコンタクト窓が、前記ボンディングパッドの端部も
しくは前記ボンディングパッドに隣接して形成されてい
ることを特徴とする半導体集積回路。
A resistor is formed directly under the bonding pad via an insulating film, and a contact window connecting the bonding pad and the resistor is formed at an end of the bonding pad or adjacent to the bonding pad. Semiconductor integrated circuit.
JP13595290A 1990-05-25 1990-05-25 Semiconductor integrated circuit Pending JPH0430461A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13595290A JPH0430461A (en) 1990-05-25 1990-05-25 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13595290A JPH0430461A (en) 1990-05-25 1990-05-25 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH0430461A true JPH0430461A (en) 1992-02-03

Family

ID=15163680

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13595290A Pending JPH0430461A (en) 1990-05-25 1990-05-25 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH0430461A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017092057A (en) * 2015-11-02 2017-05-25 コニカミノルタ株式会社 Semiconductor integrated circuit and image forming apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017092057A (en) * 2015-11-02 2017-05-25 コニカミノルタ株式会社 Semiconductor integrated circuit and image forming apparatus

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