JPH0220863Y2 - - Google Patents

Info

Publication number
JPH0220863Y2
JPH0220863Y2 JP16501083U JP16501083U JPH0220863Y2 JP H0220863 Y2 JPH0220863 Y2 JP H0220863Y2 JP 16501083 U JP16501083 U JP 16501083U JP 16501083 U JP16501083 U JP 16501083U JP H0220863 Y2 JPH0220863 Y2 JP H0220863Y2
Authority
JP
Japan
Prior art keywords
capacitor
dielectric film
transistor
wiring
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP16501083U
Other languages
Japanese (ja)
Other versions
JPS6073224U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16501083U priority Critical patent/JPS6073224U/en
Publication of JPS6073224U publication Critical patent/JPS6073224U/en
Application granted granted Critical
Publication of JPH0220863Y2 publication Critical patent/JPH0220863Y2/ja
Granted legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Description

【考案の詳細な説明】 考案の技術分野 本考案は、ハイブリツド集積回路基板に搭載さ
れる電磁波妨害対策用コンデンサに関する。
[Detailed Description of the Invention] Technical Field of the Invention The present invention relates to an electromagnetic interference countermeasure capacitor mounted on a hybrid integrated circuit board.

従来技術と問題点 トランジスタは雑音電圧が混入するとオンして
しまうことがある。即ち第1図は自動車搭機器の
ランプ駆動回路の一例を示し、Q1はランプをオ
ンオフするトランジスタ、R1,R2はそのベー
ス回路に挿入された抵抗、D1,D2はダイオー
ドであり、入力端子T1及び又はT2に正電圧が
加わるとトランジスタQ1はオンになつてそのコ
レクタに接続された図示しないランプをオンに
し、端子T1,T2の入力電圧がなくなるとQ1
はオフとなり、ランプは消灯するが、それ以外に
端子T1及び又はT2に電磁波性の雑音電圧が加
わるとダイオードD1及び又はD2によつて該雑
音電圧が整流され、この結果トランジスタQ1の
ベースが正電位にバイアスされ、ベース電流が流
れて該トランジスタQ1がオンすることがある。
Prior Art and Problems Transistors may turn on when noise voltage is mixed in with them. That is, FIG. 1 shows an example of a lamp drive circuit for automobile equipment, in which Q1 is a transistor that turns on and off the lamp, R1 and R2 are resistors inserted in the base circuit, D1 and D2 are diodes, and input terminals T1 and Alternatively, when a positive voltage is applied to T2, transistor Q1 turns on, turning on a lamp (not shown) connected to its collector, and when the input voltage at terminals T1 and T2 disappears, Q1
is turned off and the lamp is extinguished, but if an electromagnetic noise voltage is applied to terminals T1 and/or T2, the noise voltage is rectified by diode D1 and/or D2, and as a result, the base of transistor Q1 becomes positive. The transistor Q1 may be biased to a potential, a base current may flow, and the transistor Q1 may be turned on.

かゝる誤動作に対する対策(EMi対策という)
としては、コンデンサC1,C2をダイオードD
1,D2に並列に接続するのが有効である。即
ち、コンデンサC1,C2があると、ダイオード
D1,D2は交流的に短絡されたことになり、ト
ランジスタQ1のベースの直流電位は0、従つて
該Q1がオンすることはなくなる。
Countermeasures against such malfunctions (referred to as EMi countermeasures)
, the capacitors C1 and C2 are connected to the diode D
1 and D2 in parallel. That is, when the capacitors C1 and C2 are present, the diodes D1 and D2 are short-circuited in an alternating current manner, and the direct current potential of the base of the transistor Q1 is 0, so that Q1 is no longer turned on.

EMi対策用コンデンサはトランジスタのベー
ス、エミツタにも並設されることがある。第2図
はその例で、Q3は出力トランジスタ、Q2はそ
のドライバトランジスタ、R3〜R6は抵抗、C
3がトランジスタのベース、エミツタに並列に接
続されるEMi対策用コンデンサである。コンデン
サC3がないと、入力端子T3に入力する電磁波
性雑音電圧がトランジスタQ2のベース、エミツ
タ接合つまりダイオードで整流され、この結果Q
2はオン、従つてQ3もオンとなつてしまう。コ
ンデンサC3があると、トランジスタQ2のベー
ス、エミツタ接合は交流的に短絡され、整流作用
は実質上なくなる。
EMi countermeasure capacitors are sometimes installed in parallel to the base and emitter of the transistor. Figure 2 is an example of this, where Q3 is the output transistor, Q2 is its driver transistor, R3 to R6 are resistors, and C
3 is an EMi countermeasure capacitor connected in parallel to the base and emitter of the transistor. Without capacitor C3, the electromagnetic noise voltage input to input terminal T3 would be rectified by the base and emitter junction of transistor Q2, that is, by the diode, and as a result, Q
2 is on, so Q3 is also on. When the capacitor C3 is present, the base and emitter junctions of the transistor Q2 are short-circuited in an alternating current manner, and the rectification effect is substantially eliminated.

集積回路では多数のトランジスタ、ダイオード
を使用しており、つれてEMi対策用コンデンサも
多数必要である。かゝるコンデンサを個別部品で
取付けるようにすると部品点数が多くなる、実装
スペースが大になつて小型化が図れなくなる、取
付け作業が煩雑でコストアツプを招くなどの難点
がある。特にハイブリツドICでは基板にはセラ
ミツクを用い、それに各種集積回路及び個別部品
を取付けてなるが、寸法はそれ程大きくないのが
普通であるから、多数のコンデンサを個別部品で
取付けるのは問題である。
Integrated circuits use a large number of transistors and diodes, which also requires a large number of capacitors for EMi countermeasures. If such a capacitor is mounted as individual parts, there are disadvantages such as the number of parts increases, the mounting space becomes large, making it impossible to achieve miniaturization, and the mounting work is complicated, leading to increased costs. Particularly in hybrid ICs, the substrate is made of ceramic and various integrated circuits and individual parts are attached to it, but the dimensions are usually not that large, so it is a problem to attach a large number of capacitors with individual parts.

考案の目的 本考案は極めて簡単な手段でEMi対策用コンデ
ンサを形成し、個別部品取付けに伴なう上記問題
を改善しようとするものである。
Purpose of the invention The present invention is an attempt to form a capacitor for EMi countermeasures using extremely simple means and to improve the above-mentioned problems associated with mounting individual parts.

考案の構成 本考案はハイブリツド集積回路のダイオード部
に並列に接続される電磁波妨害対策用のコンデン
サにおいて、該ハイブリツド集積回路の基板上の
配線パターンの、該ダイオード部の一端が接続さ
れる配線パターンに誘電体膜を被着し、該ダイオ
ード部の他端が接続される配線パターンを該誘電
体膜上に延在させ、該誘電体膜を介して対向する
両配線パターンのクロスオーバー部で静電容量を
形成させてなることを特徴とするが、次に実施例
を参照しながらこれを説明する。
Structure of the invention The present invention relates to a capacitor for preventing electromagnetic interference that is connected in parallel to a diode part of a hybrid integrated circuit, and a capacitor that is connected in parallel to a diode part of a wiring pattern on a board of the hybrid integrated circuit to which one end of the diode part is connected. A dielectric film is deposited, a wiring pattern to which the other end of the diode part is connected is extended over the dielectric film, and static electricity is removed at the crossover portion of both wiring patterns facing each other through the dielectric film. The feature is that a capacitance is formed, which will be explained next with reference to Examples.

考案の実施例 第3図は本考案の実施例を示し、10,12,
14はハイブリツドIC基板SUB上の配線パター
ン、16はこれらの配線パターンに取付けたチツ
プダイオードである。コンデンサを形成するため
配線パターン10,14上に誘電体膜18が被着
され、その上に配線パターン12の拡大部12
a,12bが形成される。ハイブリツドICのセ
ラミツク基板上配線は例えばスクリーンで導電ペ
ーストを印刷し、加熱焼結して形成されるから図
示のようなパターンはまず配線パターン10,1
4を印刷し、その上に誘電体膜18を印刷し、そ
の後配線パターン12を印刷して形成できる。
Embodiment of the invention FIG. 3 shows an embodiment of the invention, 10, 12,
14 is a wiring pattern on the hybrid IC board SUB, and 16 is a chip diode attached to these wiring patterns. A dielectric film 18 is deposited on the wiring patterns 10 and 14 to form a capacitor, and an enlarged portion 12 of the wiring pattern 12 is formed on the dielectric film 18.
a, 12b are formed. The wiring on the ceramic substrate of a hybrid IC is formed by, for example, printing a conductive paste with a screen and heating and sintering it, so the pattern shown in the figure is first formed by wiring patterns 10, 1
4, print the dielectric film 18 thereon, and then print the wiring pattern 12.

導体パターン10と12a及び14と12bは
誘電体膜18を介して対向しているからこれらの
クロスオーバー部はコンデンサを形成し、そして
チツプダイオード16は端子16aと16b、1
6aと16cに接続される2個のダイオードを有
するから、結局第3図aの装置は同図bの等価回
路で表わされる。これは第1図のトランジスタQ
1のベース入力回路に挿入されるダイオードD
1,D2、コンデンサC1,C2の回路に他なら
ない。こうして本装置によれば個別部品で作られ
るコンデンサC1,C2を用いて接続作業をする
必要なく、ダイオードD1,D2にEMi対策を施
すことができる。
Since the conductor patterns 10 and 12a and 14 and 12b face each other with the dielectric film 18 in between, these crossover portions form a capacitor, and the chip diode 16 connects the terminals 16a, 16b, 1
Since there are two diodes connected to 6a and 16c, the device of FIG. 3a is finally represented by the equivalent circuit of FIG. 3b. This is the transistor Q in Figure 1.
Diode D inserted into the base input circuit of 1
1, D2, and capacitors C1 and C2. In this way, according to the present device, EMi countermeasures can be applied to the diodes D1 and D2 without the need for connection work using the capacitors C1 and C2 made of individual parts.

誘電体膜18がガラスセラミツクの場合、誘電
率εsは9〜15である。従つてパターン10と12
aまたは14と12bの対向する面積をS、間隔
従つて誘電体膜の厚さdを0.04mmとすると、コン
デンサC1,C2の容量C〔PF〕はC=εs・εo・
S/d=(1.86〜15)×Smm2となる(εo=8.854×
10-12〔F/m〕)。この式を用いて必要な容量値が
得られるように対向面積Smm2を定めればよい。
EMi用コンデンサの容量値は20pF以下程度の小
容量であり、配線パターンの幅は数mmであるから
単に両配線パターンをクロスオーバーさせる、或
いはクロスオーバー部では幅又は長さを若干拡大
する、程度でよい。
When the dielectric film 18 is made of glass ceramic, the dielectric constant εs is 9 to 15. Therefore patterns 10 and 12
If the opposing area of a or 14 and 12b is S, and the spacing and the thickness of the dielectric film d are 0.04 mm, the capacitance C [PF] of capacitors C1 and C2 is C=εs・εo・
S/d=(1.86~15)×Smm 2 (εo=8.854×
10 -12 [F/m]). Using this formula, the facing area Smm 2 may be determined so as to obtain the required capacitance value.
The capacitance value of the EMi capacitor is small, about 20 pF or less, and the width of the wiring pattern is several mm, so it is necessary to simply cross over both wiring patterns, or slightly expand the width or length at the crossover part. That's fine.

考案の効果 以上説明したことから明らかなように本考案で
はEMi用コンデンサの実装スペースを必要としな
いからハイブリツドICの小型化が可能となる、
チツプコンデンサなどの個別部品を取付ける作業
がなくなり、製造に要する時間、コストの低減が
可能になる等の効果が得られる。
Effects of the invention As is clear from the above explanation, this invention does not require mounting space for the EMi capacitor, making it possible to downsize the hybrid IC.
This eliminates the need to attach individual parts such as chip capacitors, resulting in reductions in manufacturing time and costs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図はEMi対策用コンデンサを説
明する回路図、第3図は本考案の実施例を示す図
でaは平面図、bは等価回路図である。 図面でC1〜C3はEMi対策用コンデンサ、
SUBはハイブリツドICの基板、10,12,1
4は配線パターン、D1,D2はダイオード、1
6はその個別部品、18は誘電体膜、12a,1
2bは配線パターン12の配線パターン10,1
4上への延在部である。
1 and 2 are circuit diagrams illustrating a capacitor for EMi countermeasures, and FIG. 3 is a diagram showing an embodiment of the present invention, in which a is a plan view and b is an equivalent circuit diagram. In the drawing, C1 to C3 are EMi countermeasure capacitors,
SUB is the hybrid IC board, 10, 12, 1
4 is a wiring pattern, D1 and D2 are diodes, 1
6 is its individual component, 18 is a dielectric film, 12a, 1
2b is the wiring pattern 10,1 of the wiring pattern 12
4. It is an extension part above 4.

Claims (1)

【実用新案登録請求の範囲】 ハイブリツド集積回路のダイオード部に並列に
接続される電磁波妨害対策用のコンデンサにおい
て、 該ハイブリツド集積回路の基板上の配線パター
ンの、該ダイオード部の一端が接続される配線パ
ターンに誘電体膜を被着し、該ダイオード部の他
端が接続される配線パターンを該誘電体膜上に延
在させ、該誘電体膜を介して対向する両配線パタ
ーンのクロスオーバー部で静電容量を形成させて
なることを特徴とするハイブリツド集積回路用コ
ンデンサ。
[Claims for Utility Model Registration] In a capacitor for electromagnetic interference prevention that is connected in parallel to a diode section of a hybrid integrated circuit, the wiring to which one end of the diode section of the wiring pattern on the substrate of the hybrid integrated circuit is connected. A dielectric film is applied to the pattern, a wiring pattern to which the other end of the diode section is connected is extended over the dielectric film, and a crossover portion of both wiring patterns facing each other with the dielectric film interposed therebetween is formed. A capacitor for a hybrid integrated circuit characterized by forming a capacitance.
JP16501083U 1983-10-25 1983-10-25 Capacitors for hybrid integrated circuits Granted JPS6073224U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16501083U JPS6073224U (en) 1983-10-25 1983-10-25 Capacitors for hybrid integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16501083U JPS6073224U (en) 1983-10-25 1983-10-25 Capacitors for hybrid integrated circuits

Publications (2)

Publication Number Publication Date
JPS6073224U JPS6073224U (en) 1985-05-23
JPH0220863Y2 true JPH0220863Y2 (en) 1990-06-06

Family

ID=30361612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16501083U Granted JPS6073224U (en) 1983-10-25 1983-10-25 Capacitors for hybrid integrated circuits

Country Status (1)

Country Link
JP (1) JPS6073224U (en)

Also Published As

Publication number Publication date
JPS6073224U (en) 1985-05-23

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