JPH04302557A - Code error rate measuring instrument - Google Patents

Abstract

PURPOSE:To present a device which performs the processing, which is interrupted by turning-off of a main power source, as soon as possible after turning- off of the main power source. CONSTITUTION:A switch 2 is switched to connect the main power source to the power supply circuit of a measuring instrument, and its state is outputted. If the voltage supplied to the power supply circuit is reduced to a certain value or lower, a main power source turning-off detection circuit 1 outputs a signal indicating turning-off of the main power source. A switch state holding circuit 3 inverts the state by a prescribed threshold of chattering generated for switching or the switch and holds and outputs this state. An input latch 4 receives the output of the switch state holding circuit and the main power source turning-off signal to store the output of the switch state holding circuit.

Description

[Detailed description of the invention]

0001

[Field of Application of the Invention] The present invention is a code error rate measuring device used to evaluate the transmission quality of a digital communication line, which detects a main power failure and performs a predetermined process. . That is, the present invention relates to a code error rate measuring device that detects whether the power switch has been turned off or due to a power outage according to the intention of the operator of the device, and changes the processing routine after the main power is turned off.

0002

2. Description of the Related Art A code error rate measuring device is mainly used for maintenance of communication lines. The configuration of a typical code error rate measuring device is as follows. The transmitting side is equipped with a clock generator and a pattern generator that generates a pseudo-random pattern in synchronization with the clock. Then, the pseudorandom pattern is transmitted to the receiving side via the line under test. The receiving side includes an error detection circuit, an error counter for counting the number of detected errors, a pattern generator, and a synchronization establishment circuit for establishing synchronization between the transmitting side signal and the receiving side signal. .

[0003] As an example of the use of this bit error rate measuring device,
Sometimes a communication line is connected for a long period of time and the quality of the line is evaluated based on the average error rate. In such a case, if there is a power outage during measurement, the measurement will be interrupted and it will be necessary to restart the measurement after the power outage is restored. It is also necessary that the measurer be able to interrupt the measurement at will by operating a switch or the like during the measurement.

For example, in measuring the bit error rate, if the measurer turns off the switch arbitrarily, the measurement data, which is the bit error rate data, is stored, as well as the interface conditions, measurement conditions, line setting conditions, etc. It is desirable to keep it. If these conditions are stored, the measurer is freed from the need to set a large number of complicated conditions when restarting measurement. Furthermore, even if the measurer is not skilled, the measurement can be easily carried out. In addition, it is also desirable that when restarting measurement, the measurer can select whether to return to the initial measurement state or to return to the continuous measurement state, based on his or her judgment.

[0005] Furthermore, when the main power is cut off due to an external factor such as a power outage, it is necessary to protect the measurement data up to that point. If line settings are performed using a switchboard or the like, the line setting conditions must also be stored and protected. For example, when a telephone exchange is controlled to connect a line, such as with a dialing function on a telephone, if the line settings are not memorized by the measuring device when the power is restored, the line will remain connected. Further, even when a branch box for connecting to the measuring device is inserted in the middle of a dedicated line for control, it is necessary to memorize the line settings so that the line does not continue to be disconnected.

[0006] In this way, even if the operator turns off the switch at will, or if the main power is cut off due to an external factor such as a power outage, the power supply circuit (generally a DC power supply) inside the measuring instrument (generally a DC power supply, It is necessary to memorize the necessary data until the measuring device stops functioning due to a drop in the voltage of the "internal power supply"), and to memorize the various measurement conditions in preparation for recovery from a main power outage. . At this time, the data to be saved may differ depending on the cause of the main power outage, and the processing when recovering from the main power outage also differs.
Treatment appropriate to each cause is required. In order to do this, if the main power is cut off for some reason during measurement, it is necessary to check whether the measurer turned off the switch voluntarily during the time until the voltage of the internal power supply drops, or whether it was caused by an external power failure such as a power outage. It is required to detect as soon as possible whether the main power supply has been cut off due to a cause.

However, when the operator turns off the switch, chattering occurs in the switch, so it takes a certain amount of time until the chattering subsides to determine whether the switch is on or off. have to wait for time. Only when the state of this switch can be determined can it be determined whether the cause of the main power cut-off is artificial or caused by an external factor. As a result, it is not possible to secure enough processing time to compress the measurement data, rearrange it, and store it in the backup memory. There was a problem that there was not enough processing time to memorize the information.

For example, as a conventional technique, Japanese Patent Laid-Open No. 58-1
There is a main power failure recovery method disclosed in Japanese Patent No. 69218, but in this method, the running program is saved in a memory backed up by a battery or the like when the main power is turned off, and is read out when the power is restored. It is determined whether the saved program is a main power-off program or not, so that even if there is switch chattering, the return program will operate correctly when the power is restored. However, with this method, no processing can be performed until the chattering subsides, so although normal operation is guaranteed when the power is restored,
The processing time when the main power is turned off is substantially the maximum time from when the chattering settles until the internal power is turned off, and it cannot be said that sufficient processing time after the main power is turned off has been secured. Note that, generally, the time from when the power switch is turned off until the chattering subsides is about 40 ms.

[0009]

[Problems to be Solved by the Invention] As stated above, when a main power outage occurs, it is difficult to determine whether the main power was cut off due to an external factor such as a power outage. It is necessary to judge whether the situation has occurred and to perform processing appropriate to the situation. However, in the conventional technology, chattering occurs when the operator turns off the switch, so it is necessary to wait for a certain period of time to determine the state of the switch until the chattering subsides. Therefore, it was not possible to take enough processing time for each factor. The purpose of the present invention is to quickly determine whether the operator turned off the switch manually or whether the main power supply was cut off due to an external factor such as a power outage, and the processing time for each factor is longer than before. An object of the present invention is to provide a code error rate measuring device that has the following characteristics.

0010

[Means for Solving the Problems] In order to solve such problems, in the code error rate measuring device of the present invention, switch 2
The present invention is characterized in that the cause of the main power cut-off is detected before the chattering due to switching has subsided, and the time for processing corresponding to each cause is made as long as possible. For this purpose, a switch state holding circuit 3 that inverts the state with the first pulse that successively arrives due to chattering caused by the transition of the switch 2 between on and off states, holds that state, and outputs that state. It is characterized by having the following. That is, in the code error rate measurement device of the present invention, a switch is provided that switches whether or not to supply the main power supply supplied from the outside to the power supply circuit 7 of the code error rate measurement device 6, and outputs its on or off state. 2, and a main power cutoff detection circuit 1 that outputs a main power cutoff signal when the voltage of the main power supply supplied to the power supply circuit 7 falls below a specified value, and a main power cutoff detection circuit 1 that outputs a main power cutoff signal when the voltage of the main power supply supplied to the power supply circuit 7 becomes lower than a specified value, and a predetermined chattering that occurs when switching the switch. When the threshold value is reached, the switch state holding circuit 3 inverts the logic state, holds the logic state, and outputs the logic state, and the output of the switch state holding circuit 3 and main power failure detection. The input latch 4 receives the main power supply cutoff signal from the circuit 1 and stores the output of the switch state holding circuit 3.

[0011]

[Operation] First, when the switch 2 is set to OFF, that is, when the measurer intentionally turns off the main power, the processing is as follows. When the switch 2 is set to OFF, the voltage of the main power supply decreases and chattering occurs. In this case, the switch state holding circuit 3 inverts the logic state of the switch state holding circuit 3 with the first pulse that successively arrives due to this chattering, and holds that state. Next, the main power supply cutoff detection circuit 1 detects a drop in the voltage of the main power supply, and when the voltage falls below a specified voltage, outputs a result indicating that the voltage has dropped. Based on this result, main power-off interrupt processing begins. The input latch 4 receives the detection result of the main power supply cutoff, latches the state of the switch state holding circuit 3 (off), reads the state of the input latch 4 in the interrupt processing, and determines that the main power supply cutoff was caused by the operator. to decide. Next, when the setting of switch 2 is on, that is, when the main power is turned off due to an external factor, the processing is as follows. The state of switch 2 remains on, but the mains voltage drops. In this case, the switch state holding circuit 3 is in an on state. Thereafter, when the output of the main power-off detection circuit 1 becomes lower than a predetermined voltage, interrupt processing is started. Alternatively, the input latch 4 receives the input disconnection detection result and latches the state of the switch state holding circuit 3. In the interrupt processing, the state of the input latch 4 is read, and since the state is on, it is determined that the main power has been cut off due to an external factor. As described above, the present invention differs from the prior art in that the process when the main power is turned off can be performed before the chattering of the switch 2 ends.

0012

[Embodiment] An embodiment of the code error rate measuring device of the present invention will be described below. The transmitting side includes a clock generator and a pattern generator that generates a pseudo-random pattern in synchronization with the clock. Then, the pseudorandom pattern is transmitted to the receiving side via the line under test. The receiving side, which is the code error rate measuring device 6, includes an error detection circuit for detecting errors in the pseudo-random pattern, an error counter for counting the number of detected errors, a pattern generator, and a pseudo-random pattern error detection circuit on the transmitting side. It has a synchronization establishment circuit for establishing synchronization between the signal and the pseudo-random pattern signal on the receiving side.

The main power failure detection section 5 of the bit error rate measuring device has the following configuration. That is, it has a switch 2 that switches whether or not to supply the main power supply supplied from the outside to the power supply circuit of the bit error rate measuring device 6, and outputs its on or off state, and the switch 2 that is supplied to the power supply circuit. The main power cutoff detection circuit 1 outputs a main power cutoff signal when the voltage falls below a specified value, and the logic state is reversed at the first pulse that arrives consecutively due to chattering that occurs when switching a switch. The switch state holding circuit 3 outputs the state, and receives the output of the switch state holding circuit 3 and the main power cutoff signal from the main power cutoff detection circuit 1, and changes the switch state. It also includes an input latch 4 that stores the output of the holding circuit 3.

The operating procedure of this measuring device will be described below with reference to FIGS. 1 and 2. In FIG. 1, the thick line indicates the external main power source. Further, lines A, B, C, D, and E each indicate the input/output relationship between the individual devices described below. Further, the circuit diagram shown in FIG. 3 is a diagram showing the detailed configuration of the switch 2 and the switch state holding circuit 3. The switch 2 has a switch that operates in conjunction with an external main power source, and the switch state holding circuit 3 is composed of a D flip-flop. First, the code error rate measuring device 6 receives a pseudo-random pattern signal, generates a pseudo-random pattern signal that is synchronized with the received signal, and detects errors using an error detection circuit. Therefore, if the main power is cut off for some reason, the following processing is performed.

(1) The main power supply cutoff detection circuit 1 detects a drop in the voltage A of the main power supply. In this case, the main power failure detection unit 5 cannot yet determine the cause of the voltage drop. This is the operation at point A in (a) or (b) in FIG.

(2) The switch 2 outputs the state B of the switch 2 to the switch state holding circuit 3 in response to the decrease in the voltage A detected by the main power cutoff detection circuit 1. This is the operation at point A in FIG. 2(a).

(3) The switch state holding circuit 3 receives the output B from the switch 2 and holds the state of the switch 2. Here, conventionally, it has not been possible to immediately determine whether the switch 2 is on or off due to chattering when the switch 2 is switched. In the present invention, when chattering occurs due to switching of switch 2, switch state holding circuit 3 detects that the output from switch 2 has reached a predetermined threshold (for example, (2V or higher) detects the first pulse, inverts its state, and holds it. This is the operation at point A in FIG. 2(a).

(4) When the switch 2 is not switched, there is no change in the output B from the switch 2, and the switch state holding circuit 3 maintains its on state. This is the operation from a to b in FIG. 2(a).

(5) In this embodiment, the voltage of A is set to be 80V as the specified value, and when the voltage falls below the specified value, it is determined that the main power supply is turned off, and the voltage A of this main power supply is 80V or less. If so, the main power cutoff detection circuit 1 outputs the main power cutoff signal E. This is the operation at point A in (a) or (b) in FIG.

(6) When the main power-off detection circuit 1 determines that the main power is off, the output E of the main power-off detection circuit 1 stores the output D of the switch state holding circuit 3 in the input latch 4. In other words,
If the state is (3), the main power has been cut off because switch 2 has been disconnected, and if the state is (4), the main power has been cut off even though the state of switch 2 has not changed. For example, the main power is cut off due to an external factor such as a power outage, and this state is stored in the input latch 4. This is the operation at point A in (a) or (b) in FIG.

(7) Depending on the value of the input latch 4, it is determined whether the main power is cut off due to the switch 2 being turned off or the power is cut off due to an external factor, and each process is performed. This process is limited to the period from A to C in FIG. 2(a) or (b). The main power failure detection circuit 1 has a method of lowering the main power directly or using a transformer, rectifying and smoothing the voltage, converting it to direct current, and comparing it with a reference value using a comparator.
There is a method, such as that disclosed in Japanese Patent No. 12630, in which a retrigger monostable multivibrator is used to change the logic state when the main power supply is missing for one cycle or half a cycle or more. In the above embodiment, the main power source is the commercial power source (
I explained the case of 50 hertz, 100 volts,
It is clear that the effects of the present invention can be achieved even when the main power supply externally supplied to the bit error rate measuring device is direct current.

As explained above, by using the present invention, the time from the occurrence of a main power outage to the start of main power outage processing can be minimized, thereby reducing the bit error rate that would otherwise require complicated processing at the time of a main power outage. It is extremely effective in measuring equipment.

[0023] According to the present invention, predetermined processing can be executed immediately after the power switch is turned off, so that the time during which processing can be performed can be extended by about 20 ms compared to the conventional example. Therefore, for example, if the clock speed is 12.5MHz,
Assuming that a CPU with four bus cycles and an average of five bus cycles per instruction is used, 12,000 more steps can be processed. The following can be considered as an example of processing using this 20 ms time.

The error rate can be evaluated as the number of errors/number of clocks. Recent requirements for communication lines require that error rates be evaluated in units of 1/100th of a second. For example, there are similar movements in the International Telegraph and Telephone Advisory Committee. Therefore, the cycle for detecting errors is set to 10
It becomes necessary to set it to ms.

To measure the error rate, in addition to error detection in units of 10 ms, the following processing is performed in units of 1 second in order to evaluate the transmission quality of the line. For example, parameters called deterioration seconds, abnormal deterioration seconds, etc. are provided and the line is evaluated for each time period. Error detection processing in units of 10 ms requires 5 ms. Furthermore, in addition to the previous 5 ms, processing every second requires 3 ms for comparison processing between previous data and currently measured data, for a total of 8 ms. Even if the processing requires 5 ms or 8 ms, the processing can be performed within a period of 10 ms. However, in order to read the results of that processing into backup non-volatile RAM, which retains the data even if the internal power is turned off, instead of into normal RAM,
An additional 5 ms is required. In other words, 8ms+5ms
This requires a time of 13ms. Furthermore, it not only simply saves data, but also adds a parity code and checksum error code to the data to check whether it is correct after recovering from a main power failure. If it takes more time. If this process takes 13 ms or more, it becomes impossible to detect errors every 10 ms. A possible solution here would be to increase the number of digits in the counter and change the error detection cycle to 20ms or 50ms, but increasing the number of digits in the counter is not easy from the point of view of price/performance ratio. cannot be adopted. Therefore, during normal measurement, only error detection processing and measurement data comparison processing are performed, and data is not saved, and only when the main power is turned off, normal RA
This involves performing a process of copying the data written in M to a non-volatile backup RAM, and moving on to a process of saving the data.

[0026] In the present invention, it takes 20 ms from when the main power is cut off to when it is determined what is the cause of the main power cut.
The processing time will be extended. Using this available processing time, we can process data for error detection in units of 10 ms,
All processing data for each second can be easily stored in a non-volatile RAM for backup.

[0027]

[Effects of the Invention] The configuration of the present invention is capable of detecting the cause of the main power outage immediately after the power switch is turned off and before the chatter of the switch has subsided, and detecting the main power outage in accordance with the cause. Now you can start the process.
The main power-off processing time can be sufficiently long. As a result, there is sufficient time to carry out processing procedures appropriate to the detected cause of the main power outage, and when recovering from the main power outage, recovery processing commensurate with the cause of the main power outage can be performed. In addition, when measuring error rates over a long period of time, if data is sent to an external control system at regular intervals, when the main power is cut off due to external factors such as a power outage,
It is also possible to send abnormal messages to the control system. Furthermore, even if it is not possible to increase the speed of the counter and there is no room to store the detected data in backup memory every second, it is now possible to take a longer processing time when the main power is turned off. , it is possible to perform processing to retain that data in the event of a power outage.

[0028]

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a code error detection device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a timing chart during execution of an embodiment of the present invention, and (a) is a diagram showing changes in output when a switch is turned off. (b) A diagram showing changes in output when the main power is cut off due to external factors.

FIG. 3 is a diagram showing a circuit configuration of a switch 2 and a switch state holding circuit 3 according to an embodiment of the present invention.

[Explanation of symbols]

1 Main power failure detection circuit 2 Switch 3　　　　　Switch state holding circuit 4 Input latch 5　　　　　　Main power failure detection section 6 Bit error rate measuring device 7 Power supply circuit

Claims (1)

[Claims] 1. A code error rate measuring device, comprising: a switch (2) for switching whether or not to supply a main power source from an external source to a power supply circuit of the code error rate measuring device and outputting its on or off state; , a main power cutoff detection circuit (1) that outputs a main power cutoff signal when the voltage supplied to the power supply circuit becomes less than a specified value; a switch state holding circuit (3) that inverts the state, holds the state, and outputs the state; and receives the output of the switch state holding circuit and a main power cutoff signal, and stores the output of the switch state holding circuit. A code error rate measuring device comprising an input latch (4).