JPH04302311A - Bias circuit and method of bias voltage generation - Google Patents

Abstract

PURPOSE: To obtain a reference voltage for emitter coupled logic(ECL) which is tolerant of source voltage variation by providing a bias network, which supplies a 1st and a 2nd ECL reference voltage, with a differential amplifier. CONSTITUTION: The differential amplifier which detects the potential of nodes 44 and 46 by NPN bipolar transistors(TR) 50 and 52 and amplifies and feeds the different back to a node 28 hold the operation points of the nodes 44 and 46 at the same potential. Then P channel FETs 54 and 56 form mirror constitution and is adapted to asymmetrical output. Resistors 58 and 60 increase the output impedance of a P channel FET 54 of a node 62 and the gain of the differential amplifier is therefore increased. The P channel FET 64 connects the collector terminal of an NPN TR 26 to the node 28. When the FET 64 is not present, all the TRs are OFF and have stable operation points where VREF1 =VREF2 =0. The FET 64 sends a supply voltage to the node 28 when this state is entered to prevent the circuit from becoming inactive.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD This invention relates to circuits for generating specified voltage levels. More specifically, the present invention provides EC
This invention relates to an improvement in a bias circuit network for generating an L reference voltage.

0002

[Prior art and problems of the invention] Emitter coupled logic (ECL)
) circuit is constructed from a highly capable group of digital integrated circuits. ECL circuits were invented long before the invention of integrated circuits. Because IC processes have enabled the development of such circuits, ECL circuits are currently the fastest digital ICs available on the market, with typical propagation delays of less than 1 ns and clock speeds approaching 1 GHz. It is.

ECL circuits are based on non-saturated current switches, also known as emitter-coupled pairs. By carefully choosing the circuit parameters (including the supply current), the basic ECL circuit can be configured such that the bipolar transistors of the current switches do not saturate, which reduces the short propagation delay times typical of ECL circuits. It is a contributing factor.

BiCMOS chips with ECL I/O (input/output circuits) typically operate between ground potential and a supply voltage of about -5 volts and require a reference voltage V1 of about -1.3 volts. do. If a complete ECL stage is also to be implemented, another reference voltage V2 approximately 1.2 volts higher than the supply voltage (VSS) is required.

The reference voltage should be made as independent as possible from temperature and supply voltage variations to maintain stable logic reference voltages and output voltage levels. Unfortunately, these two important values are affected by temperature and supply voltage. Misalignment of voltage transfer characteristics presents a particularly large design problem in large digital systems that incorporate many small units, each receiving separate supply voltages and ambient temperatures.

A number of methods have been devised in the past in an attempt to obtain temperature independent vias. One method employs a Zener diode reference and requires high voltages. Alternatively, a voltage with a negative temperature coefficient (e.g. base
emitter voltage) with a positive temperature coefficient (i.e., a voltage proportional to the thermal voltage VT = κT/q, where κ
= Boltzmann constant, T = temperature, q = charge of the electrons) can be used. The latter type of bias network is shown in FIG.

Although there has been some success in overcoming temperature effects, efforts to neutralize supply voltage irregularities have
Conventional techniques were not successful. A common way to compensate for such variations has been to add a shunt transistor to act as a regulator and hold the collector current of the voltage generator transistor constant. Unfortunately, such devices require the use of pnp transistors as shunt elements. As a result, the fabrication of suitable equipment is
Significant complexity due to the device's inherent lateral geometry (npn transistors, on the other hand, are vertically structured devices)
. Fabrication of vertical PNP devices can be extremely difficult and expensive. A further problem is that pnp transistors are considerably slower due to npn devices.

[0008]

OBJECTS OF THE INVENTION Therefore, an object of the present invention is to overcome the above-mentioned problems by a novel circuit configuration and provide a reference voltage that is resistant to power supply voltage fluctuations.

[0009]

SUMMARY OF THE INVENTION One embodiment of the present invention overcomes the shortcomings of the prior art by improving the biasing circuitry that provides the first and second ECL reference voltages. This improvement comprises a first bipolar transistor whose base is connected to the base of a second bipolar transistor, the emitter of the second transistor is connected to the first power supply terminal, and the emitter of the first transistor is connected to the base of the second bipolar transistor. A bias network of the type connected to the first power supply terminal via a resistor is targeted. The collectors of the transistors are connected to a common node via a resistor. The emitter of the third bipolar transistor is connected to this node. In a biasing network of the type described above, the invention provides such a network with a differential amplifier that adjusts the base voltage of the third bipolar transistor with respect to changes in the supply voltage applied to the first power supply terminal. An improvement is made in which stabilization is achieved by equalizing the voltages at the collector terminals of the first and second bipolar transistors.

In another embodiment, the invention provides an E transistor of the type comprising a first bipolar transistor whose base is connected to the base of a second bipolar transistor.
A method for controlling a CL bias network is provided. The emitter of the second transistor is connected to the first power supply terminal, and the emitter of the first transistor is connected to the first power supply terminal through a resistor. The collectors of the transistors are connected to a common node through a resistor, and the emitters of the third bipolar transistor are connected to the common node. In such an ECL bias network arrangement, the method of the invention includes adjusting the voltage at the common node such that the voltages at the collector terminals of the first and second transistors are equal.

[0011]

[Detailed description of embodiments of the invention]

FIG. 5 is a schematic diagram of a common circuit configuration that supplies the necessary reference voltages VREF1 and VREF2 to the ECL logic circuit. Such a network, with a mechanism (described below) to counteract the effects of temperature on the bias voltage, is particularly useful in conjunction with the 100k series ECL.

A bias network is inserted between the first power supply terminal 10 and the second power supply terminal 12. ECLI/O
Typically, BiCMOS chips with a power supply terminal 12 are operated between ground potential and -5 volts, and in the device according to FIG. 5 the first power terminal 10 is held at ground potential and the second power terminal 12 is at
It is held at 5 volts. Parallel circuit branches 14 and 1
6 connects the first power terminal 10 to the second power terminal 12.

Circuit branch 14 includes npn bipolar transistors 18 and 2 connected in series as shown.
Consists of 0. Resistor 22 is transistor 20
is inserted between the emitter of and the second power supply terminal 12.

[0014] The circuit branch 16 has a first power supply terminal 10 and
A resistor 24 is inserted between the collector terminal of an npn bipolar transistor 26. The base of transistor 18 of circuit branch 14 is connected to transistor 26
is connected to the collector terminal of the transistor 26
is connected to the base of transistor 20 of circuit branch 14.

The emitter terminal of transistor 26 is connected to node 28, which determines the voltage level applied to subbranches 30 and 32 of the parallel circuit.

The sub-branch 30 consists of a resistor 33, an npn transistor 34, and a resistor 35, which is placed between the emitter terminal of the transistor 34 and the second power supply terminal 12 as shown. .

The sub-branch 32 has its emitter terminal connected directly to the second power supply terminal 12 and its base connected to the sub-branch 30.
The device includes an npn bipolar transistor 40 connected to the base of a bipolar transistor 34 . A resistor 42 connects the collector terminal of transistor 40 and node 2.
It is located between 8.

The operation of an ECL bias network of the type illustrated in FIG. 5 is well known. When the base current of a bipolar transistor can be ignored and IS is the saturation current, IC = IE = IS exp (VBE/VT
), and further assume that the base voltage of transistor 26 is such that the voltages at node 44 of sub-branch 30 and node 46 of sub-branch 32 are the same: The analysis shown below applies.

R42i32=R33i30

(1) i32=Is40 ex
p(VBE40/VT)
(2) i30
=Is34 exp((VBE40-R35i30)/
VT) (3)
From the above formula:

R33/R42=
i32/i30=(Is40/Is34)exp(
R35i30/VT ) (4) Therefore: i30=(VT /R35)ln (R33IS34
/R42IS40)
(5) i32+i30=(R33/R42+1)(V
T /R35)ln (R33IS34 /R42IS
40)

(6) In the end, the two reference voltages are as follows. VREF1=R24(i32+i30)VBE18=V
T (R24/R35) (R33/R42+1)ln
(R33IS34 /R42IS40)+VBE18


(7) VREF2≒V28-V1
2=R42i32+VBE40=VT (R33/R3
5) ln (R33/IS34 /R42IS40)
VBE40 (8) VREF2-(V2
8-V12)=VBE26-VBE20=VT (ln
((i32+i30)/IS26)-ln (VR
Note that EF2/R22ln20)) is small but not exactly zero. For example, if two transistors are the same and the ratio of collector currents is 2, then ΔV
BE=VT ln 2=18 mv.

[0020] The temperature coefficient of VBE is negative (≒-1.5mV/
°C), and its absolute value decreases as Ic increases. The voltage across R24 and R42 is determined solely by the ratio of resistance to saturation current. R35, R42,
Temperature changes in R33 and R24 will be canceled out if the temperature coefficients of the resistors are the same, but IS40/IS34
is temperature invariant for transistors of the same type.

The voltage V24 across the resistor 24 is obtained from equation 7 as follows. V24=VT (R24/R35) (R33/R42+
1) ln (R33IS34 /R42IS40


(9)

FIG. 5
The temperature dependence of the reference voltage obtained from the circuit can be explained as follows. Assuming that the resistance ratio and saturation current ratio are temperature dependent, V24 is linear in T, so ΔV24/ΔT=V24/T. For example, V24=500mV and T=300°K
If so, ΔV24/ΔT=500/300=1.67
mV/℃ and ΔVREF1/ΔT=ΔV24/ΔT+
VBE18/ΔT≒1.67-1.5=0.17mV/
℃, and VREF1≒500mV+800mV=1.
It is 3V. A similar analysis applies to VREF2. Therefore, the circuit of FIG. 1 utilizes a voltage with a negative temperature coefficient and a voltage with a positive coefficient to obtain a temperature independent bias. As a result, the resulting values of VREF1 and VREF2 are virtually invariant with respect to temperature. However, looking back, this analysis requires V44=V
46. That is, the temperature invariance of the reference voltage is associated with the assumption that the potentials at nodes 44 and 46 are equal.

FIG. 6 is a graph illustrating the potential (relative to the supply voltage) at nodes 44 and 46 as a function of the potential at node 28. The stable operating point of the circuit, indicated at 48, occurs when the two nodes 44 and 46 are at the same potential. The potential at node 28 increases as the current in circuit branch 16 increases. As shown, at low currents the circuit sub-branch 3
The voltage drop across the zero resistor 35 is negligible. Therefore, the saturation current of transistor 34 is
The current in sub-branch 30 is greater than the current in sub-branch 32 and the potential at node 44 is less than the potential at node 46, assuming that the saturation current is greater than zero.

As the current increases, VBE 34 becomes substantially smaller as the voltage drop across resistor 35 increases. At this large current, the current in sub-branch 32 is greater than the current in sub-branch 30, and the potential at node 44 is
higher than the potential of node 46. As shown below, the present invention forces the circuit of FIG. 5 to the crossover operating point 48 of FIG. The present invention achieves this advantageous operation of the circuit by coupling the inputs to nodes 44 and 46 and the output to transistor 26.
This is achieved by utilizing a BiCMOS differential amplifier coupled to the base of the . The high gain of the amplifier is at node 4
4 and 46 nearly identical voltages, and VREF
1 and VREF2 to the supply voltage V12-V10. From the above analysis, it will be seen that by equalizing the potentials of nodes 44 and 46, temperature invariance of VREF1 and VREF2 is achieved. Therefore, the present invention deals with variations in both temperature and supply voltage.

FIG. 1 is a circuit schematic diagram of an improved ECL biasing network according to the present invention. The elements of the conventional ECL bias network with temperature compensation of FIG. 5 are labeled with corresponding numbers for ease of explanation.

The potentials at nodes 44 and 46 are maintained at operating point 48 by a differential amplifier having npn bipolar transistors 50 and 52 as input devices. P-channel FETs 54 and 56 are arranged in a mirror configuration. As shown below, such a configuration is well suited for asymmetric outputs. Resistors 58 and 60 increase the output impedance of p-channel FET 54 at node 62, thus increasing the gain of the differential amplifier. p-channel FET 46 is npn
The collector terminal of transistor 26 is connected to node 28. If FET 64 is not present, the circuit of FIG.
VREF1 = VREF2 when all transistors are off
= 0, which is a stable operating point. As shown, FET 64 ensures that the supply voltage is transferred to node 28 when this condition occurs to prevent the circuit from becoming "stuck" in an inactive state.

In operation, assuming that differential amplifier bipolar transistors 50 and 52 are off, nodes 28 and 62 are both at ground potential. transistor 2
0 is also off, and its base voltage is 600m above earth potential.
Since the voltage is not higher than V, VREF2=0. As stated above, the presence of p-channel FET 64 prevents this condition from continuing. transistor 2
A low base voltage of 0 is applied to the gate of FET 64, turning on the FET and pulling node 28 to the level of first voltage supply terminal 10. As a result, the circuit sub-branch 30
and 32 is activated, and the differential amplifier can be operated to protect the bias network from supply voltage fluctuations as described below. This circuit operates properly and draws current from transistor 26 unless FET 64 acts as a short circuit. FE
The effect of the presence of T64 is small, and VREF2 is lower than VBE26.
VREF1 does not change even if it decreases slightly because it decreases slightly.

As is well known, in a differential amplifier, even a slight difference between two input voltages can cause a large change in output. In operation, the potentials at nodes 44 and 46 serve as inputs to the differential amplifier defined above. Furthermore, as noted above, the proper operation of the network is determined by the circuit working at an operating point characterized by equal potentials at the two nodes. As shown in FIG. 6, the operating point of the bias network is a function of the value of the potential at node 28. Fluctuations in the supply voltage at the first voltage supply terminal 10 affect the potential voltage at node 28 and disturb the operation of the circuit, causing an imbalance in the potentials at nodes 44 and 46.

Assuming that transistors 50 and 52 are identical, equal currents will flow through the left and right branches of the differential amplifier when the potentials at nodes 44 and 46 are equal. For example, if the potential at node 46 becomes higher than the potential at node 44 in response to a change in the potential at node 28, the magnitude of the current flowing through transistors 50 and 52 will correspondingly change. That is, the current through transistor 52 increases relative to the current through transistor 50 as a result of the increased forward bias of npn transistor 52. As the current through transistor 52 increases, the current flowing through p, whose drain is attached to the collector of transistor 52,
The current through channel FET 56 increases.

The mirror configuration of FETs 54 and 56 provides a corresponding increase in the magnitude of the current through FET 54. The net result of the potential imbalance between nodes 44 and 46 is to increase the current flowing in the upper half of the left branch of the differential amplifier, where the current initially decreased due to the reduction in the forward bias of transistor 34. It is about falling.

As the current in the left branch (upper half) of the differential amplifier increases, the potential at node 62 is pulled up. node 62
In addition to the base of the npn transistor 20, the voltage value of
Base of npn transistor 26 and p-channel F
This will also be communicated to the gate of ET64.

Transistor 26 is arranged in an emitter follower configuration. That is, transistor 26
The potential at the emitter terminal of is always 0.7 volts lower than the potential at base 26 when transistor 26 is on. In this example, as the potential at node 62 increases, the potential at node 28, which is coupled to the emitter terminal of transistor 26, correspondingly increases. Referring to FIG. 6, this increase at node 28 equalizes the potentials at nodes 44 and 46, which is the desired operating point for this circuit. A corresponding analysis is applied to the operation of the differential amplifier when the voltage at node 44 is higher than the voltage at node 46 to reduce the potential at node 28, lowering the potential at node 44 with respect to the potential at node 46, and It will be readily appreciated that it is possible to drive the biasing network back to the required operating point in this manner.

The operation of a voltage generator incorporating the teachings of the present invention is illustrated in FIGS. 2(a), 2(b), 3(a), 3(b),
It is shown in FIG. 4(a) and FIG. 4(b). Figures 2(a) and 2(b) show the supply voltage at 25°C and V
is a curve of the relationship between REF1 and VREF2,
FIG. 3(a) and FIG. 3(b) show the results of simulation at 125°C. From these figures, it can be seen that for a 1 volt change in supply voltage, VREF1 and VREF2 each change by less than 10 mV. Compare the two graphs, ΔVREF1/ΔT=0.27mV
/°C, and ΔVREF2/ΔT=0.24 mV/°C.

FIGS. 4(a) and 4(b) combine to show the response of a voltage generator to pulses (ie, noise) superimposed on the supply voltage. It can be seen from the figure that the generator of one embodiment of the invention requires less than 2 ns to recover from perturbation. In the case of unbalance under high capacitive loads, a small capacitor can be coupled to high impedance node 62 to restore stability.

[0035]

It can thus be seen that the present invention improves bias circuitry for generating ECL reference voltages. By utilizing the teachings of the present invention, the required ECL reference voltage can be reliably obtained even when temperature and supply voltage are unstable. By adjusting and equalizing the voltages at a given node, good temperature characteristics of the bias network are achieved in addition to protecting the circuit from supply voltage fluctuations. Further, since this circuit does not include a PNP device, it is easy to manufacture and provides reliable operation. Although the invention has been described with reference to preferred embodiments thereof, it is not limited thereto. On the contrary, the invention is limited only insofar as defined by the claims, with all equivalents included within their scope.

[Brief explanation of drawings]

FIG. 1 is a schematic circuit diagram of a bias generation circuit according to an embodiment of the present invention.

[Figure 2(a)] VREF1 of the circuit in Figure 1 at 25°C
FIG.

[Figure 2(b)] VREF2 of the circuit in Figure 1 at 25°C
FIG.

FIG. 3(a) is a diagram showing the characteristics of VREF1 in FIG. 1 at 125°C.

FIG. 3(b) is a diagram showing the characteristics of VREF2 in FIG. 1 at 125°C.

4(a) is a diagram showing the response of VREF1 of the circuit of FIG. 1 to the pulse applied to the power supply shown in FIG. 4(b).

FIG. 4(b) is a diagram showing pulses applied to the power supply of the circuit of FIG. 1;

FIG. 5 is a circuit diagram of a conventional bias generation circuit.

FIG. 6 is a diagram showing voltage characteristics of a predetermined node of the bias circuit of FIG. 5;

Claims (6)

[Claims] Claim: 1. A bias circuit comprising (a) to (e) described below. (a) First transistor. An emitter of the first transistor is in electrical communication with a first power supply terminal, and a collector of the first transistor is in electrical communication with a common node. (b) Second transistor. The emitter of the second transistor is in electrical communication with the first power supply terminal, and the emitter of the second transistor is in electrical communication with the first power supply terminal.
The collectors of the transistors of are in electrical communication with the common node. (c) Third transistor. An emitter of the third transistor is in electrical communication with the common node, and a collector of the third transistor is in electrical communication with the second power supply terminal. (d) means for electrically communicating with the first, second and third transistors for inducing a reference voltage from the potentials of the first and second power supply terminals; (E) Differential amplification means having first and second inputs and an output, the first input receiving the collector potential of the first transistor, and the second input receiving the collector potential of the second transistor. A collector potential is received and the output is provided as a control signal to the third transistor. The control signal is the first control signal.
, the collector potentials of the second transistors are made equal, thereby acting to keep them constant with the reference voltage regardless of fluctuations in the potentials of the first and second power supply terminals. 2. The communicating means operates to induce two reference voltages, and the control signal induces both of the two reference voltages irrespective of potential fluctuations at the first and second power supply terminals. 2. The bias circuit according to claim 1, further comprising a constant-maintaining feature. 3. The differential amplification means has first and second input transistors, the first input transistor being in electrical communication with the collector of the first transistor, and the second input transistor being in electrical communication with the collector of the first transistor. 3. The bias circuit according to claim 1, wherein 2 is electrically connected to the collector of the second transistor. 4. A bias voltage generation method comprising steps (a) to (c) described below for adjusting a reference voltage provided by a bias circuit comprising steps (A) to (B) described below. (A) First and second transistors. The emitters of both the first and second transistors are in electrical communication with the first power supply terminal, and the collectors of both are in electrical communication with the common node. (B) Third transistor. An emitter of the third transistor is in electrical communication with the common node, and a collector is in electrical communication with the second power supply terminal. (a) Comparing the collector potentials of the first and second transistors. (b) inducing a control signal having a magnitude determined by the potential difference; (c) In order to equalize the collector potentials of the first and second transistors so that the reference voltage maintains a constant value regardless of fluctuations in the potentials of the first and second power supply terminals, the control signal is applying voltage to a third transistor; 5. The control signal is applied to the third transistor so that both the second reference voltage and the reference voltage are kept constant regardless of potential fluctuations at the first and second power supply terminals. 5. The bias voltage generation method according to claim 4, further comprising an additional step. 6. The bias voltage generation method according to claim 4, further comprising the step of applying the control signal to the third transistor so that the bias circuit operates at a quiescent point.