JP2011170455A - Reference voltage circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reference voltage circuit which is improved in temperature dependency. <P>SOLUTION: A reference voltage circuit 100 is provided with: current sources 30 sequentially and serially stacked between a power supply terminal and a ground terminal; and a first band gap reference circuit 10 and a second band gap reference circuit 20. The first band gap reference circuit 10 and the second band gap reference circuit 20 generate a first reference voltage Vref1 and a second reference voltage Vref2 having opposite temperature coefficients. The reference voltage circuit 100 outputs a sum voltage Vref(=Vref1+Vref2) of the first reference voltage Vref1 and the second reference voltage Vref2. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a reference voltage circuit.

  In a semiconductor integrated circuit, a bandgap reference voltage circuit (also referred to as a bandgap reference (BGR) circuit) is used for the purpose of generating a constant voltage independent of power supply voltage fluctuations and temperature fluctuations. Patent Document 1 discloses an example of a BGR circuit.

JP-A-5-088767 PAUL R. GRAY, PAUL J. HURST, STEPHEN H. LEWIS, ROBERT G. MEYER, ANALYSIS AND DESING OF ANALOG INTEGRATED CIRCUIT 4th Edition, JOHN WILEY & SONS, INC. Pp.229-336

  The BGR circuit described in Patent Document 1 can generate a reference voltage Vref that is stable with respect to the power supply voltage and temperature. However, the temperature coefficient δVref / δT is not completely zero, and may be insufficient depending on the application. is there.

  The present invention has been made in view of the above problems, and one of exemplary objects of an embodiment thereof is to provide a reference voltage circuit with improved temperature dependency.

  One embodiment of the present invention relates to a reference voltage circuit. The reference voltage circuit includes a first band gap reference circuit and a second band gap reference circuit that are stacked in series between a power supply terminal and a ground terminal. Each of the first band gap reference circuit and the second band gap reference circuit is configured to generate a first reference voltage and a second reference voltage having opposite temperature coefficients. The reference voltage circuit outputs the sum of the first and second reference voltages.

  According to this aspect, since the temperature characteristics of the first reference voltage and the second reference voltage cancel each other, a reference voltage having a small temperature dependency can be generated.

  The first and second band gap reference circuits may be configured using conductive bipolar transistors opposite to each other.

  One of the first and second bandgap reference circuits includes a first terminal, a second terminal, a first wider type current mirror circuit provided on the second terminal side, a first wider type current mirror circuit, and a first A first load circuit provided between the terminals and a first output for generating a first reference voltage between the first terminal and the second terminal according to a potential at a connection point between the first load circuit and the second transistor; And a circuit. The first Wideler type current mirror circuit may include a first transistor, a second transistor, and a first emitter resistor of an NPN type bipolar transistor. The other of the first and second bandgap reference circuits includes a third terminal, a fourth terminal, a second Wider type current mirror circuit provided on the third terminal side, a second Wider type current mirror circuit, and a fourth terminal. A second load circuit provided between the terminals, and a second output for generating a second reference voltage between the third terminal and the fourth terminal according to a potential at a connection point between the second load circuit and the fourth transistor. And a circuit. The second Wideler type current mirror circuit may include a third transistor, a fourth transistor, and a second emitter resistor of a PNP type bipolar transistor.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  The reference voltage circuit according to the present invention can improve temperature dependency.

It is a circuit diagram which shows the structure of the reference voltage circuit which concerns on embodiment. It is a figure which shows the temperature characteristic of the reference voltage circuit of FIG.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected in addition to the case where the member A and the member B are physically directly connected. It includes the case of being indirectly connected through another member that does not affect the connection state.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 1 is a circuit diagram showing a configuration of a reference voltage circuit 100 according to the embodiment. The reference voltage circuit 100 includes a first band gap reference circuit 10, a second band gap reference circuit 20, and a current source 30.

  The current source 30, the first band gap reference circuit 10, and the second band gap reference circuit 20 are stacked in series between a power supply terminal to which the power supply voltage Vcc is applied and a ground terminal to which the ground voltage Vgnd is applied. .

  The first band gap reference circuit 10 generates a first reference voltage Vref1 between both ends thereof. The second band gap reference circuit 20 generates a second reference voltage Vref2 between both ends thereof. Each of the first band gap reference circuit 10 and the second band gap reference circuit 20 is configured such that the first reference voltage Vref1 and the second reference voltage Vref2 have opposite temperature coefficients.

  The reference voltage circuit 100 outputs the sum (Vref1 + Vref2) of the first reference voltage Vref1 and the second reference voltage Vref2 as the reference voltage Vref. That is, the voltage between both ends of the first band gap reference circuit 10 and the second band gap reference circuit 20 is output.

  The above is the overall configuration of the reference voltage circuit 100. Next, specific configurations of the first band gap reference circuit 10 and the second band gap reference circuit 20 will be described. In order to generate the reference voltages Vref1 and Vref2 having opposite temperature coefficients, the first band gap reference circuit 10 and the second band gap reference circuit 20 are configured symmetrically using opposite conductive bipolar transistors. In other words, the first band gap reference circuit 10 and the second band gap reference circuit 20 are inverted from each other, and the PNP bipolar transistor (P channel MOSFET) and the NPN bipolar transistor (N channel MOSFET) are replaced. It has become.

  The first band gap reference circuit 10 includes a first terminal P 1, a second terminal P 2, a first Wideler type current mirror circuit 12, a first load circuit 14, and a first output circuit 16. The first band gap reference circuit 10 generates a first reference voltage Vref1 between the first terminal P1 and the second terminal P2.

  The first wideler type current mirror circuit 12 is provided on the second terminal P2 side. The first Wider type current mirror circuit 12 includes a first transistor Q1, a second transistor Q2, and a first emitter resistor Re1 which are NPN type bipolar transistors. The size ratio of the first transistor Q1 and the second transistor Q2 is 1: N.

  The first load circuit 14 is provided between the first wideler type current mirror circuit 12 and the second terminal P2. Specifically, the first load circuit 14 includes a first load resistor RL1 provided on the path of the first transistor Q1 and a second load resistor RL2 provided on the path of the second transistor Q2. An active load (current mirror circuit) may be used as the first load circuit 14.

The first output circuit 16 includes a first load circuit 14 of the first reference voltage Vref1 according to the potential _{V N1} at the connection point N1 of the second transistor Q2, is generated between the first terminal P1 and the second terminal P2.

The first output circuit 16 includes a fifth transistor Q5 to a ninth transistor Q9. The voltage V _{N1 at the} connection point _N1 is input to the base of the fifth transistor Q5 (first amplification transistor). The transistors Q7 to Q9 operate as a bias circuit that supplies a current proportional to the current flowing through the transistors Q1 and Q2 to the fifth transistor Q5. The sixth transistor (first output transistor) Q6 is a source follower circuit that receives the collector voltage of the fifth transistor Q5 at its base. The transistors Q6 to Q9 can be regarded as a buffer circuit that outputs a voltage (current) according to the state of the fifth transistor Q5. The configuration of the first output circuit 16 is not limited to that of FIG.

  The second bandgap reference circuit 20 includes a third terminal P3, a fourth terminal P4, a second Wideler type current mirror circuit 22, a second load circuit 24, and a second output circuit 26. The second band gap reference circuit 20 generates a second reference voltage Vref2 between the third terminal P3 and the fourth terminal P4.

  The second Wideler type current mirror circuit 22 is provided on the third terminal P3 side. The second Wideler type current mirror circuit 22 includes a third transistor Q3, a fourth transistor Q4, and a second emitter resistor Re2, which are PNP type bipolar transistors. The size ratio of the third transistor Q3 and the fourth transistor Q4 is 1: N.

  The second load circuit 24 is provided between the second Wideler type current mirror circuit 22 and the fourth terminal P4. Specifically, the second load circuit 24 includes a third load resistor RL3 provided on the path of the third transistor Q3, and a fourth load resistor RL4 provided on the path of the fourth transistor Q4. Note that an active load (current mirror circuit) may be used as the second load circuit 24.

The second output circuit 26 includes a first load circuit 14 and the second reference voltage Vref2 corresponding to the potential _{V N2} of the connection point N2 of the fourth transistors Q4, is generated between the third terminal P3 of the fourth terminal P4.

The second output circuit 26 includes a tenth transistor Q10 to a fourteenth transistor Q14. The voltage V _{N2 at the} connection point _N2 is input to the base of the tenth transistor (second amplification transistor) Q10. The transistors Q12 to Q14 operate as a bias circuit that supplies a current proportional to the current flowing through the transistors Q3 and Q4 to the tenth transistor Q10. The eleventh transistor (second output transistor) Q11 receives the voltage of the collector of the tenth transistor Q10 at its base. The transistors Q11 to Q14 can be regarded as a buffer circuit that outputs a voltage (current) according to the state of the tenth transistor Q10. The configuration of the second output circuit 26 is not limited to that shown in FIG.

  The above is the configuration of the reference voltage circuit 100. Next, the operation will be described. FIG. 2 is a diagram illustrating temperature characteristics of the reference voltage circuit 100 of FIG. The horizontal axis represents temperature, the upper stage shows the temperature characteristics of the first bandgap reference circuit 10, the middle stage shows the second bandgap reference circuit 20, and the lower stage shows the temperature characteristics of the reference voltage circuit 100 as a whole.

Focusing on the first band gap reference circuit 10, the current I _Q1 flowing in the first transistor Q1 is given by the following equation (1).
I _Q1 = V _TN · ln (N) / Re1 (1)
Here, V _TN indicates the thermal voltage of the NPN bipolar transistor Q1. Therefore, the first reference voltage Vref1 generated by the first bandgap reference circuit 10 is given by the following equation (2).
Vref1 = V _F + I _Q1 × RL1
= V _F + V _TN · ln (N) / Re1 × RL1 (2)
Here V _F is the forward voltage between the base emitter of the bipolar transistor Q1.

Subsequently, when focusing on the second band gap reference circuit 20, the current _IQ3 flowing through the third transistor Q3 is given by the following equation (3).
I _Q3 = V _TP · ln (N) / Re2 (3)
Here, _VTP represents the thermal voltage of the PNP bipolar transistor Q3. Therefore, the second reference voltage Vref2 generated by the second band gap reference circuit 20 is given by the following equation (4).
Vref2 = V _F + I _Q3 × RL3
= V _F + V _TP · ln (N) / Re2 × RL3 (4)
Here V _F is the forward voltage between the base emitter of the bipolar transistor Q3.

  The first reference voltage Vref1 given by Expression (2) has an upward convex temperature dependency. On the contrary, the second reference voltage Vref2 given by the equation (2) has a temperature dependency that is convex downward, as opposed to the first reference voltage Vref1. As a result, the reference voltage Vref obtained by adding the first reference voltage Vref1 and the second reference voltage Vref2 has a flat characteristic with respect to temperature.

  As described above, the reference voltage circuit 100 shown in FIG. 1 can generate the reference voltage Vref having a temperature dependency smaller than that of the related art.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications may exist in each of those constituent elements, each processing process, and a combination thereof. Hereinafter, such modifications will be described.

  The positions of the first band gap reference circuit 10 and the second band gap reference circuit 20 may be interchanged. The configurations of the first bandgap reference circuit 10 and the second bandgap reference circuit 20 are not limited to those shown in FIG. 1, and various modifications can be designed by those skilled in the art. For example, the bandgap reference circuit using bipolar transistors is used in the embodiment, but the same effect can be obtained by stacking two bandgap reference circuits using MOSFETs having different conductivity types.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 ... Reference voltage circuit, 30 ... Current source, 10 ... 1st band gap reference circuit, P1 ... 1st terminal, P2 ... 2nd terminal, 12 ... 1st wider type current mirror circuit, 14 ... 1st load circuit, 16 ... first output circuit, Q1 ... first transistor, Q2 ... second transistor, Re1 ... first emitter resistor, 20 ... second bandgap reference circuit, P3 ... third terminal, P4 ... fourth terminal, 22 ... second Wideler-type current mirror circuit, 24 ... second load circuit, 26 ... second output circuit, Q3 ... third transistor, Q4 ... fourth transistor, Re2 ... second emitter resistor, Vref ... reference voltage, Vref1 ... first reference voltage , Vref2... Second reference voltage.

Claims (4)

A first band gap reference circuit and a second band gap reference circuit stacked in series between a power supply terminal and a ground terminal in order;
The first band gap reference circuit and the second band gap reference circuit are each configured to generate a first reference voltage and a second reference voltage having opposite temperature coefficients,
A reference voltage circuit that outputs a sum of the first and second reference voltages.   2. The reference voltage circuit according to claim 1, wherein the first and second band gap reference circuits are configured using conductive bipolar transistors opposite to each other. 3. One of the first and second bandgap reference circuits is
A first terminal;
A second terminal;
A first wider current mirror circuit provided on the second terminal side, including a first transistor, a second transistor and a first emitter resistor of an NPN bipolar transistor;
A first load circuit provided between the first WIDLER type current mirror circuit and the first terminal;
A first output circuit for generating a first reference voltage between the first terminal and the second terminal according to a potential at a connection point between the first load circuit and the second transistor;
Including
The other of the first and second bandgap reference circuits is
A third terminal;
A fourth terminal;
Including a third transistor, a fourth transistor and a second emitter resistor of a PNP-type bipolar transistor, and a second Wideler type current mirror circuit provided on the third terminal side;
A second load circuit provided between the second wideler type current mirror circuit and the fourth terminal;
A second output circuit that generates a second reference voltage between the third terminal and the fourth terminal according to a potential at a connection point between the second load circuit and the fourth transistor;
The reference voltage circuit according to claim 2, further comprising: The first output circuit includes:
An NPN-type first amplifying transistor receiving at its base the potential of the connection point of the first load circuit and the second transistor;
A first bias circuit for supplying a current corresponding to a current flowing through the first and second transistors to the first amplifying transistor;
A first output transistor receiving at its base a collector voltage of the first amplifying transistor;
Including
The second output circuit includes:
A PNP-type second amplifying transistor receiving at its base the potential of the connection point of the second load circuit and the fourth transistor;
A second bias circuit for supplying a current corresponding to a current flowing through the third and fourth transistors to the second amplifying transistor;
A second output transistor receiving at its base a collector voltage of the second amplifying transistor;
The reference voltage circuit according to claim 3, comprising:

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