JPH0430061B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a bulk control method suitable for use in a data processing system in which a plurality of devices transfer data using the same bus.

[Technical background of the invention and its problems]

FIG. 1 shows an example of a general configuration of a data processing system. In the figure, a bus 9 includes a CPU 1, a main memory 8, a DMA controller 10, a floppy disk controller (hereinafter referred to as FDC) 3, a hard disk controller (hereinafter referred to as HDC) 6,
are commonly connected, and furthermore, a floppy disk device 2 is connected to the FDC 3 via a signal line 4,
A disk device 5 is connected to the HDC 6 via a signal line 7.

In such systems, e.g.
When trying to start up the HDC 6 while the HDC 3 is transferring data, the following two methods have conventionally been used.

Data transfer of FDC3 during data transfer is forcibly interrupted, and CPU1 transfers data to HDC via bus 9.
Start on 6.

Apart from bus 9, CPU1, FDC3, HDC6
A command/status information bus is used to connect the two devices so that even if one device is transferring data, the other device can be activated independently.

However, this method has the disadvantage that it requires a memory for data buffering of the interrupted FDC3, which increases the amount of hardware. This also applies when HDC 6 is interrupted. Further, according to the method (2), the wiring becomes complicated and the amount of hardware increases. This is a drawback that becomes more significant as the number of bulk devices increases.

[Purpose of the invention]

The present invention was made in view of the drawbacks of the conventional methods described above, and its purpose is to enable one device to activate another device while data is being transferred, and to enable simultaneous data transfer of multiple devices. The objective is to provide a bulk control scheme that allows for progress (not necessarily at the same time).

[Summary of the invention]

Therefore, in the present invention, a plurality of bulk devices including a CPU are commonly connected to a bus, and a series of operations from starting the device to completing data transfer is performed on the same bus. At least one of the devices has means for interrupting data transfer at predetermined intervals when using the bus and detecting and notifying this, and the means causes the CPU to
Other bulk devices can now be started by interrupting.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, a bulk floppy disk device and a disk device are taken as an example, but there is at least one device (such as a magnetic tape) that necessarily interrupts data transfer and another device (such as a magnetic tape). This is effective when simultaneously proceeding with data transfer for a set of data (in some cases, there may be a plurality of data transfers).

FIG. 2 shows a system adopting the method of the present invention, and the same components as in FIG. 1 are given the same reference numerals. In the figure, 14 is a byte counter, which has a function of detecting that the floppy disk device 2 is interrupted. Specifically, the byte counter 14 counts the number of times the DMA controller 10 outputs a 1-byte data transfer request acceptance signal to the FDC 3, and counts the number of times the DMA controller 10 outputs a 1-byte data transfer request acceptance signal to the FDC 3. When an acceptance signal corresponding to the amount of data (predetermined bytes) is detected, an interrupt signal 15 is output to the CPU 1. The CPU 1 uses this interrupt to check whether or not a work request to the disk device 5 has been sent from the host device, and if so, starts the HDC 6 via the bus 9.

Next, the operation of the system will be explained with reference to FIGS. 2 and 3. In the floppy disk format shown in FIG. 3, a data non-storage area (Gap) of a predetermined length is provided between one sector of data.
For details of this format, for example,
This information is disclosed in the "μPD765 FDC User's Manual" (NEC NEC Corporation) published on May 7th. Assume that at current time _T1 , a write command to the main memory 8 is issued from the floppy disk device 2. Then, the CPU 1 outputs a read command address to the FDC 3 via the bus 9. The FDC 3 performs a seek operation on the floppy disk device 2 to move the head to the address position. Data read by the read operation is taken into the FDC 3 from the signal line 4. The FDC 3 outputs a data transfer request to the DMA controller 10. Then, the DMA controller 10 checks whether a data transfer request has been output from another location. In this case, since it is not output, the DMA controller 10 outputs the acceptance signal to the FDC 3 and outputs the address information/write signal to the main memory 8. This results in
Data on bus 9 is stored in main memory 8.

This operation is repeated every 1 byte transfer, and 1
When the data transfer of the number of bytes for one sector is completed, the byte counter 14 outputs an interrupt signal 15 because the acceptance signal for the number of bytes of one sector has been given to the byte counter 14. At this time,
Assuming that a work instruction for the disk device 5 has been issued to the CPU 1 (indicated by ▽ in the figure), the CPU 1 outputs read command and address information from the bus 9 to the HDC 6. At this time, since the floppy disk device 2 is operating corresponding to the gap between sectors, the FDC 3 is connected to the bus 9.
is not used.

In this way, the disk device 5 is started,
The data taken into the HDC 6 is stored in the main memory 8 under the control of the DMA controller 10. On the other hand, when the gap is passed, the floppy disk device 2 also starts data read operation, and the FDC
Data will be imported into 3. Then,
Data now exists in each of FDC3 and HDC6, and the DMA controller 10
3. Continue the operation of sequentially storing data in the main memory 8 while accepting data transfer requests from the HDC 6. For example, the DMA controller 10
When a data transfer request is received from HDC 6 during 1 byte transfer from FDC 3 to main memory 8, the 1 byte is transferred from FDC 3 to main memory 8, and then from HDC 6 to main memory 8.
Transfer 1 byte of data to. Therefore, data taken into the FDC 3 or HDC 6 from the floppy disk device 2 or the disk device 5, respectively, is transferred to the main memory 2 within 1 byte transfer time from another device to the main memory 8 after a data transfer request.
will be transferred to. The data transfer from FDC3 and the data transfer from HDC6 in Figure 3 are as follows:
The data transfers are performed alternately at the timing indicated by the vertical lines within the pulses, and as a result, data transfers proceed simultaneously.
In this embodiment, the byte counter 14 is shown in FIG. 3 to always output an interrupt signal when a predetermined acceptance signal (the number of bytes for one sector) is input. This is not an essential requirement, and after outputting an interrupt signal once, it may be configured such that it does not operate until it is reset by the CPU 1, for example.

〔Effect of the invention〕

As described above, according to the present invention, one device can activate another device during data transfer and data transfers of a plurality of devices can proceed simultaneously, so that the throughput of the system is significantly reduced. Moreover,
It does not require any particularly complicated equipment to start up, and can be easily configured with just a byte counter. Furthermore, by forcibly interrupting the equipment or complicating the wiring,
Since it does not start up other devices, there is no need for increased hardware such as the need for buffer memory or multiple wiring lines, making it extremely efficient.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a system using the conventional method, Fig. 2 is a block diagram showing an example of a system using the method of the present invention, and Fig. 3 is a timing chart for explaining the operation of Fig. 2. It is. 1... CPU, 2... floppy disk device,
3...FDC, 5...Disk device, 6...HDC,
8... Main memory, 10... DMA controller, 14... Byte counter.

Claims (1)

[Claims] 1. In a data processing device in which a plurality of bulk devices are connected on the same bus and are formatted to store data divided into a plurality of blocks and have a predetermined non-storage area between each block, start the bulk device. means for transferring data of the bulk device started by the starting means; and means for recognizing that one block of data transfer has been completed by the transferring means and notifying the starting means; The activation means receives the notification and activates the other bulk device in response to a request for activation of another bulk device other than the activated bulk device, and the transfer means activates the other bulk device other than the activated bulk device. 1. A bulk control method characterized in that the data transfers of the bulk devices are performed in parallel, and the data transfers of the activated bulk devices are then switched and executed in parallel.