JPH04298887A - Memory circuit - Google Patents

Abstract

PURPOSE:To improve writing speed by providing plural column address selection signal lines and providing and FET connecting gates to the column address selection lines in the transfer gate circuit of a memory cell. CONSTITUTION:A row address selection signal 1 is given only to one row address selection signal line Ri, and a column address selection signal 1 is given only to one column address selection signal line Cj. Then FET Q11 and Q12 of transfer gate circuits G1 and G2 are turned on. FET Q13 of the circuit G1 and the FET Q14 of the circuit G2 are also turned on. By giving a pair of writing logic signal only to a pair of bit lines Bj and Bj' under such state, write-in to the memory cell can be performed. By giving the selection signal 1 to only one signal line Ri and one signal line Cj, the signal in a cell Mij can be read out. Thus, this construction need only small power consumption.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to memory circuits.

0002

2. Description of the Related Art Conventionally, the following memory circuit has been proposed with reference to FIGS. 8 and 9.

That is, a plurality of m×n memory cells M1
1, M12......M1n; M21, M22......M2n
;......Mm1, Mm2......Mmn, and a plurality of m row address selection signal lines R1, R2...Rm extending from the row address selection circuit 1, and a plurality of n pairs of mutually complementary bit lines B1 and B1', B2 and B2', . . . Bn and Bn'.

In this case, memory cells Mij (i=1, 2
......m; j=1, 2......n) includes a flip-flop circuit F having logic signal input/output terminals T1 and T2 and configured using field effect transistors; A transfer game having a logic signal input/output terminal T3 connected to the logic signal input/output terminal T1 and a logic signal input/output terminal T4 connected to the bit line Bj.
A transfer game having a logic signal input/output terminal T5 connected to a logic signal input/output terminal T2 of a flip-flop circuit F, and a logic signal input/output terminal T6 connected to a bit line Bj'. It is configured using a gate circuit G2.

Further, the flip-flop circuit F in the memory cell Mij includes field effect transistors Q1 and Q2 having p-channel type, field effect transistors Q3 and Q4 having n-channel type, and field effect transistor Q1. and Q3 are connected in series with the field effect transistor Q1 on the power supply end E1 side between the power supply terminal E1 where a high potential can be obtained and the power supply terminal E2 where a low potential can be obtained, and the field effect transistor Q2
and Q4 are connected in series between the power supply terminals E1 and E2 with the field effect transistor Q2 facing the power supply terminal E1 side. In addition, field effect transistors Q1 and Q
The gates of field effect transistors Q2 and Q4 and the connection midpoint of field effect transistors Q2 and Q4 are connected to the logic signal input/output terminal T2, and the gates of field effect transistors Q2 and Q4 and the connection midpoint of field effect transistors Q1 and Q3 are A point is connected to the logic signal input/output terminal T1.

Furthermore, the transfer gate circuit G1 in the memory cell Mij connects the gate to the row address selection signal line Ri and the logic signal input/output terminals T3 and T4.
It has an n-channel field effect transistor Q11 connected therebetween.

Further, the transfer gate circuit G2 in the memory cell Mij is an n-channel type ( (in the case of FIG. 2) or p-channel type (in the case of FIG. 3) field effect transistor Q12.

The above is the structure of a conventionally proposed memory circuit.

According to the memory circuit having such a configuration, only one row address selection signal line Ri among the m row address selection signal lines R1 to Rm is selected by the row address selection circuit 1. If the row address selection signal is given to the row address selection signal line Ri as a binary "1" signified by a high potential (in addition, the other (m-1) row addresses are selected). A row address selection signal is given to both signal lines as "0" in binary representation), and a transfer gate is applied only to n memory cells Mi1 to Min connected to the row address selection signal line Ri. Field effect transistor Q11 of transfer gate circuit G1 and field effect transistor Q of transfer gate circuit G2
12 are both turned on.

Therefore, from this state, the pair of write logic signals is sent to only the pair of bit lines Bj and Bj' as a binary "1" signal, which is defined by a high potential and a low potential, respectively. ” and “0” (note that the other (n-1) pairs of bit lines are both given a high potential, for example), the write logic signal for that pair is 0. Therefore, the pair of write logic signals applied to the bit lines Bj and Bj' can be written into the memory cell Mij.

Furthermore, n pairs of bit lines B1 and B1'
~Bj and Bj' are both given a high potential, for example, and only one row address selection signal line Ri is selected by the row address selection circuit 1, and the row address selection signal line Ri is assigned to the row address selection signal line Ri. If the signal is given as "1" in binary representation, n memory cells M
Transfer gate circuit G only for i1 to Min
Both field effect transistor Q11 of No. 1 and field effect transistor Q12 of transfer gate circuit G2 are turned on.

Therefore, in the flip-flop circuit F of the memory cell Mij, the pair of logic signals at the logic signal input/output terminals T1 and T2 are "1" and "0", respectively.
If the state is obtained by If the signal has been read out, and if the pair of logic signals at the logic signal input/output terminals T1 and T2 are "0" and "1", respectively, then the bit line Bj is A current flows through bit line Bj', but no current flows through bit line Bj', so by detecting this, the logic signal currently written in memory cell Mij can be read.

From the above, the conventional memory circuit shown in FIGS. 8 and 9 can function as a static type memory circuit.

[0014]

In the case of the conventional memory circuits shown in FIGS. 8 and 9, as mentioned above, the row address selection signal is displayed as "1" on the row address selection signal line Ri in binary form.
It was stated that when the logic signal written in the memory cell Mij can be read by obtaining ``, a current flows in the bit line Bj or Bj'. The field effect transistor Q11 of the transfer gate circuit G1 and the field effect transistor Q12 of the transfer gate circuit G2 of n memory cells Mi1 to Min connected to the address selection signal line Ri are both turned on. . Therefore, although it is sufficient for current to flow in only one bit line Bj or Bj', bit line B1 or B1' and bit line B2
Or Bn'...A current flows through the n bit lines of the bit line Bn or Bn' as a whole.

Therefore, the conventional memory circuits shown in FIGS. 8 and 9 have a disadvantage in that power consumption is large depending on the number of paired bit lines.

[0016] Therefore, the present invention is free from the above-mentioned drawbacks.
This paper aims to propose a new memory circuit.

[0017]

[Means for Solving the Problems] A memory circuit according to the first invention of the present application, as in the case of the conventional memory circuit described above with reference to FIGS. 8 and 9, has (i) a plurality of m×n memory cells M11; , M12...M1n; M21, M22......
M2n;......Mm1, Mm2......Mmn, (ii
) A plurality of m row address selection signal lines R1, R2...
...Rm, and (iii) n pairs of mutually complementary bit lines B1 and B1', B2 and B2'...
...Bn and Bn', and (iv) the memory cell Mij (i=1, 2...m; j=1, 2...
...n) includes (a) a flip-flop circuit having first and second logic signal input/output terminals and configured using field effect transistors, and (b) a first logic of the flip-flop circuit. a first transfer gate circuit having a third logic signal input/output terminal connected to the signal input/output terminal and a fourth logic signal input/output terminal connected to the bit line Bj; (c) a fifth logic signal input/output terminal connected to the second logic signal input/output terminal of the flip-flop circuit; and a sixth logic signal input/output terminal connected to the bit line Bj'. and a second transfer gate circuit.

However, in the memory circuit according to the first invention of the present application, in the memory circuit having such a configuration, (v) a plurality of n column address selection signal lines C1
, C2...Cn, and (vi) the first transfer game in the memory cell Mij.
A gate circuit is connected to the row address selection signal line Ri and the column address selection signal line Cj, respectively, and is connected in series between the third and fourth logic signal input/output terminals. (vii) the memory cell Mij
A second transfer gate circuit connects gates to the row address selection signal line Ri and column address selection signal line Cj, respectively, and is connected in series to the fifth and sixth logic circuits. It has third and fourth field effect transistors connected between the signal input and output terminals.

Further, the memory circuit according to the second invention of the present application has the following features in the memory circuit according to the first invention of the present application:
(viii) The flip-flop circuit in the memory cell Mij includes fifth and sixth field effect transistors having the first channel type, and a second field effect transistor, as in the case of the conventional memory circuit described above with reference to FIGS. and (ix) the flip-flop circuit of the memory cell Mij is similar to the conventional memory circuit described above with reference to FIGS. 8 and 9. (a) the fifth and seventh field effect transistors are connected in series between the first and second power supply terminals, with the fifth field effect transistor on the first power supply terminal side; (b) the sixth and eighth field effect transistors are connected in series between the first and second power supply terminals, with the sixth field effect transistor facing the first power supply terminal; connected, (c
) The gates of the fifth and seventh field effect transistors and the connection midpoints of the sixth and eighth field effect transistors are connected to the second logic signal input/output terminal, (d)
The gates of the sixth and eighth field effect transistors and the connection midpoints of the fifth and seventh field effect transistors are connected to the first logic signal input/output terminal.

However, in the memory circuit according to the second invention of the present application, in the memory circuit having such a configuration, (x) a plurality of n column write control signal lines W1, W
2......Wn, and (xi) the flip-flop circuit in the memory cell Mij further includes ninth and tenth field effect transistors having a second channel type, and (xii) ) In the flip-flop circuit in the memory cell Mij, (e) the ninth and tenth field effect transistors are connected in parallel with the fifth and sixth field effect transistors, and (f) the ninth and tenth field effect transistors are connected in parallel. The gate of the tenth field effect transistor is connected to the column write control signal line Wj.

[0021]

[Operation/Effect] According to the memory circuit according to the first invention of the present application, a binary row address selection signal is transmitted to only one row address selection signal line Ri among m row address selection signal lines R1 to Rm. "1" (or "0") is displayed and given.
In addition, the column address selection signal is given in binary form to only one column address selection signal line Cj among the n column address selection signal lines C1 to Cn.
” (or “0”) and give it (in addition, other (n-1
) The column address selection signal line for both books has a binary display of "0".
” (or “1”), n memory cells Mi1 to M1 connected to the row address selection signal line Ri
The first field effect transistor and the second transfer gate circuit of the first transfer gate circuit only in Min.
The third field effect transistors of the gate circuit are both turned on, and the second field effect transistor of the first transfer gate circuit and the second field effect transistor of the first transfer gate circuit only in m memory cells M1j to Mmj are turned on. The fourth field effect transistors of the transfer gate circuit are both turned on. Therefore, the first and second field effect transistors of the first transfer gate circuit and the third and fourth field effect transistors of the second transfer gate circuit in one memory cell Mij Both are turned on.

Therefore, from this state, a pair of write logic signals is applied to only the pair of bit lines Bj and Bj' to indicate binary values of ``1'' and ``0'' (or ``0'' and ``0''). 1
'') (note that the other (n-1) pairs of bit lines are both given a high potential, for example), then the write logic signal of that pair is given to the memory cell Mij The flip-flop of the memory cell Mij is transferred through the first and second field effect transistors of the first transfer gate circuit and the third and fourth field effect transistors of the second transfer gate circuit, respectively. Therefore, in the flip-flop circuit of the memory cell Mij, a pair of logic signals is applied to the first and second logic signal input/output terminals of the flip-flop circuit, respectively. The state obtained by the binary display corresponding to the binary display of the write logic signal is obtained,
Therefore, the pair of write logic signals applied to bit lines Bj and Bj' can be written into memory cell Mij.

Furthermore, n pairs of bit lines B1 and B1'
~Bj and Bj' are both given a high potential, for example, and m row address selection signal lines R1 ~Rm
A row address selection signal with a binary representation of "1" (or "0") is applied to only one of the row address selection signal lines Ri, and n column address selection signal lines C1
A column address selection signal is set to only one column address selection signal line Cj among Cn.
), then the first field effect transistor of the first transfer gate circuit and the third field effect transistor of the second transfer gate circuit in only n memory cells Mi1 to Min are given by In addition, the second field effect transistor of the first transfer gate circuit and the fourth electric field of the second transfer gate circuit only in m memory cells M1j to Mmj are turned on. Both effect transistors are turned on. Therefore, the first and second field effect transistors of the first transfer gate circuit and the third and fourth field effect transistors of the second transfer gate circuit in one memory cell Mij are
Both field effect transistors are turned on.

Therefore, in the flip-flop circuit of the memory cell Mij, the pair of logic signals at the first and second logic signal input/output terminals are "1" and "0", respectively.
(or "0" and "1"), no current flows through either of the bit lines Bj and Bj', but current flows through the other, so this can be detected. By doing so, the logic signal written in the memory cell Mij can be read out.

From the above, according to the memory circuit according to the first invention of the present application, the function as a static type memory circuit can be obtained as in the case of the conventional memory circuit described above with reference to FIGS. 8 and 9. Can be done.

However, in the case of the memory circuit according to the first invention of the present application, when it becomes possible to read out the logic signal written in the memory cell Mij, the difference between the pair of bit lines Bj and Bj' It has been stated that current flows in one of them but not in the other, but in this case, as mentioned above, if the current is connected to the row address selection signal line Ri and the column address selection signal line Cj. The first and second field effect transistors of the first transfer gate circuit and the third and fourth field effect transistors of the second transfer gate circuit of only one memory cell Mij are Both are simply turned on. Therefore, n pairs of bit lines B1 and B1' to Bn
Current flows only through one of the pair of bit lines Bj and Bj' in Bj and Bn', and therefore current flows only through one bit line as a whole.

Therefore, in the case of the memory circuit according to the first invention of the present application, the power consumption is only 1/n of that in the case of the conventional memory circuit described above with reference to FIGS. 8 and 9.

Furthermore, according to the memory circuit according to the second invention of the present application, in the memory circuit according to the first invention of the present application, a plurality of n column write control signal lines W1, W2
A flip-flop circuit in the memory cell Mij, which has Wn and has the same configuration as the conventional memory circuit described above in FIGS. 8 and 9, has its gate connected to the column write control signal line Wj. and the memory circuit according to the first invention of the present application, except that it has ninth and tenth field effect transistors having a second channel type and connected in parallel with the fifth and sixth field effect transistors. Since they have similar configurations, detailed explanations will be omitted, but the same effects as described above for the memory circuit according to the first invention of the present application can be obtained.

However, in the case of the memory circuit according to the second invention of the present application, if "1" (or "0") is given to the column write control signal line Wi in binary representation, the memory cell M
Since the ninth and tenth field effect transistors in the memory cell Mij can be turned off, the memory cell Mij
However, from the state in which the logic signal is stored as the content that keeps the fifth or sixth field effect transistor in the flip-flop circuit in the on state, a write logic signal is sent to the pair of bit lines Bj and Bj'. When writing it into the memory cell Mij, a column write control signal is given as "1" (or "0") in binary display to the column write control signal line Wj, and the ninth and tenth If the field effect transistor is turned off, if the write logic signal is to turn the fifth or sixth field effect transistor off, the ninth and tenth field effect transistors are turned off. If the fifth or sixth field effect transistor is connected in parallel with the fifth or sixth field effect transistor, the speed at which the fifth or sixth field effect transistor is turned off is not that of the ninth and tenth field effect transistor. faster than.

Therefore, according to the memory circuit according to the second aspect of the present invention, the function as a static type memory circuit can be obtained faster than the memory circuit according to the first aspect of the present invention.

[0031]

[Embodiment 1] Next, a first embodiment of a memory circuit according to the present invention will be described with reference to FIGS. 1 to 3.

In FIGS. 1 to 3, parts corresponding to those in FIGS. 8 and 9 are designated by the same reference numerals, and detailed description thereof will be omitted.

The memory circuit according to the present invention shown in FIGS. 1 to 3 has (i) a plurality of m×n memory cells M11, M, as in the case of the conventional memory circuit described above with reference to FIGS.
12...M1n;M21, M22...M2n;...
...Mm1, Mm2......Mmn, (ii) a plurality of m row address selection signal lines R1, R2...Rm,
(iii) A plurality of n pairs of mutually complementary bit lines B
1 and B1', B2 and B2'...Bn and Bn', and (iv) memory cell Mi
j (i=1, 2......m; j=1, 2......n) is (
a) A flip-flop circuit F having logic signal input/output terminals T1 and T2 and configured using field effect transistors, and (b) a logic signal connected to the logic signal input/output terminal T1 of the flip-flop circuit F. input/output terminal T3;
Logic signal input/output terminal T4 connected to bit line Bj
(c) a logic signal input/output terminal T5 connected to the logic signal input/output terminal T2 of the flip-flop circuit F; and a logic signal input/output terminal T5 connected to the bit line Bj'. It has a configuration including a transfer gate circuit G2 having an input/output terminal T6.

However, in the memory circuit according to the present invention shown in FIGS. 1 to 3, in the memory circuit having such a configuration, a plurality of n column address selection signal lines C1, C
2......Cn, and the transfer gate circuit G1 in the memory cell Mij connects the gate to the row address selection signal line Ri and the column address selection signal line Cj.
It has field effect transistors Q11 and Q13 connected to each other in series and connected to each other in series between logic signal input/output terminals T3 and T4.
The transfer gate circuit G2 in j has its gate connected to the row address selection signal line Ri and the column address selection signal line Cj, respectively, and are connected in series to each other between logic signal input/output terminals T5 and T6. It has connected field effect transistors Q12 and Q14.

Note that the flip-flop circuit F in the memory cell Mij includes field effect transistors Q1 and Q2 having p-channel type, and field-effect transistors Q2 having n-channel type, as in the case of the conventional memory circuit described above with reference to FIGS. 8 and 9. and field effect transistors Q3 and Q4 are connected in series between power supply terminals E1 and E2 with field effect transistor Q1 on the power supply terminal E1 side, and , field effect transistors Q2 and Q4 are connected between power supply terminals E1 and E2,
The field effect transistor Q2 is connected in series with the power supply terminal E1 side, and the gates of the field effect transistors Q1 and Q3 and the connection midpoint of the field effect transistors Q2 and Q4 are connected to the logic signal input/output terminal. Further, the gates of field effect transistors Q2 and Q4 and the connection midpoint of field effect transistors Q1 and Q3 are connected to logic signal input/output terminal T1.

The above is the configuration of the first embodiment of the memory circuit according to the present invention.

According to the memory circuit according to the present invention having such a configuration, m row address selection signal lines R1 to
Only one row address selection signal line Ri in Rm,
The row address selection signal is given as "1" (in the case of Figure 2) (or as "0" (in the case of Figure 3), which is interpreted as a low potential) in a binary format with a meaning given by a high potential. ,other(
m-1) A row address selection signal is given to each of the row address selection signal lines as a binary representation of "0" (in the case of FIG. 2) (or "1" (in the case of FIG. 3)), and n Only one column address selection signal line Cj among the column address selection signal lines C1 to Cn of the book displays the column address selection signal in binary display as "1" (in the case of FIG. 2) (or "0" (in the case of FIG. 3). in the case of)
) and give it (in addition, the other (n-1) column address selection signal lines are both binary-displayed as "0" (in the case of Figure 2)
(or "1" (in the case of FIG. 3)), the field effect transistor of the transfer gate circuit G1 in only n memory cells Mi1 to Min connected to the row address selection signal line Ri Q11 and the field effect transistor Q12 of the transfer gate circuit G2 are both turned on, and m memory cells M1j~
Only in Mmj, the field effect transistor Q13 of the transfer gate circuit G1 and the field effect transistor Q14 of the transfer gate circuit G2 are both turned on. Therefore, the field effect transistor Q of the transfer gate circuit G1 in one memory cell Mij
11 and Q13, and field effect transistors Q12 and Q14 of transfer gate circuit G2 are both turned on.

Therefore, from this state, a pair of write logic signals is now applied to only the pair of bit lines Bj and Bj', indicating binary values of ``1'' and ``0'' (or ``0'' and ``0''). 1
'') (note that the other (n-1) pairs of bit lines are both given a high potential, for example), then the write logic signal of that pair is given to the memory cell Mij Field effect transistors Q11 and Q13 of transfer gate circuit G1 and transfer
Field effect transistors Q12 and Q1 of gate circuit G2
4 to the logic signal input/output terminals T1 and T2 of the flip-flop circuit F of the memory cell Mij, respectively. A state is obtained in which each of the logic signals is expressed in a binary value corresponding to the binary expression taken by the pair of write logic signals,
Therefore, the pair of write logic signals applied to bit lines Bj and Bj' can be written into memory cell Mij.

In addition, n pairs of bit lines B1 and B1'
~Bj and Bj' are both given a high potential, for example, and m row address selection signal lines R1 ~Rm
A row address selection signal with a binary representation of "1" (or "0") is applied to only one of the row address selection signal lines Ri, and n column address selection signal lines C1
A column address selection signal is set to only one column address selection signal line Cj among Cn.
), both the field effect transistor Q11 of the transfer gate circuit G1 and the field effect transistor Q12 of the transfer gate circuit G2 in only n memory cells Mi1 to Min are turned on, and Transfer gate circuit G1 field effect transistor Q13 only in m memory cells M1j to Mmj
Both field effect transistor Q14 of transfer gate circuit G2 are turned on. Therefore, the transfer gate circuit G in one memory cell Mij
1 field effect transistors Q11 and Q13, and field effect transistor Q1 of transfer gate circuit G2.
2 and Q14 are both turned on.

Therefore, now, in the flip-flop circuit F of the memory cell Mij, the pair of logic signals at the logic signal input/output terminals T1 and T2 are "1" and "0", respectively.
(or "0" and "1"), no current flows through either of the bit lines Bj and Bj', but current flows through the other, so this can be detected. By doing so, the logic signal written in the memory cell Mij can be read out.

From the above, the memory circuit according to the present invention shown in FIGS. 1 to 3 can function as a static type memory circuit in the same way as the conventional memory circuit shown in FIGS. 8 and 9. can be obtained.

However, in the case of the memory circuit according to the present invention shown in FIGS. 1 to 3, when the logic signal written in the memory cell Mij can be read out, the pair of bit lines Bj and Bj ', current flows through one of them, but no current flows through the other; Transfer gate circuit G1 with only one memory cell Mij
field effect transistors Q11 and Q13 of the transfer gate circuit G2, and field effect transistor Q12 of the transfer gate circuit G2.
and Q14 are simply turned on. Therefore, n pairs of bit lines B1 and B1' to Bn and B
Current flows only through one of the pair of bit lines Bj and Bj' in n', and therefore, current flows only through one bit line as a whole.

Therefore, in the case of the memory circuit according to the present invention shown in FIGS. 1 to 3, the power consumption is only 1/n of that in the case of the conventional memory circuit described above in FIGS. 8 and 9.

[0044]

[Embodiment 2] Next, a second embodiment of the memory circuit according to the present invention will be described with reference to FIGS. 5 to 7.

In FIGS. 5 to 7, parts corresponding to those in FIGS. 1 to 3 are designated by the same reference numerals.

The memory circuit according to the invention shown in FIGS. 5-7 has a similar structure to the embodiment of the memory circuit according to the invention described above in FIGS. 1-3, except for the following.

That is, the flip-flop circuit F in the memory cell Mij has a plurality of ny column write control signal lines W1, W2, .
In the flip-flop circuit F in the memory cell Mij, the field effect transistor Q5 has p-channel type field effect transistors Q5 and Q6.
and Q6 are connected in parallel with field effect transistors Q1 and Q2, respectively, and field effect transistor Q5
The gates of Q6 and Q6 are connected to column write control signal line Wj.

The above is the configuration of the second embodiment of the memory circuit according to the present invention.

According to the memory circuit according to the present invention having such a configuration, in the memory circuit according to the present invention shown in FIGS. 1 to 3, a plurality of n column write control signal lines W1
, W2 . . . Wn and has the same configuration as the conventional memory circuit described above in FIGS. A memory circuit similar to the memory circuit according to the invention described above in FIGS. 1 to 3, except that it has field effect transistors Q5 and 6 having a p-channel type connected and connected in parallel with field effect transistors Q1 and Q2. Since it has a structure, detailed explanation will be omitted, but
The same effects as described above for the memory circuit according to the present invention described above with reference to FIGS. 1 to 3 can be obtained.

However, in the case of the memory circuit according to the present invention shown in FIGS. 4 to 6, if the column write control signal line Wi is given as "1" (or "0") in binary representation, the electric field in the memory cell Mij is Since the effect transistors Q5 and Q6 can be turned off, the memory cell Mij stores a logic signal that maintains the on state of the field effect transistors Q1 and Q2 in the flip-flop circuit F. When a write logic signal is given to the pair of bit lines Bj and Bj' and written into the memory cell Mij, the column write control signal is given to the column write control signal line Wj in binary form as " 1 (or 0) to turn field effect transistors Q5 and Q6 off, if the write logic signal is to turn the field effect transistors off, the field effect Since the transistors Q5 and Q6 are connected in parallel with the field effect transistors Q1 and Q2, the speed at which the field effect transistors Q1 or Q2 are turned off is
This is faster than when the field effect transistors Q5 and Q6 are not included.

Therefore, according to the memory circuit according to the present invention shown in FIGS. 4 to 6, the function as a static type memory circuit can be obtained faster than the memory circuit according to the present invention described above in FIGS. 1 to 3. be able to.

[0052] In the above description, only a few embodiments of the present invention have been shown, and in the above embodiments, the p-channel type is replaced with the n-channel type, and the n-channel type is replaced with the p-channel type. You can also
Various modifications and changes may be made without departing from the spirit of the invention.

[Brief explanation of drawings]

FIG. 1 is a systematic connection diagram showing a first embodiment of a memory circuit according to the present invention.

FIG. 2 is a connection diagram showing an embodiment of a memory cell used in the memory circuit according to the present invention shown in FIG. 1;

FIG. 3 is a connection diagram showing an embodiment of another memory cell used in the memory circuit according to the invention shown in FIG. 1;

FIG. 4 is a diagram illustrating the relationship between power consumption and the number of memory cells in comparison with that of a conventional semiconductor laser, in order to explain the effects of the memory circuit according to the present invention.

FIG. 5 is a systematic connection diagram showing a second embodiment of the memory circuit according to the invention.

6 is a connection diagram showing an embodiment of a memory cell used in the memory circuit according to the present invention shown in FIG. 5; FIG.

FIG. 7 is a connection diagram showing another embodiment of a memory cell used in the memory circuit according to the present invention shown in FIG. 1;

FIG. 8 is a systematic connection diagram showing a conventional memory circuit.

FIG. 9 is a connection diagram showing memory cells used in the conventional memory circuit shown in FIG. 8;

[Explanation of symbols]

1 Row address selection circuit 2
Column address selection circuit B1
~Bn Bit line B1 '~Bn ' Bit line C1 ~Cn Column address selection signal line E1
, E2 power supply terminal

Claims (2)

[Claims] [Claim 1] A plurality of m×n memory cells M11, M
12...M1n;M21, M22...M2n;...
...Mm1, Mm2...Mmn, a plurality of m row address selection signal lines R1, R2...Rm, and a plurality of n pairs of mutually complementary bit lines B1, B1', B
2 and B2 ′……Bn and Bn ′ and plural n
Book column address selection signal lines C1, C2......Cn
and the memory cell Mij (i=1, 2......m
; j = 1, 2...n), (a) a flip-flop circuit having first and second logic signal input/output terminals and configured using field effect transistors; a third logic signal input/output terminal connected to the first logic signal input/output terminal of the pull circuit, and the bit line Bj
(c) a fifth transfer gate circuit having a fourth logic signal input/output terminal connected to the second logic signal input/output terminal of the flip-flop circuit; the logic signal input/output terminal of and the bit line Bj
and a second transfer gate circuit having a sixth logic signal input/output terminal connected to the gate. first and second gates connected to the row address selection signal line Ri and column address selection signal line Cj, respectively, and connected in series between the third and fourth logic signal input/output terminals. A second transfer gate circuit in the memory cell Mij has two field effect transistors, the gates of which are connected to the row address selection signal line Ri and the column address selection signal line Cj, respectively, and which are connected to each other. A memory circuit comprising third and fourth field effect transistors connected in series between the fifth and sixth logic signal input/output terminals. 2. The memory circuit according to claim 1,
A plurality of n column write control signal lines W1, W2...Wn
and the flip-flop circuit in the memory cell Mij includes fifth and sixth field effect transistors having a first channel type, and seventh, eighth, ninth and tenth field effect transistors having a second channel type. In the flip-flop circuit of the memory cell Mij, (a) the fifth and seventh field effect transistors are arranged between the first and second power supply terminals to (b) the sixth and eighth field effect transistors are connected between the first and second power supply terminals;
(c) the ninth field effect transistor is connected in series with the sixth field effect transistor facing the first power supply end;
and a tenth field effect transistor connected in parallel with the fifth and sixth field effect transistors, (d)
(e) the gates of the fifth and seventh field effect transistors and the connection midpoints of the sixth and eighth field effect transistors are connected to the second logic signal input/output terminal; and the gate of the eighth field effect transistor and the connection midpoint of the fifth and seventh field effect transistors,
(f) the gates of the ninth and tenth field effect transistors are connected to the column write control signal line Wj; circuit.