JPH07192473A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent a malfunction due to capacitance among bit lines at the time of writing out data and to suppress a consuming current by connecting pull-up transistors(Trs) to bit line pairs adjacent to adjacent addresses among bit line pairs at the time of reading out data from memory cells. CONSTITUTION:This semiconductor storage device includes plural bit line pairs BB04, the inverse of BT04, BB11 the inverse of BT11, BB12, the inverse of BT12, BB13, the inverse of BT13, BB14 the inverse of BT14, BB21, the inverse of BT21 and plural word lines W0, W1,... and plural memory cells 3 arrange at positions corresponding. intersecting position of them. Further, the device includes plural crossing circuits 1 and plural pull-up NMOS transistors Tr2. At the time of reading out data from cells 3, since potentials of bit lines of the higher sides of a potential arc secured by crossing circuits 1 and pull-up NMOS transistors Tr 2 connected to bit line pairs adjacent to adjacent addresses among bit line pairs of the same address of more than at least three pairs, the malfunction is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.

[0002]

2. Description of the Related Art One example of a conventional semiconductor memory device is shown in FIG. The conventional example of FIG. 5 is an example showing the structure of a bit line pair of a static RAM. In FIG. 5, bit line pair B
B ₀₄ / BT ₀₄ , BB ₁₁ / BT ₁₁ , BB ₁₂ / BT ₁₂ , BB
₁₃ / BT ₁₃ , BB ₁₄ / BT ₁₄ , BB ₂₁ / BT ₂₁ , ... include a plurality of transfer NMOS transistors and driver NMOS transistors whose gate inputs are the potential levels of the word lines W ₀ , W ₁ ,. Memory cell 3
(See FIG. 7) are each connected. For all these bit line pairs, the drain and gate are connected to the power supply voltage V in order to guarantee the bit line on the higher potential side of the bit line.
_The pull-up NMOS transistor 2 which is set to _CC , the source is the bit line input, and is always ON,
Each is provided. NMOS for this pull-up
The potential level of each bit line is held at the "H" level by the transistor 2. However, in operation, when the bit line is set to the “L” level, the power supply voltage V _CC
Transfer NMOS of pull-up NMOS transistor 2, bit line and read memory cell 3
A current flows into the ground through the transistors 7 and 12 and the driver NMOS transistors 9 and 10 (see FIG. 7). Further, for the selected bit line, current also flows to the write driver. Therefore, during operation, the power supply current I _CC tends to increase and the current consumption increases.

The power supply current value I _CC which is a problem of the above conventional example
As another example of the conventional semiconductor memory device in which the current consumption due to the increase of the current is suppressed, an example in which the structure of the bit line pair of the static RAM is improved is shown in FIG. As shown in FIG. 6, in this conventional example, the bit line pair BB ₀₄ / BT ₀₄ ,
BB ₁₁ / BT ₁₁ , BB ₁₂ / BT ₁₂ , BB ₁₃ / BT ₁₃ , B
B ₁₄ / BT ₁₄ , BB ₂₁ / BT ₂₁ , ... To the word line W
A plurality of memory cells 3 each including a transfer NMOS transistor and a driver NMOS transistor whose gate inputs are the potential levels of ₀ , W ₁ , ... Are connected as constituent elements of the memory cell array. The states of such components are the same as in the case of the conventional example shown in FIG. 5 described above. Further, in order to guarantee each bit line pair, the bit line on the high potential side during reading, The stacking circuit 1 is connected.

FIG. 7 is a diagram showing a portion including bit line pairs BB ₁₄ / BT ₁₄ and BB ₂₁ / BT ₂₁ and word lines W ₀ and W ₁ in the second conventional example. As shown in FIG. 3, the plow-through circuit 1 is composed of PMOS transistors 5 and 6. As shown in the memory cell 3a, each of the memory cells 3a to 3d is composed of a NMOS transistor 7 and a NMOS transistor 8, a NMOS transistor 9 and 10, and a resistor 11 and 12, respectively. In FIG. 7, word line W0 Becomes "H" level and the data "0" of the memory cell 3a is read,
The potential level of the bit line BT ₁₄ gradually decreases from the power supply voltage V _CC , and the potential level corresponds to the bit line BB ₁₄ side and the level at which the PMOS transistor 5 included in the plucking circuit 1 is turned on ( V _CC + V _tb : V _tb is PM
When it drops to the threshold voltage of the OS transistor 5), the potential of the bit line BB ₁₄ is guaranteed at the V _CC level via the PMOS transistor 5. Therefore, by providing this pulling circuit 1, the pull-up NMO
It is not necessary to use the S transistor 2, and the pull-up NMOS transistor 2 is eliminated in this conventional example. As a result, the current amount of I _CC from the power supply corresponding to that amount can be suppressed. However, on the other hand, the following problems occur.

Now, as shown in FIG. 7, the address Y ₁
Bit line pair BB ₁₄ / B of I / O terminal I / O ₄ corresponding to
And T _14, in the case where the input-output terminal I / 0 ₁ bit line pair BB ₂₁ / BT ₂₁ corresponding to the address Y ₂ is adjacent to the memory cell 3c of the address Y _2, the timing shown in FIG. 4 The time transition of each potential when the data “0” is written will be described. First, time t ₀
At WEB, the WEB falls to enter the write state, the potential of the word line W ₀ of the selected bit rises, and the transfer NMOS transistors 7 and 8 in the memory cell 3c are turned on. At this time, since the inverted data “1” of the write data is input, the potential levels of the bit lines BT ₂₁ and BB _{21 become} the “H” level and the “L” level, respectively, with respect to the memory cell 3c. Data is written.

Next, at time t ₁ , write data “0” is input, and the levels of the bit lines BT ₂₁ and BB ₂₁ corresponding to the memory cell 3c become “L” level and “H” level, respectively. Data “0”
Is written. On the other hand, the adjacent bit line BT ₁₄
And BB ₁₄ are precharged at time t ₀ (bit line B
From the state where both T ₁₄ and BB ₁₄ are V _CC ),
Transfer NMOS transistors 7 and 8 are ON
The data "0" held in the memory cell 3a on the selected word being read is read out, and the potential of the bit line BT ₁₄ gradually decreases as shown in FIG. _{In 2} , the potential level of bit line BT ₁₄ drops to the ground potential level. At time t ₂ , that is, after the state where the adjacent bit line decreases to the ground potential level, as shown in FIG. 4C, at time t ₁ ,
When the write data is inverted from the inverted data to the positive data “0”, as shown in FIG. 4D, the bit line B
The potential level of T ₂₁ drops from the V _CC level to the ground potential level. At this time, the bit line BT ₁₄ adjacent to the ground potential level is connected to the bit line BT ₂₁ by the capacitance 4 between the bit lines, which causes the bit line BT ₁₄ to be coupled. The potential level of line BT ₂₁ is
As shown in FIG. 4E, the state is such that the potential level (−ΔV) is lower than the ground potential level.

On the other hand, the capacity between the bit lines tends to increase in the process of further increasing the degree of integration with the semiconductor memory device and further reducing the bit line pitch. 3 μm, bit line length 4 mm
In this case, the line capacitance reaches 0.25 pF. As a result, the influence of the capacitive coupling between lines becomes large, and, for example, in the above case, the potential drop in the bit line BT ₁₄ is further increased, and the potential drop becomes a non-correspondence on the corresponding bit line BT _14. The transfer N included in the memory cell 3b corresponding to the selected bit
The potential at which the MOS transistor 8 is turned on (GND-V _tt :
When V _tt falls to V _tn of the NMOS transistor 8, there is a problem that data in the memory cell 3b is destroyed and malfunction occurs.

[0008]

The above-mentioned conventional semiconductor memory device has a drawback that the current value of I _CC flowing from the power supply into the semiconductor memory device increases during operation, and this drawback is also disadvantageous. The excluded semiconductor memory device has a drawback that malfunction occurs due to coupling capacitance between bit lines.

[0009]

A semiconductor memory device of the present invention is a memory formed by a plurality of bit line pairs and a plurality of word lines, and a plurality of memory cells arranged at positions corresponding to the intersections thereof. A cell array, and a plurality of crossing circuits each connected to the bit line pair in order to guarantee the potential of the bit line on the higher potential side of the corresponding bit line pair when reading data from the memory cell. Of the three or more pairs of bit lines having the same address, at least a plurality of pull-up transistors connected only to adjacent bit lines and adjacent bit line pairs are provided. It has a feature.

The pull-up transistor may be formed so as to have the pull-up function only during a data write cycle, or the pull-up transistor may be included in the bit line pair. It may be formed so as to be connected only to the bit line on one side adjacent to the adjacent address.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, in this embodiment, a plurality of bit line pairs BB ₀₄ / BT ₀₄ , BB ₁₁ / BT ₁₁ , BB _{12 are used.}
/ BT ₁₂ , BB ₁₃ / BT ₁₃ , BB ₁₄ / BT ₁₄ , BB ₂₁ /
BT ₂₁ , ... And a plurality of word lines W ₀ , W ₁ ,.
Corresponding to, a plurality of plucking circuits 1, a plurality of pull-up NMOS transistors 2, and a plurality of memory cells 3 corresponding to each bit line pair and word line.

In FIG. 1, in the present embodiment, an NMOS transistor which is always set to an ON state is provided only in a pair of bit lines adjacent to an adjacent address (except when the GND and V _CC wirings are sandwiched). , Pull-up NMO
It is provided as the S transistor 2. Also, FIG.
FIG. 3 is a diagram showing a portion including bit line pairs BB ₁₄ / BT ₁₄ and BB ₂₁ / BT ₂₁ and word lines W ₀ and W _{1 in the} embodiment, and as shown in FIG. The circuit 1 is composed of PMOS transistors 5 and 6, and the memory cells 3a to 3d have N transfer transistors.
MOS transistors 7 and 8 and driver NMOS
It is composed of transistors 9 and 10 and resistors 11 and 12. In this case, since the bit line pair BB ₁₄ / BT ₁₄ and BB ₂₁ / BT ₂₁ are a bit line pair adjacent to the adjacent address, the pull-up NMOS transistor 2 is connected to each bit line. Has been done.

Next, the write operation of this embodiment will be described with reference to FIGS. When the write state is set at time t ₀ , the word line W ₀ of the selected bit is set to the “H” level, and the transfer NMOS transistors in the memory cells 3a and 3c are turned on. At this time, since the inverted data “1” of the write data “0” has been input, the potential levels of the bit lines BT ₂₁ and BB ₂₁ become “H” level and “L” level, respectively, and the data write Done.
On the other hand, the input / output terminal I / O at the adjacent address Y _1
In the bit line pair BB ₁₄ / BT ₁₄ of 4, the data “0” held in the memory cell 3a on the selected word is read to the bit line, and the potential of the bit line BT ₁₄ gradually decreases. , By this, the potential level of the bit line BT ₁₄ becomes
When lower than V _t of the NMOS transistor 5 of the cross-coupled circuit 1 becomes _{(<V CC -V tb),} PMOS transistor 5 becomes a state ON, the potential of the bit line BB ₁₄ is guaranteed to V _CC level. The above operation is the same as in the case of the conventional example described above.

After that, at time t ₂ , the potential level of the bit line BT ₁₄ changes via the operation of the pull-up NMOS transistor 2 to the pull-up NMOS transistor 2 and the transfer NMOS of the memory cell 3a.
The potential level set by the resistance division with the transistor is lowered to a potential level obtained by adding ΔV _P. This Δ
The value of V _P is preferably set to a potential of about 0.2V. Next, at time t ₁ , when the write data is inverted from the inverted data “1” to the positive data “0”, the potential of the bit line BT ₂₁ drops from V _CC to GND. At this time point, the potential level of the adjacent "L" level bit line BT ₁₄ is coupled to the bit line BT ₂₁ by the capacitance 4 and decreases by the potential ΔV.
However, the potential level of the bit line BT ₁₄ in case (GND + ΔV _P -ΔV), since (GND-V _tt) not drop below, by the word line of the bit line BT _14,
The situation that the data in the unselected memory cell 3a is destroyed does not occur.

In the case of the present embodiment, the pull-up NMOS transistor 2 is connected to both the bit line pair (BT _mn / BB _mn ) in consideration of the influence of the load line unbalance on the read operation. However, the pull-up NMOS transistor 2 may be provided only on one of the bit lines adjacent to the adjacent address as long as it is a measure for preventing the influence of the capacitive coupling between the bit lines. . Further, by selectively providing the pull-up NMOS transistor 2 only for the required bit line, the current value of the operating current I _CC can be suppressed to a smaller value. That is, as shown in FIG. 1, at the address Y ₁ , the input / output terminals I / O ₁ and I / O ₁
When O ₂ , I / O ₂ and I / O ₄ are arranged in a lump, bit line pairs BT ₁₁ / BB ₁₁ and BT corresponding to the input / output terminals I / O ₁ and I / O _{4 14} / BB ₁₄
It is only necessary to provide the pull-up NMOS transistor 2 for the above, which reduces the required number of pull-up NMOS transistors 2 in the present embodiment by half as compared with the conventional semiconductor memory device.

Next, a second embodiment of the present invention will be described.

FIG. 3 is a circuit diagram showing the configuration of the pull-up transistor circuit in this embodiment, which is a bit line pair B.
Only the pull-up circuits corresponding to B ₁₄ / BT ₁₄ and the bit line pair BB ₂₁ / BT ₂₁ are partially shown. In addition,
The overall configuration of this embodiment is similar to that of the first embodiment. As shown in FIG. 3, in the pull-up transistor circuit of this embodiment, the power supply voltage V
_CC is supplied and the drains are bit lines BB ₁₄ and
PMOS transistors 13, 14, 15 and 16 connected to BT ₁₄ , BB ₂₁ and BT ₂₁ and their PM
Inverters 17 and 18 for supplying a gate input to the OS transistor.

In FIG. 3, the WEB signal, which is at the "L" level at the time of writing, is the "L" level signal through the two-stage inverters (requiring an even number of stages) by the inverters 17 and 18. , To the gates of the PMOS transistors 13, 14, 15 and 16. Note that these PMOS transistors 13, 1
When NMOS transistors are used instead of 4, 15 and 16, it is necessary to cascade an odd number of inverters for the WEB signal input. As in the case of the first embodiment, this pull-up transistor circuit is
By providing only for the bit line pair adjacent to the adjacent address, the "L" level WEB is provided only at the time of writing when a malfunction occurs due to the destruction of the memory cell.
Receiving a signal input, the PMOS transistors 13 and 1
4, 15, and 16 are in the ON state, which causes
It is possible to prevent the bald power supply voltage V _{CC from} being supplied to the bit lines BB ₁₄ , BT ₁₄ , BB ₂₁ and BT ₂₁ to lower each bit line to the GND level. Further, in the case of the present embodiment, an increase in current at the time of reading is avoided, so the average current value obtained by summing up the current consumption I _CC from the power supply at the time of operation including writing and reading is set to the above-mentioned first embodiment. There is an advantage that it can be suppressed to a value smaller than the case of the example.

[0020]

As described above, according to the present invention, it is possible to prevent a malfunction caused by destroying cell data on an adjacent bit line at the time of writing data to a memory cell and increase a write voltage operation margin. In addition to that, there is an effect that the operating current can be suppressed and the current consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a partial circuit in the first embodiment.

FIG. 3 is a diagram showing a pull-up transistor circuit according to a second embodiment.

FIG. 4 is a timing chart during a write operation.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a block diagram showing another conventional example.

FIG. 7 is a diagram showing a partial circuit of a conventional example.

[Explanation of symbols]

 1 plucking circuit 2 pull-up NMOS transistor 3 memory cell 4 capacitance 5, 6, 13-16 PMOS transistor 7-10 NMOS transistor 11, 12 resistor 17, 18 inverter

Claims (3)

[Claims] 1. A memory cell array formed by a plurality of bit line pairs, a plurality of word lines, and a plurality of memory cells arranged at positions corresponding to these intersections, and when reading data from the memory cells, In order to guarantee the potential of the bit line on the higher potential side of the corresponding bit line pair, a plurality of crossing circuits connected to the bit line pair and at least three or more bit line pairs of the same address 2. A semiconductor memory device, comprising: at least a plurality of pull-up transistors connected only to bit line pairs adjacent to each other and adjacent addresses. 2. The semiconductor memory device according to claim 1, wherein the pull-up transistor has the pull-up function only during a data write cycle. 3. The pull-up transistor according to claim 1, wherein the pull-up transistor is connected only to a bit line on one side of the bit line pair that is adjacent to an adjacent address. Semiconductor memory device.