JPH04296963A - Multi-processor system - Google Patents

Abstract

PURPOSE:To selectively apply the optimum communication system according to the state of a multi-processor system by using at least two processors per one process, carrying out the inter-process communication(IPC) of different systems for each processor, and at the same time applying an IPC that is first through with the communication. CONSTITUTION:In an IPC system two processors 2 are used for transfer of the same date and applied to the 1st and 2nd processes 4 and 5 respectively. Then the IPC is carried out between both processes 4 and 5. In the 1st process 4, one of both processors 2 carries out the IPC of a shared memory system and at the same time the IPC of a communication circuit system is carried out by the other processor 2. Then the data that could be communicated earlier are adopted. So is with the 2nd process 5.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system that enables interprocess communication.

0002

[Background Art] Modern computers are required to have increasingly higher processing power, and as part of this, one process is performed by multiple processes under the control of one operating system (OS). A multiprocessor system is used in which multiple processors can be jointly executed.

[0003] In such a multiprocessor system, it is necessary to exchange data for interaction between processes, and Inter Process Communication is used as a means for this purpose.
ation, hereinafter abbreviated as IPC. )It has been known.

[0004] In this case, there are two main types of IPC methods: one is a shared memory method that uses a shared memory, and the other is a communication line method that uses a communication line. It is. Here, in the former shared memory method, each processor shares a certain area of the shared memory,
The necessary data is exchanged by reading and writing data to that area.The latter communication line method directly exchanges data in the form of messages to the other party without using shared memory. This is what we do.

[0005] In current multiprocessor systems, IPC is realized by adopting either the shared memory method or the communication line method, but when comparing these shared memory methods and the communication line method, Generally speaking, the former shared memory method is said to be capable of faster communication than the communication line method.

[0006] As an example, even in systems that have already been commercialized, Encore's Multimux (shared memory method) allows communication for data exchange in approximately 1 microsecond, whereas Intel's Hyper Cube (communication line system) requires several hundred microseconds.

However, the shared memory method is not without its problems, and as the number of processors composing a multiprocessor system increases and the number of IPC lines increases,
Simultaneous access to a predetermined area of the shared memory becomes a bottleneck, significantly slowing down the communication speed for data exchange.

[0008] Therefore, whether or not these shared memory systems and communication line systems are capable of faster and more efficient communication depends largely on the configuration of the multiprocessor system itself and the load placed on the system.

By the way, in current multiprocessor systems, either a shared memory method or a communication line method is fixedly adopted as a communication method for realizing IPC. For this reason, for example, if the shared memory method is fixedly adopted, in the situation described above, even if the communication line method is considered advantageous, the disadvantageous shared memory method must be used as is. On the other hand, even if a communication line method is fixedly adopted, even if a shared memory method is considered to be advantageous, a disadvantageous communication line method must be used as is, which does not suit the current situation. Due to the disadvantageous communication method, inconveniences such as significantly slowing down of communication speed for data exchange may occur.

0010

[Problem to be Solved by the Invention] As described above, in conventional multiprocessor systems, the communication method for realizing IPC is fixedly set, so a disadvantageous communication method is applied as is depending on the system situation. Therefore, using a communication method that is not suitable for the current situation has caused inconveniences such as significantly slowing down the communication speed for data exchange.

The present invention has been made in view of the above circumstances, and it is possible to selectively adopt an optimal communication method depending on the system situation, avoid delays in communication speed for data exchange, The purpose of the present invention is to provide a multiprocessor system that can realize rational and high-speed IPC.

0012

[Means for Solving the Problems] A multiprocessor system of the present invention has a plurality of processors, uses at least two processors for one process, and uses different methods of interprocess communication for each processor. The configuration is such that the inter-process communication method that completes communication first is used.

[0013]

[Operation] In the present invention, when two processors are used in one process and IPC with another process is required,
After both processes access the same data at the same time, one processor executes IPC in a shared memory manner, and in parallel, the other processor executes IPC in a communication line manner, and some of these IPC executions , IP first
By adopting the results of successful execution of C, it becomes possible to selectively adopt the optimal communication method depending on the system situation.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of the same embodiment. In the figure, 1 is a bus, to which a plurality of processors (CPUs) 2 are connected as well as a main storage section 3 including a shared memory area 31.

In this case, in the IPC system of the same embodiment, two processors 2 are used to transfer the same data.
two processors 2 to the first process (sending process) 4
, and two other processors 2 are applied to the second process (receiving process) 5, respectively, and IPC is executed between the first process 4 and the second process 5.

Regarding the first process 4, one processor 2 executes IPC using the shared memory method, and at the same time, the other processor 2 executes IPC using the communication line method, and the data that can be communicated faster is transferred. The company is starting to adopt the following. The same applies to the second process 5. Next, the operation of the embodiment configured as above will be explained. First, regarding the first process (transmission process) 4, processing is executed according to the flowchart of FIG.

In this case, the flowchart starts when IPC with the second process 5 becomes necessary during the processing of the first process 4. First, at the start of IPC, a conflict flag to be used from now on is reset to OFF (step A1). The conflict flag here is realized using a part of the main storage unit 3.

[0019] Then, the previous thread (thread 1
), a new thread (thread 2) is started (step A2). In this case, the #1 processor 2 of the first process 4 is assigned to the thread 1, the IPC using the shared memory method is executed, and the thread 2
The #2 processor 2 of the first process 4 is assigned to the processor 2, and IPC using the communication line method is executed. Further, these threads 1 and 2 perform processing in parallel.

In this state, the thread 1 starts a write operation to the shared memory area 31 of the main storage section 3 (step A3). Next, it is determined whether the sending side conflict flag of the conflict flags using the main storage unit 3 is on (step A4). Here, if the sending side conflict flag is not on, the shared memory area 3
The write operation continues until the write to 1 is successful (step A5).

[0021] Here, if the sending side conflict flag is turned on during the write operation to the shared memory area 31 by thread 1, then the I
It is determined that the PC succeeded first, and thread 1 is terminated (step A6).

On the other hand, if writing to the shared memory area 31 is successful before IPC by thread 2, which will be described later, is successful, the sender conflict flag is set to on (step A7) and the subsequent processing is continued. (Step A8).

On the other hand, thread 2 is similar to thread 1 described above.
At the same time, direct message transfer to the other process, that is, the second process (receiving process) 5 is started (step A9). In this case, in contrast to the case of the shared memory method using thread 1 described above, in the IPC using the communication line method using thread 2, only the message transfer must be completed even if thread 1 overtakes the IPC. Therefore, here, the process waits until the second process (receiving process) 5 of the other party receives a replay message indicating successful reception (step A10).

In this state, when a replay message is received from the second process (receiving process) 5, it is determined whether the sending side conflict flag is on (step A11).

[0025] Here, the second process (receiving process)
If the sender contention flag turns on before receiving the replay message from thread 5, it is determined that the IPC by thread 1 was successful first, and thread 2
(Step A12). On the other hand, if the IPC by thread 1 succeeds before receiving the replay message from the second process (receiving process) 5, then the sender contention flag is set to on (
Step A13), and subsequent processing continues (step A14). Next, in the second process (receiving process) 5, processing is executed according to the flowchart of FIG.

In this case as well, the flowchart starts when IPC with the first process 4 becomes necessary during the process of executing the second process 5. First, at the start of IPC, the receiving side conflict flag to be used from now on is reset to OFF (step B1). The conflict flag here is realized using a part of the main storage unit 3.

[0027] Then, the previous thread (thread 1
), a new thread (thread 2) is started (step B2). In this case, the #1 processor 2 of the second process 5 is assigned to the thread 1, the IPC using the shared memory method is executed, and the thread 2
The #2 processor 2 of the second process 5 is assigned to the processor 2, and IPC using the communication line method is executed. Further, these threads 1 and 2 perform processing in parallel.

In this state, the thread 1 starts a read process for the shared memory area 31 of the main storage section 3 (step B3). Next, it is determined whether the receiving side conflict flag is on (step B4). Here, if the receiving side conflict flag is not on,
Until reading from the shared memory area 31 is successful (
Step B5) Continue the read operation.

Here, in the middle of reading from the shared memory area 31 by thread 1, the receiving side conflict flag is set to o.
If it becomes n, IPC by thread 2 which will be described later
It is determined that thread 1 was successful first, and thread 1 is terminated (step B6).

On the other hand, if reading from the shared memory area 31 is successful before the IPC by thread 2, which will be described later, is successful, the receiving side conflict flag is set to on (step B7) and the subsequent processing is continued. (Step B8).

On the other hand, thread 2 is similar to thread 1 described above.
At the same time, reception of a message from the other process, that is, the first process (sending process) 4 is started (step B9). Next, it is determined whether the receiving side conflict flag is on (step B10). Here, if the receiving side conflict flag is not on, reception continues until message reception is successful (step B11).

[0032] Here, before the message reception is successful,
Assuming that the receiving side conflict flag is turned on, this means that the IPC by thread 1 mentioned above was successful first, but in this case, message reception is continued (step B12).
, the reception is successful (step B13), and the rep is sent to the other party.
After transferring the lay message (step B14),
Thread 2 is ended (step B15).

On the other hand, if the message is successfully received before the above-mentioned IPC by thread 1 is successful, the receiving side conflict flag is set to on (step B16), and after the replay message is transferred to the other side (step B17). ), processing continues (step B1
8).

[0034] Therefore, by doing this, when IPC with another process becomes necessary in the process of processing one process at a time, IPC can be executed in different ways for the two processors 2. , since the results of successful IPC are used first, IPC is realized using a more appropriate method that reflects the various situations of the system, such as communication line usage efficiency and access frequency to the shared memory area 31. can do. For example, if the number of accesses from each processor 2 to the shared memory area 31 is small as shown in FIG. On the other hand, as shown in FIG. 5, when many processes are executing IPC and competition for the shared memory area 31 is intense, the communication line method succeeds first, which is advantageous in this case. A line system has been adopted, and in any case, an appropriate IPC is selected depending on the current situation, and high-speed IPC can be realized.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be implemented with appropriate modifications without changing the gist. For example, in the embodiment described above, thread 1 and thread 2
Although thread 1 and thread 2 do not need to perform processing in parallel at the same time, we adopted a method in which one is executed, then the other is executed after a short wait. Good too. The key is to execute the two methods in parallel.

[0036]

[Effects of the Invention] The multiprocessor system of the present invention has the following features:
Allocate two threads to different processors, execute IPC in parallel using different shared memory methods and communication line methods for these processors, and use the results of successful IPC to perform subsequent processing. As a result, the optimal IPC method can be automatically selected according to the various system conditions that are affected by the access frequency of the shared memory and communication line, and the communication By using this method, it is possible to increase the communication speed for data exchange, and high-speed IPC can be realized.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic configuration of an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a flowchart for explaining the operation of the embodiment shown in FIG. 1;

FIG. 4 is a diagram for explaining the operation of the embodiment shown in FIG. 1.

FIG. 5 is a diagram for explaining the operation of the embodiment shown in FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1... Bus, 2... Processor, 3... Main memory part, 31... Shared memory area, 4, 5... Process.

Claims (1)

[Claims] Claim 1: In a multiprocessor system having a plurality of processors, one process has at least two
1. A multiprocessor system that uses two processors, executes different methods of inter-process communication for each processor, and adopts the inter-process communication method in which communication is completed first.