JPH04295771A - Voltage detecting circuit - Google Patents

Abstract

PURPOSE:To offer a voltage detecting circuit having the hysteresis characteristics to make the voltage detecting level of voltage ascending time higher than the detecting level of descending time. CONSTITUTION:The first and second switching elements are connected between an input terminal 1 and output terminal 13, the first switching element is turned on with the detecting output of a comparator 2 whose the detecting level is low, and the second switching element is turned on with the detecting output of a comparator 8 whose detecting level is high and also latched. When the voltage is ascending, the detecting output is first put out at the time when the second switching element is turned on, and when the voltage is descending, the detecting output is first cut off at the time when the first switching element is turned off.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a voltage detection circuit that detects whether an input voltage is above a predetermined value. This invention relates to a voltage detection circuit that has hysteresis characteristics.

0002

2. Description of the Related Art A conventional voltage detection circuit sets one detection level in advance and detects whether an input voltage is higher or lower than that detection level. Therefore, when the input voltage rises and falls, it is detected at the same detection level.

0003

By the way, in devices that use batteries as a power source, in order to avoid using exhausted batteries, it is desirable to start operation only when the battery voltage is higher than a certain level. Furthermore, when the battery voltage decreases due to consumption during use, it is desirable to allow the device to continue operating even if the voltage reaches a low level.

[0004] In order to meet such demands, it is impossible to use a conventional voltage detection circuit with a single detection level, and a circuit that detects voltage at different levels when the voltage rises and when the voltage falls is desired. .

An object of the present invention is to detect the voltage at a high level when the voltage increases, and to detect the voltage at a low level when the voltage decreases, thereby satisfying the above-mentioned requirements. An object of the present invention is to provide a voltage detection circuit.

[0006]

[Means for Solving the Problems] Therefore, the present invention provides first and second switching elements connected in series between an input terminal and an output terminal, and a switching element connected between the output terminal and ground. A third switching element is turned off when the voltage at the output terminal rises and turned on when it falls to ground, and when the voltage applied to the input terminal reaches a first level, the first switching element is turned on. a first comparator that is turned off when the voltage falls below a first level; a second comparator that detects whether the voltage applied to the input terminal has reached a second level higher than the first level; The device includes a latch circuit that turns on the second switching element and holds it when the comparator reaches the second level.

[0007]

[Examples] Examples of the present invention will be described below. FIG. 1 is a circuit diagram of a voltage detection circuit according to one embodiment. 1 is an input terminal to which power supply voltage VDD is applied here. 2 is a first comparator to which a detection voltage V1 is set; 3 is a second comparator to which a detection voltage V2 (>V1) is set; 4 is a power-on circuit that is reset when the voltage becomes higher than the detection voltage V2. It is a clear circuit. Reference numeral 5 denotes a latch circuit consisting of a transfer gate 51, an inverter 52, and an inverter with a switch 53, which holds or does not hold the output of the second comparator 3 depending on the output level of the power-on clear circuit 4. 6 is an inverter connected to the output side of the power-on clear circuit 4. 7 and 8 are PMOS FETs connected in series to the input terminal 1, one FET 7 is controlled on/off by the output of the first comparator 2 via the inverter 9, and the other FET 8 is controlled by the output of the latch circuit 5. On/off is controlled by . 10 is NM connected between FET8 and ground
This is an OS FET. 11 and 12 are inverters, and 13 is an output terminal.

Now, in this circuit, in the initial state (power supply voltage VDD of input terminal 1 = 0v), both comparators 2,
The output voltages Va and Vb of No. 3 are 0v. Therefore, the latch circuit 5 is in a loaded state. From the above, FET7,
8 is cut off, and the voltage at the output terminal 13 is 0V.

Next, when the power supply voltage VDD of the input terminal 1 rises, when the voltage reaches V1, the output voltage Va of the first comparator 2 rises to the power supply voltage VDD, and the output of the inverter 9 increases. The voltage becomes 0v, and FET7 is turned on.

[0010] Then, the power supply voltage VDD further increases to V
2, the output voltage Vb of the second comparator 3 rises to the power supply voltage VDD. At this time, the output of the power-on clear circuit 4 is 0V, so the transfer gate 51 of the latch circuit 5 is turned on, the inverter with switch 53 is turned off, the output of the inverter 52 is 0V, and the FET8
turns on.

As a result, by turning on both FETs 7 and 8,
The voltage at the common connection point of FET8 and FET10 (equivalent to output terminal 13) rises to power supply voltage VDD. For this reason, FE
T10 is turned off and power supply voltage VDD appears at output terminal 13.

After that, when the output voltage of the power-on clear circuit 4 rises from 0V to the power supply voltage VDD, the latch circuit 5
The transfer gate 51 is turned off and the switched inverter 53 is turned on.
The positive feedback operation of the inverter 52 causes the latch circuit 5 to enter a latched state, and the FET 8 is kept in the on state regardless of the output voltage of the second comparator 3.

On the other hand, when the power supply voltage VDD decreases,
When the output voltage Vb drops to V2, the output voltage Vb of the second comparator 3 falls to 0V, but the FET 8 remains on due to the function of the tick circuit 5 as described above.

[0014] Then, when the power supply voltage VDD drops to the voltage V1, the output voltage Va of the first comparator 2 becomes 0v.
Then, the output of inverter 9 rises to power supply voltage VDD, and FET 7 is turned off. As a result, output terminal 13
voltage falls to 0v.

As described above, when the power supply voltage VDD rises, the power supply voltage VDD appears at the output terminal 13 when the output of the second comparator 3, which has a high detection level, rises, and when it falls, the detection level A hysteresis operation is performed such that the voltage at the output terminal 13 becomes 0V when the output voltage of the first comparator 2, which has a low voltage, falls. A timing chart of the above operation is shown in FIG. Note that the inverters 11 and 12 are for waveform shaping and are not necessarily necessary.

FIG. 3 is a circuit diagram of another embodiment of the voltage detection circuit. Here, a regulator 14 is connected to the output terminal 13. As a result, the regulator 14 starts operating when the power supply voltage VDD rises to the voltage V2, and stops when the power supply voltage VDD falls to the voltage V1.

[0017]

As described above, according to the present invention, it is possible to provide a hysteresis characteristic such that the detection level when the input voltage falls is lower than the detection level when the input voltage rises. Therefore, when the input voltage is the battery voltage, the voltage will not be detected unless the battery voltage is high enough to detect the rise described above, which prevents the use of exhausted batteries, which may lead to unexpected situations. disappears. Also,
If the battery voltage drops during use, it is not detected until the voltage reaches a low level, which prevents the circuit from accidentally stopping.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a voltage detection circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of the operation of the voltage detection circuit.

FIG. 3 is a circuit diagram of a voltage detection circuit according to another embodiment.

[Explanation of symbols]

1: input terminal, 2: first comparator, 3: second comparator, 4: power-on clear circuit, 5: latch circuit,
51: Transfer gate, 52: Inverter, 53
: Inverter with switch, 6: Inverter, 7, 8: P
MOS FET, 9: Inverter, 10: NMOS FET
ET, 11, 12: Inverter, 13: Output terminal, 14
:regulator.

Claims (2)

[Claims] 1. First and second switching elements connected in series between an input terminal and an output terminal, and a switching element connected between the output terminal and ground and turned off when the voltage at the output terminal rises. a third switching element that turns on when the voltage falls to ground, and a third switching element that turns on the first switching element when the voltage applied to the input terminal reaches a first level and turns off when the voltage falls below the first level. a second comparator that detects whether the voltage applied to the input terminal reaches a second level higher than the first level; and a second comparator that detects whether the voltage applied to the input terminal reaches the second level, A voltage detection circuit comprising a latch circuit that turns on the second switching element and holds it. 2. The voltage detection device according to claim 1, further comprising a power-on clear circuit that causes the latch circuit to perform a latching operation when the voltage applied to the input terminal exceeds the second level. circuit.