JP3082782B2 - Voltage detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage detecting circuit for detecting whether or not an input voltage is equal to or higher than a predetermined value. A voltage detection circuit having a hysteresis characteristic.

[0002]

2. Description of the Related Art An ordinary voltage detection circuit sets one detection level in advance and detects whether an input voltage is higher or lower than the detection level. Therefore, when the input voltage rises and falls, the input voltage is detected at the same detection level.

[0003]

By the way, in a device using a battery as a power source, it is desirable to start the operation only when the battery voltage is higher than a certain level in order to avoid using a depleted battery. When the battery voltage decreases due to consumption during use, it is desirable that the operation of the device be continued even if the voltage reaches a low level.

In order to meet such a demand, a conventional voltage detection circuit having a single detection level is impossible, and a circuit which performs voltage detection at different levels when the voltage rises and when the voltage falls is desired. .

An object of the present invention is to detect the voltage at a high level when the voltage rises and to detect the voltage at a low level when the voltage drops, so that the above-mentioned demand can be satisfied. It is to provide a voltage detection circuit.

[0006]

SUMMARY OF THE INVENTION Accordingly, the present invention provides a first and a second switching element connected in series between an input terminal and an output terminal, and the first and second switching elements connected between the output terminal and ground. Turning on the first switching element when the voltage applied to the input terminal reaches a first level, and turning on the first switching element when the voltage applied to the input terminal reaches a first level; A first comparator for turning off when the voltage falls below a first level, a second comparator for detecting whether or not a voltage applied to the input terminal has reached a second level higher than the first level; And a latch circuit for turning on the second switching element when the comparator reaches the second level and holding the second switching element.

[0007]

Embodiments of the present invention will be described below. FIG. 1 is a circuit diagram of a voltage detection circuit according to one embodiment. Reference numeral 1 denotes an input terminal to which a power supply voltage V _DD is applied. 2
Is a first comparator to which a detection voltage V1 is set, 3 is a second comparator to which a detection voltage V2 (> V1) is set,
Reference numeral 4 denotes a power-on-clear circuit that performs reset release when the voltage becomes higher than the detection voltage V2. Reference numeral 5 denotes a latch circuit including a transfer gate 51, an inverter 52, and an inverter 53 with a switch.
May or may not keep the output of Reference numeral 6 denotes an inverter connected to the output side of the power-on-clear circuit 4. Reference numerals 7 and 8 denote PMOS Fs connected in series to the input terminal 1.
The on / off of one FET 7 is controlled by the output of the first comparator 2 via the inverter 9, and the on / off of the other FET 8 is controlled by the output of the latch circuit 5. 10 is an NMO connected between the FET 8 and the ground.
S FET. 11 and 12 are inverters, and 13 is an output terminal.

In this circuit, in the initial state (the power supply voltage V _DD = 0 V of the input terminal 1), both comparators 2, 3
Output voltages Va and Vb are 0V. Therefore, the latch circuit 5 is in the load state. From the above, FET7,8
Is cut off, and the voltage of the output terminal 13 is 0V.

Next, when the power supply voltage V _DD of the input terminal 1 rises, when the voltage reaches V 1, the output voltage Va of the first comparator 2 first rises to the power supply voltage V _DD , The output becomes 0 V, and the FET 7 turns on.

Then, the power supply voltage V _DD further rises to V2
, The output voltage Vb of the second comparator 3 rises to the power supply voltage _VDD . At this time, since the output of the power-on clear circuit 4 is 0 V, the transfer gate 51 of the latch circuit 5 is turned on, the inverter 53 with the switch is turned off, the output of the inverter 52 becomes 0 V, and the FET 8 is turned on.

As a result, when both FETs 7 and 8 are turned on,
The voltage at the common connection point between the FET 8 and the FET 10 (equivalent to the output terminal 13) rises to the power supply voltage V _DD . Therefore, FET
10 turns off, and the power supply voltage V _DD appears at the output terminal 13.

Thereafter, when the output voltage of the power-on clear circuit 4 rises from 0 V to the power supply voltage V _DD , the transfer gate 51 of the latch circuit 5 is turned off and the inverter 53 with a switch is turned on, and the inverter with a switch is turned on. The latch circuit 5 enters the latch state by the positive feedback operation of the inverter 53 and the inverter 52, and the ON state of the FET 8 is maintained regardless of the output voltage of the second comparator 3.

On the other hand, when the power supply voltage V _DD falls, the output voltage Vb of the second comparator 3 falls to 0 V when the power supply voltage V _DD falls to V 2. The FET 8 keeps the ON state.

When the power supply voltage V _DD drops to the voltage V1, the output voltage Va of the first comparator 2 falls to 0V, the output of the inverter 9 rises to the power supply voltage V _DD , and the FET 7 turns off. As a result, the voltage of the output terminal 13 falls to 0V.

As described above, when the power supply voltage V _DD rises, the power supply voltage V _DD appears at the output terminal 13 when the output of the second comparator 3 having a high detection level rises,
When the output voltage drops, the voltage of the output terminal 13 becomes 0 V when the output voltage of the first comparator 2 having a low detection level falls.
The hysteresis operation is as follows. FIG. 2 shows a timing chart of the above operation. The inverters 11 and 12 are used for waveform shaping, and are not always necessary.

FIG. 3 is a circuit diagram of a voltage detection circuit according to another embodiment. Here, the regulator 14 is connected to the output terminal 13. As a result, when the power supply voltage V _DD rises to the voltage V2, the regulator 14 starts operating and the voltage V
It stops when it drops to 1.

[0017]

As described above, according to the present invention, it is possible to provide a hysteresis characteristic such that the detection level when the input voltage falls is lower than the detection level when the input voltage rises. For this reason, when the input voltage is the battery voltage, the battery voltage is not detected unless the battery voltage is higher than the above-described rising detection level, so that the use of the exhausted battery can be prevented, which may cause an unexpected situation. Disappears. Further, when the battery voltage drops during use, no detection is made until the battery voltage reaches a low voltage, so that it is possible to prevent the circuit from stopping unnecessarily.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a voltage detection circuit according to one embodiment of the present invention.

FIG. 2 is a timing chart of the operation of the voltage detection circuit.

FIG. 3 is a circuit diagram of a voltage detection circuit according to another embodiment.

[Explanation of symbols]

1: input terminal, 2, first comparator, 3: second comparator, 4: power-on clear circuit, 5: latch circuit,
51: transfer gate, 52: inverter, 5
3: Inverter with switch, 6: Inverter, 7, 8:
PMOS FET, 9: inverter, 10: NMOS FET, 11, 12: inverter, 13: output terminal, 1
4: Regulator.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G01R 19/00-19/32 H02J 1/00-1/16 H03K 5/00-5/26 H03K 17 / 00-17/98

Claims (2)

(57) [Claims] A first switching element connected in series between an input terminal and an output terminal; and a first switching element connected between the output terminal and ground, and turned off when a voltage of the output terminal rises. A third switching element that is turned on when falling to the ground, and a first switching element that is turned on when a voltage applied to the input terminal reaches a first level;
A first comparator that turns off when the voltage falls below the level of the first comparator, a second comparator that detects whether the voltage applied to the input terminal has reached a second level higher than the first level, and a second comparator that detects whether the voltage applied to the input terminal has reached a second level higher than the first level. A voltage detection circuit, comprising: a latch circuit that turns on the second switching element when the second level is reached and holds the second switching element. 2. A voltage detecting device according to claim 1, further comprising a power-on-clear circuit for performing a latch operation of said latch circuit when a voltage applied to said input terminal exceeds said second level. circuit.