KR950002023B1 - Circuit for backup cmos memory - Google Patents

Circuit for backup cmos memory Download PDF

Info

Publication number
KR950002023B1
KR950002023B1 KR1019920000633A KR920000633A KR950002023B1 KR 950002023 B1 KR950002023 B1 KR 950002023B1 KR 1019920000633 A KR1019920000633 A KR 1019920000633A KR 920000633 A KR920000633 A KR 920000633A KR 950002023 B1 KR950002023 B1 KR 950002023B1
Authority
KR
South Korea
Prior art keywords
transistor
voltage
resistor
circuit
terminal
Prior art date
Application number
KR1019920000633A
Other languages
Korean (ko)
Other versions
KR930017031A (en
Inventor
권영호
Original Assignee
금성전선주식회사
박원근
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성전선주식회사, 박원근 filed Critical 금성전선주식회사
Priority to KR1019920000633A priority Critical patent/KR950002023B1/en
Publication of KR930017031A publication Critical patent/KR930017031A/en
Application granted granted Critical
Publication of KR950002023B1 publication Critical patent/KR950002023B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Power Sources (AREA)

Abstract

When the power is off, the central processing unit (CPU) stops memory function and preserves data by use of battery power. The circuit consists of a current control circuit with a Zener diode (D1), resistances (R1,R2,R3) and transistors (Q1,Q2), and a battery (BATT) part with a resistance (R4), a diode (D2) and a battery, and a voltage comparing part with an IC input devices (2,3) and resistances (R5, R6). The voltage comparing part controls CPU by comparing two powers (VCC, VBAT) and tansmitting a signal (POFF) to output device (7).

Description

마이크로 프로세서 응용회로에서의 CMOS 메모리 백업회로CMOS Memory Backup Circuit in Microprocessor Applications

제1도는 본 발명의 CMOS 메모리 백업회로도.1 is a CMOS memory backup circuit diagram of the present invention.

제2도는 본 발명의 동작 원리도.2 is a principle of operation of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

D1: 전압 제어용 다이오드D2: 전원 출력 다이오드D 1 : voltage control diode D 2 : power output diode

R1~R6: 저항 BATT : Nicd 배터리(3.6V)R 1 to R 6 : Resistance BATT: Nicd battery (3.6V)

Q1, Q2: 트랜지스터 IC : 비교기Q 1 , Q 2 : Transistor IC: Comparator

A : 동작기능 전압 B : 동작불확실 전압A: Operating Function Voltage B: Operating Uncertain Voltage

C : 동작불가능 전압C: Inoperable Voltage

본 발명은 마이크로 프로세서에 의한 CMOS 램 내에 기억된 데이타를 전원공급 중단시에도 안전하게 보존할 수 있도록 한 마이크로 프로세서 응용회로에서의 CMOS 메모리 백업회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS memory backup circuit in a microprocessor application circuit that enables safe storage of data stored in the CMOS RAM by a microprocessor even when power supply is interrupted.

종래의 메모리 백업회로를 채택한 마이크로 프로세서에서는 CMOS 램에게만 바이어스 전원을 인가한 상태에서 전원공급이 중단된 순간에 마이크로 프로세서의 동작이 불완전하게 되어 먼저 기억된 데이타를 손상시키게 되는 단점이 있었다.The conventional microprocessor employing the memory backup circuit has a disadvantage in that the microprocessor is incompletely operated when the power supply is stopped while the bias power is applied only to the CMOS RAM, thereby damaging the previously stored data.

따라서 본 발명에서는 전원공급이 중단되는 순간에 메모리가 동작불가능 상태가 되기 이전에 CPU에게 전원의 이상 상태를 알려 CPU가 모든 동작을 먼저 정지시켜 불필요한 데이타를 램에 기입치 못하게 하며 배터리의 전원을 이용하여 데이타를 보존할 수 있게 구성된 회로이다.Therefore, in the present invention, before the memory becomes inoperable state at the moment of stopping the power supply, the CPU informs the abnormal state of the power supply so that the CPU stops all operations first so that unnecessary data cannot be written to the RAM and uses the battery power. It is a circuit configured to save data.

이하 도면 제1도에 의거하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to FIG. 1.

먼저 메모리를 유지시키는 전원(VCC) 5V를 제너 다이오드(D1)의 케소드 단자와 밧데리(BATT)전원의 역전압 방지를 위한 트랜지스터(Q1)의 이미터단자에 인가하고, 저항(R1, R2)은 각각 인가전압을 제어하기 위한 제너 다이오드(D1)의 애노드 단자에 직렬로 연결되게 하고 트랜지스터(Q2)는 전원공급시 배터리 또는 CMOS 램으로 공급되는 전류를 제어하기 위한 것으로 저항(R1, R2) 사이에 트랜지스터(Q2)의 베이스 단자를 연결하고 트랜지스터(Q2)의 콜렉터에서 출력되는 전류로서 트랜지스터(Q1)를 구동시킨다.First, 5V of the power supply V CC holding the memory is applied to the emitter terminal of the transistor Q 1 for preventing the reverse voltage of the cathode terminal of the Zener diode D 1 and the battery power supply, and the resistor R 1 and R 2 are respectively connected in series to the anode terminal of the zener diode D 1 for controlling the applied voltage, and the transistor Q 2 is for controlling the current supplied to the battery or the CMOS RAM when the power is supplied. resistance (R 1, R 2) connects the base terminal of the transistor (Q 2) between the drive as a current output at the collector of the transistor (Q 2) transistors (Q 1).

VBAT출력이 입력되는 메모리 단자(도시안됨)와 트랜지스터(Q1)의 콜렉터 사이에 저항(R4)과 다이오드(D2)의 캐소드가 병렬 연결되고, 상기 저항(R4)과 다이오드(D2)의 반대편 단자가 Nicd 밧데리(BATT)의 +극에 연결된다.V BAT output is the cathode of the resistance (R 4) and a diode (D 2) between the collector of the memory terminal (not shown) and the transistor (Q 1) is input is connected in parallel, the resistance (R 4) and a diode (D The opposite terminal of 2 ) is connected to the + pole of the Nicd battery (BATT).

전원 출력단자(VBAT)에서 저항(R5)을 거쳐 비교기(IC)의 7번 단자에서신호를 출력한다.From terminal 7 of comparator (IC) through resistor (R 5 ) at power output terminal (V BAT ) Output the signal.

이와 같이 구성된 본 발명의 작용효과를 설명하면, 평상시 전원(Vcc)이 PNP형 트랜지스터(Q1)의 이미터와 제너 다이오드(D1)의 캐소드에 공급되면, 제너 다이오드(D1)가 가진 특성에 의해 일정한 전압을 출력하게 되고 상기 전압에 의해 저항(R1, R2)을 통해 트랜지스터(Q2)가 온되어 트랜지스터(Q1)의 베이스에 공급되는 전위는 접지와 연결되어 트랜지스터(Q1)는 도통이 된다.Turning to the effects of the present invention constructed in this manner, when the normal power supply (Vcc) is applied to the cathodes of the emitter and the Zener diode (D 1) of the PNP-type transistor (Q 1), the Zener diode (D 1) the characteristics of transistor (Q 2) and to output a constant voltage through a resistor (R 1, R 2) by the voltage by the turns on the potential to be supplied to the base of the transistor (Q 1) is connected to the grounding transistor (Q 1 ) Becomes conductive.

이에 따라 전원(Vcc) 전압이 트랜지스터(Q1)의 이미터를 통해 메모리에 공급되며, 또한 저항(R4)를 통해 Nicd 밧데리(BATT)로 충전된다.Accordingly, the power supply Vcc voltage is supplied to the memory through the emitter of the transistor Q 1 , and also charged to the Nicd battery BATT through the resistor R 4 .

전원이 최초로 공급될 경우에 공급전원을 제2도의 동작 원리도와 함께 설명하면, 전원인가시에 공급전원(Vcc)이 제2도의 동작불가능 전압(C)에서 동작가능 전압(A)으로 안정적인 전위가 될때까지 저항(R6)을 통해 비교기(IC)의 2번 단자에 입력되는 전압과 저항(R5)을 통해 비교기(IC)의 3번 단자에 입력되는 전압의 비교로, Vcc(공급전압)＜VBAT일때 비교기(IC)의 7번 단자출력()은 로우로 CPU에 입력되어 메모리의 동작을 정지시킨다.If the power supply is described with the operating principle of FIG. 2 when the power is first supplied, when the power is applied, a stable potential from the inoperable voltage (C) of FIG. Vcc (supply voltage) by comparing the voltage input to terminal 2 of comparator (IC) through resistor (R 6 ) and the voltage input to terminal 3 of comparator (IC) through resistor (R 5 ) until <V BAT terminal 7 comparator (IC) output ( ) Enters the CPU low to stop the memory operation.

공급전원(Vcc)이 동작 가능 전압(A)으로 상승했을 때는, Vcc(공급전압)＜VBAT되어 비교기(IC)의 7번단자의 출력은 하이로 CPU와 메모리 동작이 가능케 되는 것이다.When the supply power supply (Vcc) rises to the operable voltage (A), Vcc (supply voltage) <V BAT is set to terminal 7 of the comparator (IC). Output is high, enabling CPU and memory operations.

불시에 저항(R6)에 연결된 공급전원이 차단되었을 때는 공급전원 차단시 제2도처럼 천천히 전압이 하강하게 되는데 저항(R6)을 거친 공급전원이 동작불확실 전압(B)에 위치했을때 비교기(IC)의 비교에 의해 VBAT＞Vcc(공급전원)이 되므로, 비교기(IC)의 7번 출력단자()가 로우로 되어 이것이 CPU로 입력되어 메모리의 동작을 정지시키고 메모리내의 데이타를 보호하게 된다.When the power supply connected to the resistor R 6 is unexpectedly interrupted, the voltage drops slowly as shown in FIG. 2 when the supply power is cut off. When the supply power passing through the resistor R 6 is located at the operating uncertainty voltage B, the comparator Since V BAT > Vcc (supply power supply) by comparing (IC), output terminal 7 of comparator (IC) ) Goes low, which enters the CPU to stop the memory and protect the data in the memory.

본 발명은 공급전원의 상태를 감지하여, 적절한 시기에 CPU가 메모리의 동작을 정지시킬 수 있게 하여, 특성저하 및 다른 정전시에도 안전하게 데이타를 보호할 수 있으며 간단한 회로로 구성되어 비용이 적게드는 이점이 있다.The present invention detects the state of the power supply, allows the CPU to stop the operation of the memory at the appropriate time, can safely protect data in the event of deterioration and other power outages, and consists of a simple circuit to reduce the cost There is this.

Claims (1)

제너 다이오드(D1)를 거쳐 저항(R1, R2)와 트랜지스터(Q1, Q2)로 각기 구성되어 트랜지스터(Q2)의 전류 제어에 의해 트랜지스터(Q1)을 통해서 안정되게 전류를 공급하는 전류 제한회로, 트랜지스터(Q1)의 콜렉터 단자와 접지단자 사이에 병렬 연결된 저항(R4), 다이오드(D2)와 밧데리(BATT)가 직렬 연결된 Nicd 밧데리부, 저항(R5)와 외부 공급전원에 연결된 저항(R6)이 각각 비교기의 입력단자에 접속되어 공급전원(Vcc)과 전원(VBAT)을 비교하는 비교기 출력단자에서신호를 발생함으로써 CPU를 제어하는 전압비교부로 구성된 마이크로 프로세서 응용회로에서의 CMOS 메모리 백업회로.It is composed of resistors R 1 and R 2 and transistors Q 1 and Q 2 through a zener diode D 1 to stably flow current through transistor Q 1 by controlling the current of transistor Q 2 . Supply current limiting circuit, resistor (R 4 ) connected in parallel between collector terminal of transistor (Q 1 ) and ground terminal, Nicd battery part, resistor (R 5 ) connected diode (D 2 ) and battery (BATT) in series a resistor connected to the external power supply (R 6) is connected to the input terminal of each comparator supply voltage (Vcc) to the power at the comparator output terminal for comparing (V BAT) CMOS memory backup circuit in a microprocessor application circuit comprising a voltage comparison section for controlling a CPU by generating a signal.
KR1019920000633A 1992-01-17 1992-01-17 Circuit for backup cmos memory KR950002023B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920000633A KR950002023B1 (en) 1992-01-17 1992-01-17 Circuit for backup cmos memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920000633A KR950002023B1 (en) 1992-01-17 1992-01-17 Circuit for backup cmos memory

Publications (2)

Publication Number Publication Date
KR930017031A KR930017031A (en) 1993-08-30
KR950002023B1 true KR950002023B1 (en) 1995-03-08

Family

ID=19328020

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920000633A KR950002023B1 (en) 1992-01-17 1992-01-17 Circuit for backup cmos memory

Country Status (1)

Country Link
KR (1) KR950002023B1 (en)

Also Published As

Publication number Publication date
KR930017031A (en) 1993-08-30

Similar Documents

Publication Publication Date Title
JPH04156233A (en) Charging equipment
EP0238803B1 (en) Stabilized power-supply circuit
JPH02246740A (en) Power back-up circuit
US5157270A (en) Reset signal generating circuit
US5130633A (en) Circuit for detecting an excess-discharge of a battery
KR950002023B1 (en) Circuit for backup cmos memory
JP3535520B2 (en) Reset circuit
US6870721B2 (en) Apparatus for power source protection with automatic latch-off
KR940000522B1 (en) Charging circuit of battery
JP2001352692A (en) Backup power charger
KR200157748Y1 (en) Electrostatic compensation circuit
KR920002337Y1 (en) Timer reset circuit using condensors
JPS6338694Y2 (en)
KR19990040744U (en) Battery over discharge protection device in portable device
KR910001691Y1 (en) The protection circuit of ram data at interruption of electric power
JPH03101518A (en) Load driving circuit
KR0129033Y1 (en) Constant current charging circuit in wireless telephone
JP2515950Y2 (en) Backup power supply voltage drop detection circuit
JPH0379937B2 (en)
JPS59212926A (en) Detector for voltage drop of power supply
JPH0473326B2 (en)
JPS607166A (en) Protecting circuit
JPH11313443A (en) Battery charger
JPH06141477A (en) Battery type power supply mechanism
JPS59127540A (en) Backup power source circuit

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 19980305

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee