JPH0379937B2 - - Google Patents
Info
- Publication number
- JPH0379937B2 JPH0379937B2 JP56036041A JP3604181A JPH0379937B2 JP H0379937 B2 JPH0379937 B2 JP H0379937B2 JP 56036041 A JP56036041 A JP 56036041A JP 3604181 A JP3604181 A JP 3604181A JP H0379937 B2 JPH0379937 B2 JP H0379937B2
- Authority
- JP
- Japan
- Prior art keywords
- battery
- power supply
- circuit
- voltage
- supply circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- OJIJEKBXJYRIBZ-UHFFFAOYSA-N cadmium nickel Chemical compound [Ni].[Cd] OJIJEKBXJYRIBZ-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
Description
【発明の詳細な説明】
本発明は、バツテリ過放電検出方式、特に通常
電源、バツテリおよびバツテリでバツクアツプさ
れた回路をそなえ上記バツテリは上記通常電源に
より充電されつつ上記バツテリでバツクアツプさ
れた回路を動作させる電子装置において、上記通
常電源が投入されると上記バツテリへの充電開始
を遅延せしめると共にバツテリ過放電状態を検出
できるようにしたバツテリ過放電検出方式に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a battery over-discharge detection method, in particular, comprises a normal power supply, a battery, and a circuit backed up by the battery, and the battery operates the circuit backed up by the battery while being charged by the normal power supply. The present invention relates to a battery over-discharge detection method that delays the start of charging the battery when the normal power is turned on, and detects an over-discharge state of the battery in an electronic device.
マイクロプロセツサなどの電子回路を無停電動
作させる為の電源として、一般にニツケル・カド
ミウム電池などの充放電可能なバツテリが用いら
れる。この種のバツテリは通常第１図に図示する
如く、通常電源回路１から抵抗Ｒ、ダイオードＤ
などを介して充電されつつバツテリによりバツク
アツプされた回路即ちバツテリでバツクアツプさ
れた回路２を動作せしめるよう構成される。なお
図示符号３はバツテリである。 Rechargeable and dischargeable batteries, such as nickel-cadmium batteries, are generally used as power sources for uninterrupted operation of electronic circuits such as microprocessors. This type of battery normally has a power supply circuit 1, a resistor R, a diode D, as shown in FIG.
It is configured to operate the battery backed up circuit, ie, the battery backed up circuit 2, while being charged via the battery. Note that the reference numeral 3 in the figure is a battery.
ところでこの種の電子装置において、バツテリ
が過放電状態にあると、バツテリでバツクアツプ
された回路２が正常な動作を行なえなくなり、例
えば情報の消失、各種の誤動作を行なうなどの状
態が発生する。しかしこのような状態の発生にも
かかわらず通常電源１を投入すると、バツテリ３
は急速に電圧が上昇し、バツテリでバツクアツプ
された回路２は異常な状態のままで再び動作を開
始することとなる。 In this type of electronic device, if the battery is in an over-discharge state, the circuit 2 backed up by the battery will no longer be able to operate normally, resulting in situations such as loss of information and various malfunctions. However, when the normal power supply 1 is turned on despite the occurrence of this condition, the battery 3
The voltage increases rapidly, and the circuit 2 backed up by the battery starts operating again in an abnormal state.
本発明は上記の点を考慮し、通常電源回路１の
電源投入時にバツテリ３が過放電状態にあること
を簡単な構成により検出し得るようにし当該検出
信号によりバツテリでバツクアツプされた回路２
がリセツト状態になるようにして正常な動作が開
始できるようにすることを目的としている。そし
てそのため本発明のバツテリ過放電検出方式は、
通常電源回路１と、バツテリ３と、バツテリ３
でバツクアツプされた回路２とを備え、上記バツ
テリ３が、上記通常電源回路１により充電されつ
つ上記バツテリでバツクアツプされた回路２を動
作させる電子装置において、
通常電源回路１の電源投入が行われ、電源電圧
が正常値になつた後に充電指示信号を発生する制
御手段８と、
充電指示信号が発生する迄は通常電源回路１か
らバツテリ３への充電を阻止し、充電指示信号が
出されていることを条件として通常電源回路１か
らバツテリ３への充電を行う給電制御用スイツチ
手段４と、
バツテリ３の一端とバツテリ・バツクアツプ回
路２を接続する電力供給線と、
通常電源回路１の出力によつて付勢される基準
電圧発生手段５と、
アノードが抵抗を介して上記通常電源回路１に
接続され、カソードが所定電位とされ、アノード
電圧がバツテリ状態信号として出力されるサイリ
スタ１１と、
エミツタに基準電圧発生手段５から出力される
基準電圧が印加され、ベースが抵抗を介して上記
電力供給線に接続され、コレクタが抵抗を介して
上記サイリスタ１１のゲートに接続されたPNP
トランジスタ９と
を具備し、
通常電源回路１が投入されてから給電制御用ス
イツチ手段４がオンされるまでの間において、バ
ツテリ３の電圧が基準電圧より低下している場合
には、PNPトランジスタ９を通じ、基準電圧で
バツテリ３を充電すると同時にサイリスタ１１を
点弧し、これにより過放電を検出する
ことを特徴とするものである。以下第２図および
第３図を参照しつつ本発明を説明する。 In consideration of the above points, the present invention makes it possible to detect with a simple configuration that the battery 3 is in an over-discharge state when the power is turned on to the normal power supply circuit 1, and the circuit 2 backed up by the battery receives the detection signal.
The purpose of this is to bring the device into a reset state so that normal operation can begin. Therefore, the battery over-discharge detection method of the present invention has the following functions: normal power supply circuit 1, battery 3, and battery 3.
In the electronic device, the battery 3 is charged by the normal power supply circuit 1 and operates the circuit 2 backed up by the battery, wherein the normal power supply circuit 1 is powered on; A control means 8 that generates a charging instruction signal after the power supply voltage reaches a normal value, and a control means 8 that normally prevents charging from the power supply circuit 1 to the battery 3 until the charging instruction signal is generated, and the charging instruction signal is issued. A power supply control switch means 4 for charging the battery 3 from the normal power supply circuit 1, a power supply line connecting one end of the battery 3 and the battery backup circuit 2, and an output of the normal power supply circuit a thyristor 11 whose anode is connected to the normal power supply circuit 1 through a resistor, whose cathode is set at a predetermined potential, and whose anode voltage is output as a battery status signal; A PNP to which a reference voltage output from the reference voltage generating means 5 is applied, a base connected to the power supply line through a resistor, and a collector connected to the gate of the thyristor 11 through a resistor.
If the voltage of the battery 3 is lower than the reference voltage between the time when the power supply circuit 1 is turned on and the time when the power supply control switch means 4 is turned on, the PNP transistor 9 is provided. This is characterized in that the battery 3 is charged with a reference voltage and the thyristor 11 is fired at the same time, thereby detecting overdischarge. The present invention will be explained below with reference to FIGS. 2 and 3.
第２図は本発明の一実施例構成、第３図はその
動作説明図を夫々示している。 FIG. 2 shows the configuration of an embodiment of the present invention, and FIG. 3 shows an explanatory diagram of its operation.
第２図において、３はバツテリ、４は給電制御
用スイツチング・トランジスタ、５は基準電圧発
生回路、６は電圧比較回路、７は状態信号発生回
路、８は給電制御用スイツチング・トランジスタ
４の制御部を制御する制御回路、９はPNPトラ
ンジスタ、１０はNPNトランジスタ、１１はサ
イリスタ、１２ないし１４は夫々ゼナ・ダイオー
ド、１５はリレー巻線、１６はリレー接点、１７
はダイオード、１８ないし２６は夫々抵抗、２７
はコンデンサを夫々表わしている。以下処理およ
び動作を第３図をあわせ参照しつつ説明する。 In FIG. 2, 3 is a battery, 4 is a power supply control switching transistor, 5 is a reference voltage generation circuit, 6 is a voltage comparison circuit, 7 is a status signal generation circuit, and 8 is a control section of the power supply control switching transistor 4. 9 is a PNP transistor, 10 is an NPN transistor, 11 is a thyristor, 12 to 14 are Zena diodes, 15 is a relay winding, 16 is a relay contact, 17
is a diode, 18 to 26 are resistors, 27
represent capacitors. The processing and operation will be explained below with reference to FIG.
当該回路に第３図図示a1の如き通常電源１によ
る直流電圧Ｖが印加されると、制御回路８におい
て、図示端子Ａから抵抗２６および第２図図示の
如きスイツチング状態にあるリレー接点１６を介
して電流が流れると共に、図示端子Ａから抵抗２
４を介してコンデンサ２７に充電電流が流れコン
デンサ２７の端子間電圧が第３図図示波形a2の如
く上昇してゆく。そしてコンデンサ２７端子間電
圧がゼナ・ダイオード１３のゼナ電圧値にトラン
ジスタ１０のベース・エミツタ間電圧値を加算し
た電圧値に到達するようになると、トランジスタ
１０がオフ状態からオン状態に反転しリレー巻線
１５に電流が供給開始される。このためリレー接
点１６において接点切替動作が行なわれ、給電制
御用スイツチング・トランジスタ４のベース電圧
は急激に上昇し、オフ状態からオン状態に反転
し、バツテリ３に充電電流が供給されるようにな
る。即ちバツテリ３の＋端子電圧即ち図示点Ｂの
端子電圧は第３図図示の波形a5で示す如くなる。 When a DC voltage V from the normal power source 1 as shown in FIG. A current flows through the resistor 2 from the terminal A shown in the figure.
A charging current flows to the capacitor 27 through the capacitor 27, and the voltage between the terminals of the capacitor 27 rises as shown in the waveform a2 in FIG. When the voltage between the terminals of the capacitor 27 reaches the voltage value obtained by adding the voltage value between the base and emitter of the transistor 10 to the Zener voltage value of the Zener diode 13, the transistor 10 is reversed from the off state to the on state, and the relay winding Current begins to be supplied to line 15. For this reason, a contact switching operation is performed at the relay contact 16, and the base voltage of the power supply control switching transistor 4 rises rapidly, switching from the OFF state to the ON state, and charging current is supplied to the battery 3. . That is, the positive terminal voltage of the battery 3, ie, the terminal voltage at point B in the figure, becomes as shown by waveform a5 in FIG.
一方直流電源Ｖの印加によつて、図示点Ａから
抵抗１９を介してバツテリの正常電圧範囲の最小
値からトランジスタ９のベース・エミツタ間電圧
を差し引いたゼナ電圧値をもつ様に選択したゼ
ナ・ダイオード１２に電流が流れ、トランジスタ
９のエミツタ電圧は第３図図示波形a4で示す如く
ゼナ・ダイオード１２のゼナ電圧レベルに維持さ
れる。この状態において、バツテリ３の端子間電
圧が過放電状態にあると、トランジスタ９はオン
状態にスイツチングされ、抵抗２１および抵抗２
２を介して電流が流れる。このためサイリスタ１
１のゲート電圧は第３図図示a6に図示する如き波
形で印加され、サイリスタ１１はオン状態にされ
る。このためサイリスタ１１のアノード電圧波形
即ちバツテリ状態信号は第３図a7に図示する如き
ものとなる。他方、上記状態において、バツテリ
３の端子間電圧が正常な電圧レベルをもつものと
すれば、トランジスタ９はオフ状態に維持されつ
づけサイリスタ１１はオフ状態に維持される。即
ちサイリスタ１１のゲート電圧波形およびアノー
ド電圧波形は第３図図示の波形a6′および波形
a7′の如くなる。 On the other hand, by applying the DC power supply V, the zener voltage selected to have a zener voltage value obtained by subtracting the base-emitter voltage of the transistor 9 from the minimum value of the battery's normal voltage range from the point A shown in the figure through the resistor 19 is applied. Current flows through the diode 12, and the emitter voltage of the transistor 9 is maintained at the zener voltage level of the zener diode 12, as shown by waveform a4 in FIG. In this state, when the voltage between the terminals of the battery 3 is in an overdischarge state, the transistor 9 is switched on, and the resistor 21 and the resistor 2 are switched on.
Current flows through 2. For this reason, thyristor 1
A gate voltage of 1 is applied with a waveform as shown in a 6 of FIG. 3, and the thyristor 11 is turned on. Therefore, the anode voltage waveform of the thyristor 11, ie, the battery status signal, becomes as shown in FIG. 3a7 . On the other hand, in the above state, assuming that the voltage between the terminals of the battery 3 has a normal voltage level, the transistor 9 is maintained in the off state and the thyristor 11 is maintained in the off state. That is, the gate voltage waveform and anode voltage waveform of the thyristor 11 are the waveform a 6 ' and the waveform shown in FIG.
It becomes like a 7 ′.
以上説明した如く、本実施例の如き比較手段を
用いることにより、通常電源切断時及び、通常電
源投入時であつてバツテリ電圧が正常電圧範囲の
ときは、比較手段が逆バイアスとなり、バツテリ
電力を消費しないとともに、通常電源投入時であ
つてバツテリが過放電状態のときはトランジスタ
９のベース及び抵抗２０を通じて、バツテリを
少々充電するのみで、何らバツテリの負荷とはな
らない。通常電源投入から給電制御用スイツチン
グ・トランジスタ４がオンするまでの間におい
て、バツテリ電圧が低下していればPNPトラン
ジスタ９を通じて電圧低下検出と同時にバツテリ
３に充電電流が供給される。これにより、バツテ
リ３を放電させないで寧ろ充電により回復させな
がらチエツクを行うことが出来る。 As explained above, by using the comparison means as in this embodiment, when the battery voltage is within the normal voltage range during normal power-off and normal power-on, the comparison means becomes reverse biased and the battery power is reduced. In addition, when the battery is normally turned on and the battery is in an over-discharged state, the battery is only slightly charged through the base of the transistor 9 and the resistor 20, and does not impose any load on the battery. If the battery voltage has decreased between the time when the power is turned on and the power supply control switching transistor 4 is turned on, a charging current is supplied to the battery 3 through the PNP transistor 9 at the same time as the voltage decrease is detected. Thereby, the check can be performed while the battery 3 is being restored by charging rather than being discharged.
さらにトランジスタ９のエミツタ電圧からベー
スエミツタ間電圧を差引いた比較基準電圧がバツ
テリの正常電圧範囲より常に低いことにより通常
電源の投入、切断を通じて誤動作を起こさない。
又、本実施例の如きバツテリ状態信号発生手段を
用いることにより、バツテリに充電を開始しバツ
テリ電圧が正常範囲内に入つた後でも、バツテリ
が過放電状態にあつたことを保持している為、バ
ツテリでバツクアツプされた回路に正常な電源電
圧が印加された後にリセツト状態に戻す等の適切
な処置が行うことが可能である。以上の様に本発
明によれば極めて有用なバツテリ過放電検出回路
が実現できる。また、本発明によれば、電圧検出
期間をシーケンスで制御する必要がなく、単に充
電開始の遅延のみで実現できるため、検出回路の
構成が極めて簡単に実現できる。 Further, since the comparison reference voltage obtained by subtracting the base-emitter voltage from the emitter voltage of the transistor 9 is always lower than the normal voltage range of the battery, malfunctions do not occur even when the power is turned on and off.
Furthermore, by using the battery status signal generating means as in this embodiment, even after the battery starts charging and the battery voltage falls within the normal range, it is possible to maintain that the battery is in an over-discharged state. It is possible to take appropriate measures such as returning the circuit to the reset state after applying a normal power supply voltage to the circuit backed up by the battery. As described above, according to the present invention, an extremely useful battery overdischarge detection circuit can be realized. Further, according to the present invention, there is no need to sequentially control the voltage detection period, and this can be achieved by simply delaying the start of charging, so the configuration of the detection circuit can be realized extremely easily.
第１図は本発明が適用される電子装置の一例、
第２図は本発明によるバツテリ過放電検出方式の
一実施例構成、第３図はその動作説明図を夫々示
す。
図中、１は通常電源回路、２はバツテリ・バツ
クアツプ回路、３はバツテリ、４は給電制御用ス
イツチング・トランジスタ、５は電圧発生回路、
６は電圧比較回路、７は状態信号発生回路を夫々
表わす。
FIG. 1 shows an example of an electronic device to which the present invention is applied.
FIG. 2 shows the configuration of an embodiment of the battery overdischarge detection method according to the present invention, and FIG. 3 shows an explanatory diagram of its operation. In the figure, 1 is a normal power supply circuit, 2 is a battery backup circuit, 3 is a battery, 4 is a switching transistor for power supply control, 5 is a voltage generation circuit,
6 represents a voltage comparison circuit, and 7 represents a status signal generation circuit.
Claims (1)
３でバツクアツプされた回路２とを備え、上記バ
ツテリ３が、上記通常電源回路１により充電され
つつ上記バツテリでバツクアツプされた回路２を
動作させる電子装置において、 通常電源回路１の電源投入が行われ、電源電圧
が正常値になつた後に充電指示信号を発生する制
御手段８と、 充電指示信号が発生する迄は通常電源回路１か
らバツテリ３への充電を阻止し、充電指示信号が
出されていることを条件として通常電源回路１か
らバツテリ３への充電を行う給電制御用スイツチ
手段４と、 バツテリ３の一端とバツテリ・バツクアツプ回
路２を接続する電力供給線と、 通常電源回路１の出力によつて付勢される基準
電圧発生手段５と、 アノードが抵抗を介して上記通常電源回路１に
接続され、カソードが所定電位とされ、アノード
電圧がバツテリ状態信号として出力されるサイリ
スタ１１と、 エミツタに基準電圧発生手段５から出力される
基準電圧が印加され、ベースが抵抗を介して上記
電力供給線に接続され、コレクタが抵抗を介して
上記サイリスタ１１のゲートに接続されたPNP
トランジスタ９と を具備し、 通常電源回路１が投入されてから給電制御用ス
イツチ手段４がオンされるまでの間において、バ
ツテリ３の電圧が基準電圧より低下している場合
には、PNPトランジスタ９を通じ、基準電圧で
バツテリ３を充電すると同時にサイリスタ１１を
点弧し、これにより過放電を検出する ことを特徴とするバツテリ過放電検出方式。[Scope of Claims] 1. A circuit comprising a normal power supply circuit 1, a battery 3, and a circuit 2 backed up by the battery 3, wherein the battery 3 is backed up by the battery while being charged by the normal power supply circuit 1. 2, the control means 8 generates a charge instruction signal after the normal power supply circuit 1 is powered on and the power supply voltage reaches a normal value; A power supply control switch means 4 that prevents charging from the battery 3 from the normal power supply circuit 1 to the battery 3 and charges the battery 3 from the normal power supply circuit 1 on the condition that a charging instruction signal is issued; A power supply line connecting the backup circuit 2, a reference voltage generating means 5 energized by the output of the normal power supply circuit 1, an anode connected to the normal power supply circuit 1 via a resistor, and a cathode connected to a predetermined potential. The thyristor 11 outputs the anode voltage as a battery status signal, the emitter is applied with the reference voltage output from the reference voltage generating means 5, the base is connected to the power supply line via a resistor, and the collector is connected to the thyristor 11. PNP connected to the gate of the above thyristor 11 via a resistor
If the voltage of the battery 3 is lower than the reference voltage between the time when the power supply circuit 1 is turned on and the time when the power supply control switch means 4 is turned on, the PNP transistor 9 is provided. A battery over-discharge detection method is characterized in that the battery 3 is charged with a reference voltage through the battery 3, and the thyristor 11 is fired at the same time, thereby detecting over-discharge.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56036041A JPS57151244A (en) | 1981-03-13 | 1981-03-13 | Battery overdischarge detecting system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56036041A JPS57151244A (en) | 1981-03-13 | 1981-03-13 | Battery overdischarge detecting system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57151244A JPS57151244A (en) | 1982-09-18 |
| JPH0379937B2 true JPH0379937B2 (en) | 1991-12-20 |
Family
ID=12458618
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56036041A Granted JPS57151244A (en) | 1981-03-13 | 1981-03-13 | Battery overdischarge detecting system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57151244A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010070880A1 (en) | 2008-12-17 | 2010-06-24 | 株式会社 マキタ | Cutting machine |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6184645U (en) * | 1984-11-05 | 1986-06-04 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49135140A (en) * | 1973-04-27 | 1974-12-26 | ||
| JPS5491733A (en) * | 1977-12-28 | 1979-07-20 | Fujitsu Ltd | No halt power source circuit |
| JPS5638943A (en) * | 1979-09-04 | 1981-04-14 | Tokyo Shibaura Electric Co | Preliminary power malfunction detecting system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5838432Y2 (en) * | 1980-02-25 | 1983-08-31 | タケダ理研工業株式会社 | Memory power supply |
-
1981
- 1981-03-13 JP JP56036041A patent/JPS57151244A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49135140A (en) * | 1973-04-27 | 1974-12-26 | ||
| JPS5491733A (en) * | 1977-12-28 | 1979-07-20 | Fujitsu Ltd | No halt power source circuit |
| JPS5638943A (en) * | 1979-09-04 | 1981-04-14 | Tokyo Shibaura Electric Co | Preliminary power malfunction detecting system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010070880A1 (en) | 2008-12-17 | 2010-06-24 | 株式会社 マキタ | Cutting machine |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57151244A (en) | 1982-09-18 |
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