JPH04294649A - Frame phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To attain frame phase synchronization of a sub-frame signal even when a sub-frame signal in a transmission frame signal is subject to n- multiplexing in an optional relative phase with respect to a transmission frame phase. CONSTITUTION:A sub-frame type identification circuit 10 identifies a type of a sub-frame subject to n-multiplexing in a transmission frame based on a specific pattern of an address written in an overhead area. Then in the case of n=1, a selector circuit 11a selecting (n-1) sets of write addresses and a selector circuit 11b selecting (n-1) sets of read addresses are controlled so that a buffer memory 4 is controlled in common. In the case of n>=2, the selector circuits 11a, 11b are controlled so that the buffer memory 4 is controlled independently for each sub-frame. Thus, frame phase synchronization is taken while being automatically made correspondent even in any of the cases n=1, n>=2 in n-multiplex of the sub-frame signal in the transmission frame signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame phase synchronization circuit for digital time division multiplex frames.

0002

[Prior Art] Conventionally, as a known circuit of this type, FIG.
There was something like this. This figure is from W. D. GROV
E.R., T. E. MOORE, J. A. McEACHER
N, ;”WAITING TIME JITTER R
EDUCTIONBY SYNCHRONIZER S
TUFF THRESHOLD MODULATION
", GLOBECOM ■87, P514-P518. In FIG. 3, 1 is a subframe phase detection circuit that detects an arbitrary relative phase of a subframe signal with respect to a transmission frame signal, and 2 is a subframe phase detection circuit. a write control circuit that controls writing according to 1; 3;
is a write counter that is controlled by the write control circuit 2 and generates a write address; 4 is a buffer memory in which subframe signals are stored; 5 is a read counter that generates a read address; 6 is a read control circuit that controls the read counter 5; is a phase comparison circuit that compares the phase of the write address output from the write counter 3 and the phase of the read address output from the read counter 5. Further, FIG. 4 shows an example of a transmission frame signal 50 processed by the circuit shown in FIG. Addresses indicating the relative phase of subframe signals with respect to various maintenance signals and transmission frame phases are stored.

Next, the operation will be explained. The subframe phase detection circuit 1 detects an arbitrary relative phase of the subframe signal with respect to the transmission frame signal 50 in the overhead area 110.
The information is detected from the address stored in the write control circuit 2 and sent to the write control circuit 2. The write control circuit 2 controls the write counter 3 according to the information from the subframe phase detection circuit 1, and the write counter 3 supplies the write address to the buffer memory 4 to write the subframe signal to the buffer memory 4 and adjust the phase of the write address. Output to comparison circuit 7. The read counter 5 supplies the read address to the buffer memory 4 to read out the subframe signal, and outputs the read address to the phase comparator circuit 7. The phase comparison circuit 7 compares the write address and the read address and sends the result to the read control circuit 6. The read control circuit 6 controls the read counter 5 according to the phase comparison result. Through the above operations, the subframe signal 55 read from the buffer memory 4 is synchronized with the device clock and has an arbitrary relative phase with respect to the device frame phase, and frame phase synchronization is achieved. Therefore, the conventional frame phase synchronization circuit synchronizes the frame phase of an arbitrary relative frame phase of one subframe signal, as in the transmission frame shown in FIG.

0004

[Problem to be Solved by the Invention] Since the conventional frame phase synchronization circuit is configured as described above, only the case where n=1 is considered when n subframe signals in a transmission frame signal are multiplexed. However, when n is a plurality of signals, there is a problem that frame phase synchronization of arbitrary relative phases with respect to the transmission frame phase of a plurality of subframe signals cannot be achieved.

[0005] This invention was made to solve the above-mentioned problems, and even when there is only one subframe signal in a transmission frame signal, when a plurality of subframe signals are multiplexed, The purpose of this invention is to obtain a flexible frame phase synchronization circuit that can automatically adapt to any situation.

[0006]

[Means for Solving the Problems] A frame phase synchronization circuit according to the present invention includes a demultiplexing circuit that multiplexes and demultiplexes subframe signal regions in a ratio of 1:n, and a subframe type identification circuit that identifies the type of subframe signal. A frame phase synchronization section having a processing capacity of 1/n of the processing capacity required when there is only one subframe signal in a transmission frame is provided.
A selector circuit is provided in the second and subsequent frame phase synchronization sections to respectively switch the write address and read address of the buffer memory depending on the type of subframe.

[0007]

[Operation] In the present invention, the subframe type identification circuit identifies the type of subframes multiplexed within a transmission frame, and in the case of one multiplexing, the control of the buffer memory is common to n-1. The selector circuit that selects n-1 write addresses and the selector circuit that selects n-1 read addresses are controlled, and when multiplexed, the buffer memory is controlled independently for each subframe. controlling the selector circuit; As a result, when n subframe signals are multiplexed within a transmission frame signal, frame phase synchronization can be automatically achieved in any case where n=1 or n≧2.

[0008]

[Example] Example 1. FIG. 1 is a block diagram showing the configuration of a frame phase synchronization circuit according to an embodiment of the present invention. In the figure, 1 is a subframe phase detection circuit, 2 is a write control circuit, 3 is a write counter, 4 is a buffer memory, 5 is a read counter, 6 is a read control circuit,
Reference numeral 7 denotes a phase comparator circuit, which is the same as or corresponds to the conventional circuit shown in FIG. 3 with the same reference numerals, so detailed explanation will be omitted.

Further, 81 is a frame counter which is operated by a reception clock in synchronization with the transmission frame phase and counts the transmission frame area; 82 is a frame counter which is operated by the device clock in synchronization with the device frame phase and counts the transmission frame area;
a frame counter that generates various timings and sends them to the readout control circuit 6 and the multiplexing circuit 12; 9, a demultiplexing circuit that multiplexes and demultiplexes the subframe signal area in a ratio of 1:n; 10;
11a is a subframe type identification circuit that identifies the subframe type of the subframe signal demultiplexed by the demultiplexing circuit; 11a is a selector circuit that selects a write address from the write counter 3; and 11b is a readout counter 5.
12 is a multiplexing circuit that multiplexes the subframe signals read from the buffer memory 4 in an n:1 ratio, and 13a is a subframe phase detection circuit 1 and a write control circuit 2. , write counter 3, buffer memory 4, read counter 5,
A frame phase synchronization section 13b is composed of a readout control circuit 6 and a phase comparison circuit 7 and has a processing capacity of 1/n of the processing capacity required when there is only one subframe signal in a transmission frame; Phase synchronization section 13
This frame phase synchronization section is composed of the components included in a, a selector circuit 11a, and a selector circuit 11b, and has the same processing capacity as the frame phase synchronization section 13a.

FIG. 2 shows an example of a transmission frame signal 50 processed by the circuit of FIG. 1, which has the same overhead area 110 and subframe signal area 120 capacity as the transmission frame shown in FIG. However, a case is shown in which n subframe signals are multiplexed in the subframe signal area 120. overhead area 110
stores an address indicating an arbitrary relative phase of the subframe signal with respect to the transmission frame signal, and if the subframe signal is multiplexed n, n addresses are valid, and if the subframe signal is In this case, only one address is valid, and the remaining addresses are in a specific pattern.

Next, the operation will be explained with reference to FIGS. 1 and 2. The frame counter circuit 81 operates based on the reception clock in synchronization with the transmission frame phase, counts the transmission frame area, generates various timings, and sends them to the demultiplexing circuit 9 and each subframe phase detection circuit 1. The demultiplexer circuit 9 divides the signals in the subframe signal area 120 into 1:n
frame phase synchronization units 13a and n-1.
The subframe signal after demultiplexing and the signal of the overhead area 110 are sent to the frame phase synchronization unit 13b, and also sent to the subframe type identification circuit 10. The subframe type identification circuit 10 identifies whether the subframe signal is n multiplexed and is a subframe signal with n≧2 or n=1, based on a specific pattern of addresses written in the overhead area 110, and identifies n− One selector circuit 11a and n-1 selector circuits 11b are controlled. The operation in the frame phase synchronization section 13a is as follows. The subframe phase detection circuit 1 detects an arbitrary relative phase of the subframe signal with respect to the transmission frame phase from the address stored in the overhead area 110, and sends the information to the write control circuit 2. The write control circuit 2 controls the write counter 3 according to the information from the subframe phase detection circuit 1, and the write counter 3 generates and supplies a write address to the buffer memory 4, writes the subframe signal to the buffer memory 4, and writes the write address. The phase comparator circuit 7 and n-1
Selector circuit 11a in frame phase synchronization section 13b
Send to. The read counter 5 supplies the read address to the buffer memory 4 to read the subframe signal, and sends the read address to the phase comparator circuit 7, and further to the selector circuit 11b in the n-1 frame phase synchronizers 13b. do. The phase comparison circuit 7 compares the write address and the read address and sends the result to the read control circuit 6. The read control circuit 6 controls the read counter 5 according to the phase comparison result. Through the above operations, the subframe signal is synchronized with the device clock and has an arbitrary relative phase with respect to the device frame phase, and frame phase synchronization is achieved.

Next, n-1 frame phase synchronizers 13
The operation in b is as follows. Circuits with the same symbols as those in the frame phase synchronization unit 13a perform similar operations, and when the number of subframe signals n≧2 in the transmission frame signal area 100 shown in FIG. 2, the selector circuit 11a
is controlled by the subframe type identification circuit 10 to select the write address from the write counter 2 in the frame phase synchronization section 13b and supply it to the buffer memory 4. Similarly, the selector circuit 11b has a frame phase synchronization section 13b.
The address from the read counter 5 is selected and the read address is supplied to the buffer memory 4. Each of the n-1 frame phase synchronization units 13b performs the above control,
Since each buffer memory 4 storing each subframe signal is controlled independently, frame phase synchronization of each subframe signal having an arbitrary relative phase can be achieved.

On the other hand, when the number of subframe signals n=1 in the transmission frame 100 shown in FIG.
The write address is selected and supplied to the buffer memory 4. Similarly, the selector circuit 11b selects the address from the read counter 5 of the frame phase synchronization section 13a and supplies the read address to the buffer memory 4. Therefore, all the buffer memories 4 that store demultiplexed subframe signals are commonly controlled by the frame phase synchronization section 13a, so that the frame phase synchronization section of the subframe signal can be obtained.

Furthermore, the frame counter 82 is operated by the device clock in synchronization with the device frame phase, counts the transmission frame area and generates various timings, and also demultiplexes and demultiplexes subframe signals with frame phase synchronization. The multiplexing circuit 12 multiplexes the signals n:1 and outputs the multiplexed signals.

Therefore, the subframe type identification circuit 10 identifies the type of subframe multiplexed within a transmission frame, and when the number of subframe signals n=1, the control of the buffer memory is made common. n-1 selector circuits 11a and n-1 selector circuits 11b are controlled so that when the number of subframe signals n≧2, the buffer memory is controlled independently. Since the circuit 11a and the n-1 selector circuits 11b are controlled, even if n subframe signals are multiplexed at arbitrary relative phases within the transmission frame signal, frame phase synchronization can be automatically achieved. It is possible.

[0016]

As described above, according to the present invention, a demultiplexing circuit that multiplexes and demultiplexes subframe signal areas in a ratio of 1:n and a subframe type identification circuit that identifies the type of subframe signal are provided, and transmission frame n frame phase synchronization units each having a processing capacity of 1/n of the processing capacity required when there is only one subframe signal in a signal are arranged in parallel;
Since a selector circuit for selecting the write address and read address of the buffer memory respectively according to the subframe type is provided in the frame phase synchronization section after the second frame, the subframe type identification circuit is multiplexed in n subframes within the transmission frame. A selector circuit that identifies the type of signal and selects n-1 write addresses and a selector circuit that selects n-1 read addresses so that control of the buffer memory is common when n = 1. switching, n≧
In case 2, the selector circuits are switched so that the buffer memories are controlled independently, so even if n subframe signals are multiplexed within the transmission frame signal, frame phase synchronization is automatically achieved. It has the effect of being able to

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a frame phase synchronization circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a transmission frame in which a frame phase synchronization circuit according to the present invention performs frame phase synchronization.

FIG. 3 is a block diagram showing the configuration of a conventional frame phase synchronization circuit.

FIG. 4 is a diagram showing an example of a transmission frame in which a conventional frame phase synchronization circuit performs frame phase synchronization.

[Explanation of symbols]

1. Subframe phase detection circuit 2 Write control circuit 3 Write counter 4 Buffer memory 5 Read counter 6 Readout control circuit 7 Phase comparison circuit 9 Demultiplexing circuit 10 Subframe type identification circuit 11a, 11b Selector circuit

Claims (1)

[Claims] Claim 1: Digital time division multiplexing in which n (n is single or plural, the same shall apply hereinafter) subframe signals are multiplexed within a transmission frame signal with arbitrary relative frame phases to the transmission frame phase. In the frame phase synchronization circuit that synchronizes the frame phase of frame signals, a demultiplexing circuit that multiplexes and demultiplexes signals in the subframe signal area in a ratio of 1:n and a subframe type identification circuit that identifies the type of subframe signal are provided. A subframe phase detection circuit that detects the relative phase of the subframe signal with respect to the frame phase, a buffer memory that stores the subframe signal, a write counter that generates a write address for the buffer memory, a write control circuit that controls the write counter, and a read buffer memory. It consists of a read counter that generates an address, a read control circuit that controls the read counter, and a phase comparison circuit that compares the write address/read address of the buffer memory, and is necessary when there is only one subframe signal in the transmission frame. n frame phase synchronization sections each having a processing capacity of 1/n of the processing capacity are arranged in parallel, and a write address and a read address of the buffer memory are respectively selected according to the subframe type in the second to nth frame phase synchronization sections. A selector circuit is provided, and the subframe type identification circuit identifies whether the number n of multiplexed subframe signals is 1 or 2 or more, and synchronizes the frame phase of n subframe signals having arbitrary relative phases. Features a frame phase synchronization circuit.