JPH04293170A - Wiring processor of automatic design device for multilayer printed wiring board - Google Patents

Abstract

PURPOSE:To improve the wiring containing ratio and also, to execute the mounting with high density by performing a wiring processing by considering a necessary minimum gap value between each element. CONSTITUTION:In addition to storage parts 1, 2 and 4 for storing parts information, fundamental definition information, connecting information, etc., respectively, a storage part 3 is provided, gap values to be held between each element are stored and held, and by taking all these gap values into consideration, free line information 6 and free via information 7 are generated as a pre-processing of a wiring processing, and based on these free line information 6 and free via information 7, the wiring processing between two points to be connected is executed. These free line information 6 and free via information 7 are information for expressing the part in which a line or a via can be formed in a wiring running axis by a start point - an end point, and by such an expression format, the amount of information becomes small, and a calculation load required for the wiring processing can be reduced. Accordingly, the wiring processing using the minimum gap value corresponding the kind of each element of a land, a line, a via, etc., placed on the multilayer printed circuit and the sequence of a circuit can be executed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring processing device for an automatic multilayer printed wiring board design device.

With the demand for smaller size, higher speed, and multifunctionality of various electronic devices, semiconductor devices are becoming faster and more highly integrated. Moreover, the packages are becoming smaller and have more terminals, and are not only suitable for insertion mounting of DIP and PGA, but also for SMD.
Surface mounting methods such as these are also becoming widely used.

[0003] Printed wiring boards that mount such packages are required to have higher wiring capacity and higher quality due to higher density and multilayering, and in response to new products being released one after another, The work burden on design departments is increasing as delivery times for printed wiring board design work are shortened. In order to reduce such work burden, automatic design equipment has been introduced at design sites, and there is a demand for automatic design equipment that can realize high-density wiring and perform high-speed processing.

0004

2. Description of the Related Art Generally, an automatic multilayer printed wiring board design apparatus is composed of a system controller, a display, a keyboard, a magnetic disk drive, a tablet, and the like. Designers can proceed with their work in an interactive manner by using a tablet to select commands, desired positions, etc. on the display screen, or by key-inputting appropriate information in response to messages. A registration function for frequently used parts and highly versatile patterns, an editing function for adding and deleting patterns, and moving a certain wired part or pattern to another position, and a designation function for a board on which parts have been placed. It has various functions such as an automatic wiring processing function that sequentially automatically wires between two points.

The automatic wiring function described above is a function that connects lands on which components are mounted, or lands and vias, which are interlayer communication patterns, by appropriately arranging vias and lines, which are interconnection patterns within the same layer. Yes, and interference with existing elements (in this specification, lines, lands, vias, pre-designated wiring prohibited areas, etc.) that will be an obstacle for lines and vias to be formed (arranged). It is necessary to form the lines and vias while maintaining a gap equal to or greater than a predetermined gap value.

Generally, the minimum gap value required between each element (line-to-line, line-to-land, line-to-via, via-to-via, etc.) is unique to each element, and A series of circuits (T
TL, ECL, etc.).

[0007] Conventionally, the value of the minimum gap unique between each element is uniformly fixed without consideration, that is, the value is set as a value greater than or equal to the largest of the minimum gap values unique to each element. , Wiring processing is being carried out.

[0008] Furthermore, in consideration of the sizes of lands and vias and the width of lines, positions where lines can be formed and positions where vias can be formed are fixedly set in advance so that a predetermined gap value or more is maintained, and a wiring model is created. By forming a wiring model and performing wiring processing based on this wiring model, calculations for maintaining detailed gap values can be omitted.

[0009]

[Problem to be solved by the invention] However, in recent years, the use of surface mount components has been increasing, and due to the demand for higher density, the terminal pitch of surface mount components tends to be narrower, and the vias are also becoming smaller. In the above-mentioned conventional technology, the gap value between each element is set unnecessarily wide, so there is a problem that there is a limit to the improvement of the wiring accommodation rate.

[0010] The present invention has been made in view of the above points, and its purpose is to improve the wiring accommodation rate by implementing wiring processing in consideration of the minimum gap value required between each element. In addition, it is an object of the present invention to provide a wiring processing device for an automatic multilayer printed wiring board design device that can perform wiring processing at high speed.

[0011]

[Means for Solving the Problems] The present invention will be explained with reference to the principle configuration diagram shown in FIG. 1.

The wiring processing device of this multilayer printed wiring board automatic design system assumes a plurality of wiring running axes arranged at predetermined intervals for each layer of the multilayer printed wiring board, and the wiring running axes are arranged perpendicularly to each other. This is a device that processes wiring between two points to be connected using layers and Y layers.

This wiring processing device includes first to tenth storage units 1 to 10, and first to fourth storage units 1 to 10.
-4 store various types of information that are set in advance or generated in various design processes performed before processing by this wiring processing device.

That is, the first storage section 1 stores component information including the positions and shapes of lands for mounting components. The second storage unit 2 stores basic definition information including via positions and wiring prohibited areas. The third storage unit 3 stores the gap value that should be maintained between two elements among a plurality of elements including lines, lands, vias, and wiring prohibited areas.
Gap value definition information set respectively corresponding to a plurality of net codes assigned according to the element series is stored. The fourth storage unit 4 stores a plurality of pieces of connection information about two points to be connected together with the corresponding net codes.

The fifth to ninth storage units 5 to 9 store various types of intermediate information generated within this wiring processing device, and the tenth storage unit 10 stores the results of wiring processing by this wiring processing device. is stored as information.

[0016] Then, this wiring processing device removes, from the wiring running axis, a portion that is an obstacle to the wiring including the corresponding gap value, based on each information in the first to fifth storage units 1 to 5. Empty line information generation unit 11 that generates empty line information expressing the part of the wiring running axis where a line can be formed in terms of start point and end point for the X layer and Y layer used for connection, and stores it in the sixth storage unit 6. and an empty via information generation unit 12 that generates empty via information indicating a position where via formation is possible, expressed in a format similar to the empty line information, and stores it in the seventh storage unit 7;
Based on the information in the fourth, sixth, and seventh storage units 4, 6, and 7, wiring is performed between two points to be connected, outputting wiring result information, and wiring for the formed lines and vias. The wiring processing section 16 additionally stores line/via information in the fourth storage section 4.

[0017] The empty line information generation unit 11 generates information based on the information in the first to third and fifth storage units 1 to 3, 5.
an empty line deletion range information generation unit 13 that generates empty line deletion range information expressing a wiring impossible area with lands and vias as obstacles as a start point to an end point with respect to the wiring running axis, and stores the empty line deletion range information in an eighth storage unit 8; , based on the information in the first to third and fifth storage units 1 to 3, and 5, a wiring possible area with elements other than lands and vias as obstacles is expressed as a starting point to an ending point with respect to the wiring running axis. Generate master empty line information,
Master empty line information generation unit 14 stored in the ninth storage unit 9
and a working empty line information generation unit 15 that generates the empty line information based on the information in the fourth, eighth, and ninth storage units 4, 8, and 9, and stores it in the sixth storage unit 6. It consists of

Furthermore, the wiring processing unit 16 is configured to sequentially perform wiring processing so that pieces of connection information in the fourth storage unit 4 to which the same net code is assigned are consecutive. .

[0019]

[Operation] According to the present invention, gap values to be maintained between each element are stored and maintained, and empty line information and empty via information are generated as pre-processing for wiring processing, taking all these gap values into consideration. Based on this empty line information and empty via information, wiring processing between two points to be connected is performed. As mentioned above, this empty line information and empty via information is information that expresses the part of the wiring running axis where a line or via can be formed as a starting point to an ending point, and this type of expression reduces the amount of information. , the calculation load required for wiring processing can be reduced.

In addition, when generating empty line information, by having master empty line information and empty line deletion range information, if there is no change in each gap value from the previous wiring processing, this master empty line information and the empty line deletion range information are used. The information used in the previous wiring process can be used without newly generating empty line deletion range information, and the time required to generate empty line information can be significantly shortened. Since the wiring process is performed sequentially so that the same net code is assigned consecutively, the chances of diversion as mentioned above increase, and the overall processing time can be significantly shortened. It is possible.

[0021]

EXAMPLES The present invention will be explained in detail below based on examples.

First, the gap value definition information stored in the third storage section 3 in FIG. 1 will be explained. In general, the minimum gap required between each element (line-to-line, line-to-land, line-via, land-via, line-prohibited area, line-to-blind hole, line-SMD terminal, etc.) As described above, the value is unique to each circuit, and also varies depending on the series of circuits (TTL, ECL, etc.) formed by lines to be formed. Therefore, in this embodiment, patterns such as lines and vias formed by wiring processing are classified into each series, and a net code is assigned to each series as shown in FIG. Specifically, these net codes are stored in correspondence with connection information about two points to be connected in the fourth storage unit 4 in FIG.

An example of gap value definition information is shown in FIG. That is, it is matrix-like information in which gap values to be maintained between each element are respectively set corresponding to the net code.

For example, if the element to be wired is a line and its net code is B, and the obstacle is a line with net code A, in the line corresponding to line-line, the net code is Since the one corresponding to A is "185" and the one corresponding to net code B is "200", the larger one of these, that is, "200" is adopted as the gap value. In this way, the larger gap value is selected by comparing the type of element to be wired and the net code, and the gap value extracted based on the type of element to be an obstacle and the net code. In this embodiment, this gap value definition information can be set for each layer.

The structure of the empty line information generated by the empty line information generating section 11 in FIG. 1 and stored in the sixth storage section 6 will be explained with reference to FIGS. 4 to 6.

FIG. 4(A) shows a layer corresponding to the X layer of the multilayer printed wiring board, and FIG. 4(B) shows a layer corresponding to the Y layer. be. Each layer has
As shown in the figure, a plurality of wiring running axes (wiring traces) T are assumed to be arranged at predetermined intervals, and the wiring traces T in the X and Y layers are orthogonal to each other. . The wiring process is performed using two layers such as the X layer and the Y layer.

In the same figure, squares indicate lands, circles indicate vias, and thick solid lines indicate lines. S indicates the starting point of the wiring,
E indicates the end point of the wiring. Note that the wavy line is an empty line area, that is, an area where a line can be formed.

The process of generating empty line information will be explained with reference to FIG. In the same figure, T1 to T5 indicate wiring traces, and vias V1 to V4 are formed as obstacles that have already been routed or set, and V
It is assumed that lines L1 and L2 connecting vias V1 and V2 are formed, and a line L3 connecting vias V3 and V4 is formed. Also, let A be the net code of the series whose start and end points are lands S1 and E1, and V1 - L1
Let B be the net code of the pattern consisting of -L2 -V2, and C be the net code of the pattern consisting of V3 -L3 -V4.

First, the entire range on each wiring trace T1 to T5 is initially set as a line formable area. Next, land S1, which is the starting point of the wiring, and land E1, which is the ending point, are not used as obstacles, and other vias V1 to
Using V4 and lines L1 to L3 as obstacles, portions where wiring is impossible due to these obstacles are deleted from the line formable area for each of the wiring traces T1 to T5. Specifically, the obstacle in V1 is a via;
Since the net code is B, the gap value is net code A.
The larger value of the line-via gap and the line-via gap of net code B is adopted, and this gap value is set around the via V1. This image is shown in dotted lines in the figure. The area indicated by the dotted line is the wiring trace T1
~T3 overlaps over a certain range, so a line for connecting S1 and E2 cannot be placed in this overlapping range. Therefore, each wiring trace T1
Empty line information is generated by deleting the portion included in the region indicated by the dotted line ~T3.

FIG. 6 shows a specific structure of the empty line information generated as described above, and corresponds to FIG. 4. That is, the empty line information is composed of X-direction trace management information (A), Y-direction trace management information (B), and empty line range information (C). The X and Y direction management information (A) and (B) are information in which pointers are set corresponding to the identification of each wiring trace for the X layer and Y layer, and the empty line range information (C) is information for each wiring trace. This is information in which a plurality of starting point-to-end point coordinate values (X coordinate value for the X layer and Y coordinate value for the Y layer) are set in accordance with the number of obstacles. The pointers of the X and Y direction trace management information (A) and (B) indicate the address where the first one of the corresponding start point-end point coordinate values of the empty line range information (C) is set.

In addition, the empty line range information (C) stores a pointer indicating the setting position of the next information in the same wiring trace corresponding to each start point-end point coordinate value, and the address indicated by this pointer By sequentially tracking the traces, it is possible to extract multiple start point-end point coordinate values within the same wiring trace. In addition, the pointer corresponding to the last start point-end point coordinate value within the same wiring trace is "
0'' to indicate that this is the last.

FIGS. 7 and 8 are diagrams for explaining the structure of the empty via information generated by the empty via information generating section 12 in FIG. 1 and stored in the seventh storage section 7. FIG. This empty via information includes layers in the X direction (layer 1, layer 3,
..., layer n-1) management information (A), Y direction layer (layer 2, layer 4)
, ..., layer n) management information (B), and empty via range information (C
). Its contents have exactly the same structure as the above-mentioned empty line information.

However, the empty line information only needs to be generated for the two layers (X, Y layers) used for wiring, but the empty via information is generated for all the through vias as shown in FIG. When forming interlayer vias for layers, it is necessary to consider obstacles for each layer including the layer intervening between the two layers, so the difference is that information for all of these layers is set. . The reason for this configuration is that the amount of information is smaller than if the via formation possible positions are individually held as (X, Y) coordinate values. Therefore, a position where a via can actually be formed is a position where the unobstructed portions of each wiring trace of each X layer and Y layer intersect.

If the above-mentioned empty line information is generated simply by sequentially removing obstacles from the wiring trace as explained with reference to FIG. 5, it is necessary to recreate the empty line information each time wiring processing is performed. occurs.

That is, in FIG. 9, V1 and V2 are vias that have been wired, L1 is a line that has been wired, and S1 and E
1, S2, and E2 are lands, and when wiring between S2 and E2 is performed after wiring between S1 and E1, as empty line information when wiring between S1 and E1, S1 and E1 are obstacles. V1 without considering it as
, V2 , L1 and S2 , E2 need to be generated as obstacles. However, after wiring processing between S1 and E1, as shown in FIG. 10, obstacles S1, L1, V1, L2, V2, L3,
In addition to adding E1, S2 and E, which were obstacles last time,
2 is not considered an obstacle. Therefore, the previous empty line information cannot be used.

However, generating this empty line information every time wiring processing is performed requires a large calculation load and causes a delay in processing. 11 is configured as described above to cope with this problem. That is, master empty line information and empty line deletion range information are generated, and empty line information is generated based on these.

The master empty line information has the same structure as the empty line information shown in FIG. 6, and since lands and vias may become starting and ending points during wiring processing, other elements excluding these are This is information that expresses the wiring possible area as a starting point to an ending point for each wiring trace, reflecting the area as an obstacle. Note that the master empty line information is information regarding the entire area of the printed wiring board.

The structure of the empty line deletion range information is shown in FIG. This empty line deletion range information is information that expresses, for each land and via, the part of the wiring trace where the corresponding land or via overlaps as a start point - end point, and includes land/via information (A) and deletion range information ( B). In the land/via information, a pointer indicating the address of the deletion range information (B) is set for each land (via), and the deletion range information (B) includes the layer number, trace number, deletion start point - end point coordinate value. , and a pointer indicating the storage address of the next information. When there is no next information for one line or via, "0" is set, indicating that this is the last information.

This empty line deletion range information will be specifically explained with reference to FIGS. 12 and 13. In FIG. 12, T
1 to T5 are wiring traces, L is a land, and d is a required gap value. The layer number is N.

For wiring trace T1, X1 −X
2 range is X3 - X4 for wiring trace T2
The range of is X5 -X for wiring trace T3
6 range is X7 − for wiring trace T4
The range of X8 becomes X9 for wiring trace T5.
-X10 is the portion substantially occupied by this land L. In this example, empty line deletion range information is expressed as shown in FIG. 13.

That is, a pointer for land L is set in land/via information (A), and deletion range information (B)
The first information (N, T1
, X1 - X2) are set, and a pointer indicating the address where the next information is stored is also set. The second information (N, T2, X3
-X4) is set, and then the fifth information (N, T5, X9 -X10) is set, and this is the end of the information about land L1, so "0" is set as the pointer. .

The overall process will be explained with reference to the process flowchart shown in FIG.

First, one piece of connection information is extracted from the fourth storage unit 4 (Step 1, hereinafter abbreviated as ST), and it is determined whether wiring processing for all connection information has been completed (Step 1).
T2). In ST2, if there are unwired lines, it is determined whether the master empty line information used in the previous wiring process can be used as is (ST
3), that is, it is determined whether the gap value or the line width related to the line has changed, and if there is a change, the component information in the first storage unit 1 and the basic definition in the second storage unit 2 are determined. master empty line information is regenerated based on the information, the gap value definition information in the third storage section 3, and the wiring line/via information in the fifth storage section 5, and is stored in the ninth storage section 9 (ST4).

In ST3, if there is no change, that is, if the previously used master empty line information can be used as is, the process proceeds to ST5 without executing ST4. In ST5, ST
Elements corresponding to the start and end points to be connected extracted in step 1 (
land or via), and then generates empty line information based on the empty line deletion range information from which elements regarding the start and end points to be connected have been deleted and the master empty line information in the ninth storage unit 9. and sets it in the sixth storage unit 6 (ST6).

Next, it is determined whether the empty via information used in the previous wiring process can be used, that is, it is determined whether the gap value or the size of the via has changed (
ST7), if there is a change, the component information in the first storage section 1, the basic definition information in the second storage section 2, the gap value definition information in the third storage section 3, and the wiring line and Based on the via information, empty via information is generated and stored in the seventh storage section 7 (ST8). In ST7, if there is no change, that is, if the empty via information used in the previous wiring process can be used as is, proceed to ST9 without executing ST8.
Proceed to.

In ST9, based on the empty line information in the sixth storage section 6 and the empty via information in the seventh storage section 7, wiring processing is performed between the start and end points to be connected, and the newly formed lines and vias are connected to the fifth storage section 7. The data is stored in the storage unit 5 (ST9). Next, it is determined whether the wiring was successful or not (ST10), and if the wiring was successful, the empty via information in the seventh storage section 7 and the empty via information in the ninth storage section are stored using the newly formed line via as an obstacle. 9 is added to the master empty line information (ST11), information about the newly formed via is added to the empty line deletion range information in the eighth storage section 8 (ST12), and the process returns to ST1. Even if wiring fails in ST10, the process returns to ST1.

[0047] Thereafter, these processes are repeated, and ST2
If it is determined that the wiring processing for all the connection information in the fourth storage section 4 has been completed, all the wiring processing results are stored in the tenth storage section 10 (ST13), and the processing ends.

In this embodiment, the connection information stored in the fourth storage unit 4 is classified by the same net code, and in ST1 of FIG. Information is extracted sequentially, and when the wiring processing for connection information classified into one net code is completed, connection information classified into other net codes is sequentially extracted, and this process is repeated thereafter. .

According to this embodiment, the empty line information and the empty via information have a configuration in which the wiring possible area for each wiring trace is expressed as a range from the starting point to the ending point, so that grid subdivision or semi-gridless wiring It has a structure that can be applied to cases in which the amount of information is small. In addition, when creating empty line information, master empty line information and empty line deletion range information are maintained, and master empty line information is used when the gap value or line width of a line does not change. does not need to be regenerated, so processing time can be shortened. Furthermore, by having empty line information and empty via information separately, line-related gap changes and via-related gap changes can be treated separately, making it possible to respond flexibly to changes in gap values, etc. .

[0050]

Effects of the Invention Since the present invention is constructed as detailed above, lands, lines, and
It becomes possible to perform wiring processing using a minimum gap value depending on the type of each element such as a via and the series of circuits, thereby improving the wiring accommodation rate of the printed wiring board and achieving high-density packaging. In addition, the expression format of the empty line information and empty via information used for wiring processing is simple, and the empty line information is generated rationally, so the overall calculation processing load is reduced and processing speed is increased. It also has the effect of being able to achieve this.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention.

FIG. 2 is a diagram showing an example of assigning a net code in the embodiment of the present invention.

FIG. 3 is a diagram showing an example of gap value definition information in the embodiment of the present invention.

FIG. 4 is an explanatory diagram of the structure of empty line information in the embodiment of the present invention.

FIG. 5 is an explanatory diagram of generation of empty line information in the embodiment of the present invention.

FIG. 6 is a configuration diagram of empty line information in the embodiment of the present invention.

FIG. 7 is an explanatory diagram of the structure of empty via information in the embodiment of the present invention.

FIG. 8 is a configuration diagram of empty via information in the embodiment of the present invention.

FIG. 9 is an explanatory diagram of problems in the empty line information generation process.

FIG. 10 is an explanatory diagram of problems in the empty line information generation process.

FIG. 11 is a configuration diagram of empty line deletion range information in the embodiment of the present invention.

FIG. 12 is a diagram illustrating a specific example of empty line deletion range information in the embodiment of the present invention.

FIG. 13 is a diagram illustrating a specific example of empty line deletion range information in the embodiment of the present invention.

FIG. 14 is a processing flowchart in an embodiment of the present invention.

[Explanation of symbols]

1 First storage section (parts information) 2 Second storage section (basic definition information) 3 Third storage section (gap value definition information) 4 Fourth storage section (connection information) 5 Fifth storage section (wiring line/via information) ) 6 Sixth storage section (empty line information) 7 Seventh storage section (empty via information) 8 Eighth storage section (empty line deletion range information) 9 Ninth storage section (master empty line information) 10 Tenth storage section ( (Wiring result information) 11 Empty line information generation section 12 Empty via information generation section 13 Empty line deletion range information generation section 14 Master empty line information generation section 15 Work empty line information generation section 16 Wiring processing section

Claims (3)

[Claims] Claim 1: A plurality of wiring running axes arranged at predetermined intervals are assumed for each layer of a multilayer printed wiring board, and two points to be connected using an X layer and a Y layer in which the wiring running axes are orthogonal to each other are assumed. A wiring processing device of a multilayer printed wiring board automatic design device that processes wiring between parts, the first storage unit (
1), a second storage section (2) storing basic definition information including via positions and wiring prohibited areas, and two elements among multiple elements including lines, lands, vias, and wiring prohibited areas. a third storage unit (3) storing gap value definition information in which gap values to be maintained between are respectively set corresponding to a plurality of net codes assigned according to a series of elements;
and a fourth storage unit (4
) and a fifth storage unit (
5) Based on each of the information in the first to fifth storage units (1 to 5), remove the portion that is an obstacle to the wiring including the corresponding gap value from the wiring running axis, and remove the portion of the wiring running axis from the wiring running axis. an empty line information generation unit (11) that generates empty line information expressing a part where a line can be formed as a starting point and an ending point for each of the X layer and Y layer, and stores it in a sixth storage unit (6); an empty via information generating unit (12) that generates empty via information indicating a position where via formation is possible, expressed in a format similar to the empty line information, and stores it in a seventh storage unit (7); Based on the information in the sixth and seventh storage units (4, 6, 7), it processes the wiring between two points to be connected, outputs the wiring result information, and connects the wiring lines and vias to the formed lines and vias. A wiring processing device for an automatic multilayer printed wiring board design apparatus, comprising: a wiring processing section (16) for additionally storing via information in the fourth storage section (4). 2. A wiring processing device for an automatic multilayer printed wiring board design device according to claim 1, wherein land, an empty line deletion range information generating unit (13) that generates empty line deletion range information expressing a wiring impossible area with a via as an obstacle as a start point to an end point with respect to the wiring running axis, and stores the empty line deletion range information in an eighth storage unit (8); ), and based on each information in the first to third and fifth storage units (1 to 3, 5), a wiring possible area with elements other than lands and vias as obstacles is determined from the starting point - with respect to the wiring running axis. a master empty line information generation unit (14) that generates master empty line information expressed at the end point and stores it in a ninth storage unit (9); and the fourth, eighth, and ninth storage units (4, 8, 9). ) The empty line information generating unit (11) is configured from a working empty line information generating unit (15) that generates the empty line information and stores it in the sixth storage unit (6). A wiring processing device for an automatic multilayer printed wiring board design device, which is characterized by: 3. In the wiring processing device for an automatic multilayer printed wiring board design device according to claim 2, among the connection information in the fourth storage unit (4), pieces of connection information to which the same net code is assigned are consecutive. A wiring processing device for an automatic multilayer printed wiring board design device, characterized in that wiring processing is performed sequentially.