CN105792532A - Tear drop selecting method and PCB - Google Patents
Tear drop selecting method and PCB Download PDFInfo
- Publication number
- CN105792532A CN105792532A CN201610301319.7A CN201610301319A CN105792532A CN 105792532 A CN105792532 A CN 105792532A CN 201610301319 A CN201610301319 A CN 201610301319A CN 105792532 A CN105792532 A CN 105792532A
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- tear
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- drop shape
- impedance
- cabling
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0002—Apparatus or processes for manufacturing printed circuits for manufacturing artworks for printed circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/07—Electric details
- H05K2201/0776—Resistance and impedance
- H05K2201/0784—Uniform resistance, i.e. equalizing the resistance of a number of conductors
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Structure Of Printed Boards (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
Abstract
The invention provides a tear drop selecting method and a PCB, and the method comprises the steps: determining the impedance of a wire to be arranged on a PCB wiring layer; obtaining at least two shapes of to-be-arranged tear drops; respectively carrying out the simulation of the link impedance for the tear drops in each shape according to the impedance of the wire; enabling the tear drop shape in a simulation result to serve as the selected target tear drop shape when the link impedance is the smoothest; and arranging the tear drops corresponding to the target tear drop shape on the wire of the PCB wiring layer. According to the scheme of the invention, the method carries out the simulation of the link impedance of the tear drops in each shape according to the impedance of the wire through obtaining at least two shapes of the tear drops. In order to guarantee the fewer resonance points of the link impedance, the method should select the tear drop shape to serve as the selected target tear drop shape when the link impedance is the smoothest, so as to employ the tear drops corresponding to the target tear drop shape for arrangement, and to reduce the impact of tear drops on the impedance continuity of the wire.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly to a kind of tear system of selection and PCB (PrintedCircuitBoard, printed circuit board).
Background technology
Along with the arrival in cloud computing epoch, server quickly grow emergence, in the motherboard design of server, signal rate is more and more higher, high speed signal to the demand of signal integrity also in continuous lifting.
In server master board designs, in order to make pad firmer, it is prevented that during machinery making sheet, pad and wire is separated, often arranges a transition region with copper film between the pads and wires, is referred to as tear.
Owing to the shape of tear is varied, arranging difform tear between the pads and wires, they are different on the impact of the impedance continuity of cabling, therefore, how to select the tear of suitable shape, become urgent problem.
Summary of the invention
Embodiments provide a kind of tear system of selection and PCB, to select the tear of suitable shape.
First aspect, embodiments provides a kind of tear system of selection, including:
Determine the impedance of the required cabling arranged on PCB layout layer；
Obtain at least two shape of the required tear arranged；
Impedance according to described cabling, the tear being respectively directed to each shape carries out the emulation of link impedance；
By in simulation result using tear-drop shape corresponding time the most smooth for link impedance as select target tear-drop shape；
Tear corresponding for described target tear-drop shape is arranged on the described cabling of PCB layout layer.
Preferably, at least two shape of described tear includes: square and circular.
Preferably, select described target tear-drop shape be square time, described tear corresponding for described target tear-drop shape is arranged on the described cabling of PCB layout layer before, farther include:
Calculate the length and width of square tear；According to the execution of this length and width is described, tear corresponding for described target tear-drop shape is arranged on the described cabling of PCB layout layer；
The length of square tear is calculated by equation below:
L=o+s+e+a
Wherein, L is for characterizing the length of square tear, and o is for characterizing the monolateral size that solder mask is windowed, and s is used for characterizing welding resistance aligning accuracy, and e is for characterizing the etch quantity of outer-layer circuit, and a is used for characterizing safe clearance；
The width of square tear is calculated by equation below:
W=e+u+m
Wherein, W is for characterizing the width of square tear, and e is for characterizing the etch quantity of outer-layer circuit, and u is used for characterizing microetch amount, and m is used for characterizing junction live width minima.
Preferably, select described target tear-drop shape be circle time, described tear corresponding for described target tear-drop shape is arranged on the described cabling of PCB layout layer before, farther include:
Calculate the diameter of circular tear；According to the execution of this diameter is described, tear corresponding for described target tear-drop shape is arranged on the described cabling of PCB layout layer；
The diameter of circular tear is calculated by equation below:
R=[e+u+m, o+s+e+a]
Wherein, o is for characterizing the monolateral size that solder mask is windowed, and s is used for characterizing welding resistance aligning accuracy, and e is for characterizing the etch quantity of outer-layer circuit, and a is used for characterizing safe clearance；U is used for characterizing microetch amount, and m is used for characterizing junction live width minima.
Preferably, a value is 2mil-3mil；M value is 4mil.
Preferably,
When the impedance of described cabling is 100ohm, described target tear-drop shape is circular；
Preferably,
When the impedance of described cabling is 90ohm, described target tear-drop shape is square.
Second aspect, the embodiment of the present invention additionally provides a kind of PCB, including the tear that the tear-drop shape utilizing any of the above-described described tear system of selection to select is arranged.
Embodiments provide a kind of tear system of selection and PCB, by getting at least two shape of tear, the tear of each shape is carried out the emulation of link impedance by the impedance according to cabling, in order to ensure that resonance point occurs in the less of link impedance, the tear-drop shape corresponding time the most smooth of link impedance should be selected as the target tear-drop shape selected, it is arranged with the tear utilizing this target tear-drop shape corresponding, thus reducing the tear impact on the impedance continuity of cabling.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is a kind of method flow diagram that one embodiment of the invention provides；
Fig. 2 is the another kind of method flow diagram that one embodiment of the invention provides；
Fig. 3 is the emulation schematic diagram that the cabling to 100ohm that one embodiment of the invention provides carries out different tear-drop shape；
Fig. 4 is the emulation schematic diagram that the cabling to 90ohm that one embodiment of the invention provides carries out different tear-drop shape；
Fig. 5 is the schematic diagram of the square tear of the layout that one embodiment of the invention provides；
Fig. 6 is the schematic diagram of the circular tear of the layout that one embodiment of the invention provides.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearly; below in conjunction with the accompanying drawing in the embodiment of the present invention; technical scheme in the embodiment of the present invention is clearly and completely described; obviously; described embodiment is a part of embodiment of the present invention, rather than whole embodiments, based on the embodiment in the present invention; the every other embodiment that those of ordinary skill in the art obtain under the premise not making creative work, broadly falls into the scope of protection of the invention.
As it is shown in figure 1, embodiments provide a kind of tear system of selection, the method may comprise steps of:
Step 101: determine the impedance of the required cabling arranged on PCB layout layer；
Step 102: obtain at least two shape of the required tear arranged；
Step 103: the impedance according to described cabling, the tear being respectively directed to each shape carries out the emulation of link impedance；
Step 104: by simulation result using tear-drop shape corresponding time the most smooth for link impedance as select target tear-drop shape；
Step 105: tear corresponding for described target tear-drop shape is arranged on the described cabling of PCB layout layer.
According to such scheme, by getting at least two shape of tear, the tear of each shape is carried out the emulation of link impedance by the impedance according to cabling, in order to ensure that resonance point occurs in the less of link impedance, the tear-drop shape corresponding time the most smooth of link impedance should be selected as the target tear-drop shape selected, it is arranged with the tear utilizing this target tear-drop shape corresponding, thus reducing the tear impact on the impedance continuity of cabling.
In an embodiment of the invention, the shape of tear can include at least two, and wherein, this at least two shape may include that square and circular.
In an embodiment of the invention, the size of tear is also required to meet certain condition just passable, time otherwise smaller, its original function disconnected that avoids contact with cannot be realized, larger in size, other components and parts may be impacted.Therefore,
In an embodiment of the invention, select described target tear-drop shape be square time, described tear corresponding for described target tear-drop shape is arranged on the described cabling of PCB layout layer before, farther include:
Calculate the length and width of square tear；According to the execution of this length and width is described, tear corresponding for described target tear-drop shape is arranged on the described cabling of PCB layout layer；
The length of square tear is calculated by equation below:
L=o+s+e+a
Wherein, L is for characterizing the length of square tear, and o is for characterizing the monolateral size that solder mask is windowed, and s is used for characterizing welding resistance aligning accuracy, and e is for characterizing the etch quantity of outer-layer circuit, and a is used for characterizing safe clearance；
The width of square tear is calculated by equation below:
W=e+u+m
Wherein, W is for characterizing the width of square tear, and e is for characterizing the etch quantity of outer-layer circuit, and u is used for characterizing microetch amount, and m is used for characterizing junction live width minima.
In an embodiment of the invention, select described target tear-drop shape be circle time, described tear corresponding for described target tear-drop shape is arranged on the described cabling of PCB layout layer before, farther include:
Calculate the diameter of circular tear；According to the execution of this diameter is described, tear corresponding for described target tear-drop shape is arranged on the described cabling of PCB layout layer；
The diameter of circular tear is calculated by equation below:
R=[e+u+m, o+s+e+a]
Wherein, o is for characterizing the monolateral size that solder mask is windowed, and s is used for characterizing welding resistance aligning accuracy, and e is for characterizing the etch quantity of outer-layer circuit, and a is used for characterizing safe clearance；U is used for characterizing microetch amount, and m is used for characterizing junction live width minima.
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with drawings and the specific embodiments, the present invention is described in further detail.
As in figure 2 it is shown, embodiments provide a kind of tear system of selection, the method may comprise steps of:
Step 201: determine the impedance of the required cabling arranged, 100ohm and 90ohm on PCB layout layer.
Owing to the impedance of cabling is different, it is possible to the shape of the tear of required selection is different, therefore, it can the cabling of the cabling with 100ohm impedance and 90ohm impedance and illustrates respectively.
In an embodiment of the invention, in order to ensure the accurate selection of the tear of suitable shape, it is necessary to ensure when walking that line impedence is different and other conditions carry out all identical.Such as, after determining away line impedence, it is determined that on cabling, the position of mended tear is identical.
Tear is the load degree of taking between pad and wire or wire and guide hole.The purpose arranging tear is when circuit board is subject to the collision of huge external force, it is to avoid when circuit board is subject to the collision of huge external force, and the contact point of wire and pad or wire and guide hole disconnects, it is possible to make PCB seem more attractive in appearance.And the position of tear can determine according to cabling wiring on wiring layer.
Step 202: obtain two kinds of shapes of the required tear arranged: square and circular.
In the present embodiment, the shape of tear can also include polygon, irregular shape etc., wherein, can be more convenient and attractive in appearance when tear mended on circuit boards for square and circular tear, therefore, for square and circular illustrate.
Step 203: the cabling according to different impedances, is respectively directed to square tear and circular tear carries out the emulation of link impedance.
In the present embodiment, when emulating, it is possible to the link impedance without tear cabling is emulated, there is tear and impact on link impedance during without tear to determine simultaneously.
Can need to do following emulation according to above-mentioned cabling and tear-drop shape below:
1, the cabling that impedance is 100ohm is carried out respectively the link impedance emulation without tear, square tear and circular tear.
2, the cabling that impedance is 90ohm is carried out respectively the link impedance emulation without tear, square tear and circular tear.
For above-mentioned emulation 1, simulation result refer to Fig. 3, can know according to this simulation result:
When designing without tear, the resonance point that the existence of its link impedance is bigger, therefore, there is tear design relative to without tear design, the impact of link impedance is less；
For the design of square tear and circular tear design it can be seen that when the impedance of cabling is 100ohm, circular tear is relative to square tear, and the impact of link impedance is less.
For above-mentioned emulation 1, drawing following result: when the impedance of cabling is 100ohm, the target tear-drop shape of selection is circular.
For above-mentioned emulation 2, simulation result refer to Fig. 4, can know according to this simulation result:
When designing without tear, the resonance point that the existence of its link impedance is bigger, therefore, there is tear design relative to without tear design, the impact of link impedance is less；
For the design of square tear and circular tear design it can be seen that when the impedance of cabling is 90ohm, square tear is relative to circular tear, and the impact of link impedance is less.
For above-mentioned emulation 2, drawing following result: when the impedance of cabling is 90ohm, the target tear-drop shape of selection is square.
Step 204: using tear-drop shape corresponding time the most smooth for simulation result link impedance as the target tear-drop shape selected, when target tear-drop shape is square, performs step 205；When target tear-drop shape is circular, perform step 207.
The size of tear is also required to meet certain condition just passable, time otherwise smaller, its original function disconnected that avoids contact with cannot be realized, larger in size, other components and parts may be impacted.Accordingly, it would be desirable to need to be defined to the size of tear.
Step 205: calculate the length and width of square tear.
In the present embodiment, it is possible to calculate the length and width of square tear in the following way:
The length of square tear is calculated by equation below:
L=o+s+e+a (1)
Wherein, L is for characterizing the length of square tear, and o is for characterizing the monolateral size that solder mask is windowed, and s is used for characterizing welding resistance aligning accuracy, and e is for characterizing the etch quantity of outer-layer circuit, and a is used for characterizing safe clearance；
The width of square tear is calculated by equation below:
W=e+u+m (1)
Wherein, W is for characterizing the width of square tear, and e is for characterizing the etch quantity of outer-layer circuit, and u is used for characterizing microetch amount, and m is used for characterizing junction live width minima.
Wherein, a value can be 2mil-3mil；M value can be 4mil.
Step 206: according to this length and width, is arranged on the cabling of PCB layout layer by square tear, terminates.
Refer to Fig. 5, be arranged in the schematic diagram on cabling and via for square tear.
Step 207: calculate the diameter of circular tear.
In the present embodiment, it is possible to calculate the diameter of circular tear in the following way:
The diameter of circular tear is calculated by equation below:
R=[e+u+m, o+s+e+a] (3)
Wherein, o is for characterizing the monolateral size that solder mask is windowed, and s is used for characterizing welding resistance aligning accuracy, and e is for characterizing the etch quantity of outer-layer circuit, and a is used for characterizing safe clearance；U is used for characterizing microetch amount, and m is used for characterizing junction live width minima.
Wherein, a value can be 2mil-3mil；M value can be 4mil.
Step 208: according to this diameter, is arranged on the cabling of PCB layout layer by circular tear, terminates.
Refer to Fig. 6, be arranged in the schematic diagram on cabling and via for circular tear.
The embodiment of the present invention additionally provides a kind of PCB, including: utilize the tear that the tear-drop shape that in above-described embodiment, arbitrary described tear system of selection selects is arranged.
In sum, each embodiment of the present invention at least can realize following beneficial effect:
1, in embodiments of the present invention, by getting at least two shape of tear, the tear of each shape is carried out the emulation of link impedance by the impedance according to cabling, in order to ensure that resonance point occurs in the less of link impedance, the tear-drop shape corresponding time the most smooth of link impedance should be selected as the target tear-drop shape selected, it is arranged with the tear utilizing this target tear-drop shape corresponding, thus reducing the tear impact on the impedance continuity of cabling.
2, in embodiments of the present invention, by calculating its size for difform tear so that it is size meets certain condition, it is prevented that undersized cannot realize it and original avoid contact with some the function disconnected, the oversize problem that other components and parts are impacted.
The contents such as the information between each unit in said apparatus is mutual, execution process, due to the inventive method embodiment based on same design, particular content referring to the narration in the inventive method embodiment, can repeat no more herein.
It should be noted that, in this article, the relational terms of such as first and second etc is used merely to separate an entity or operation with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " includes ", " comprising " or its any other variant are intended to comprising of nonexcludability, so that include the process of a series of key element, method, article or equipment not only include those key elements, but also include other key elements being not expressly set out, or also include the key element intrinsic for this process, method, article or equipment.When there is no more restriction, statement " including " key element limited, it is not excluded that there is also other same factor in including the process of described key element, method, article or equipment.
One of ordinary skill in the art will appreciate that: all or part of step realizing said method embodiment can be completed by the hardware that programmed instruction is relevant, aforesaid program can be stored in the storage medium of embodied on computer readable, this program upon execution, performs to include the step of said method embodiment；And aforesaid storage medium includes: in the various media that can store program code such as ROM, RAM, magnetic disc or CD.
Last it should be understood that the foregoing is only presently preferred embodiments of the present invention, it is merely to illustrate technical scheme, is not intended to limit protection scope of the present invention.All make within the spirit and principles in the present invention any amendment, equivalent replacement, improvement etc., be all contained in protection scope of the present invention.
Claims (8)
1. a tear system of selection, it is characterised in that including:
Determine the impedance of the required cabling arranged on PCB layout layer；
Obtain at least two shape of the required tear arranged；
Impedance according to described cabling, the tear being respectively directed to each shape carries out the emulation of link impedance；
By in simulation result using tear-drop shape corresponding time the most smooth for link impedance as select target tear-drop shape；
Tear corresponding for described target tear-drop shape is arranged on the described cabling of PCB layout layer.
2. method according to claim 1, it is characterised in that at least two shape of described tear includes: square and circular.
3. method according to claim 2, it is characterised in that select described target tear-drop shape be square time, described tear corresponding for described target tear-drop shape is arranged on the described cabling of PCB layout layer before, farther include:
Calculate the length and width of square tear；According to the execution of this length and width is described, tear corresponding for described target tear-drop shape is arranged on the described cabling of PCB layout layer；
The length of square tear is calculated by equation below:
L=o+s+e+a
Wherein, L is for characterizing the length of square tear, and o is for characterizing the monolateral size that solder mask is windowed, and s is used for characterizing welding resistance aligning accuracy, and e is for characterizing the etch quantity of outer-layer circuit, and a is used for characterizing safe clearance；
The width of square tear is calculated by equation below:
W=e+u+m
Wherein, W is for characterizing the width of square tear, and e is for characterizing the etch quantity of outer-layer circuit, and u is used for characterizing microetch amount, and m is used for characterizing junction live width minima.
4. method according to claim 2, it is characterised in that select described target tear-drop shape be circle time, described tear corresponding for described target tear-drop shape is arranged on the described cabling of PCB layout layer before, farther include:
Calculate the diameter of circular tear；According to the execution of this diameter is described, tear corresponding for described target tear-drop shape is arranged on the described cabling of PCB layout layer；
The diameter of circular tear is calculated by equation below:
R=[e+u+m, o+s+e+a]
Wherein, o is for characterizing the monolateral size that solder mask is windowed, and s is used for characterizing welding resistance aligning accuracy, and e is for characterizing the etch quantity of outer-layer circuit, and a is used for characterizing safe clearance；U is used for characterizing microetch amount, and m is used for characterizing junction live width minima.
5. the method according to claim 3 or 4, it is characterised in that a value is 2mil-3mil；M value is 4mil.
6. according to described method arbitrary in claim 1-5, it is characterised in that
When the impedance of described cabling is 100ohm, described target tear-drop shape is circular.
7. according to described method arbitrary in claim 1-5, it is characterised in that
When the impedance of described cabling is 90ohm, described target tear-drop shape is square.
8. a PCB, it is characterised in that include the tear utilizing the tear-drop shape that in the claims 1-7, arbitrary described tear system of selection selects to arrange.
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| CN201610301319.7A CN105792532B (en) | 2016-05-06 | 2016-05-06 | A kind of tear system of selection and PCB |
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| CN201610301319.7A CN105792532B (en) | 2016-05-06 | 2016-05-06 | A kind of tear system of selection and PCB |
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| CN105792532A true CN105792532A (en) | 2016-07-20 |
| CN105792532B CN105792532B (en) | 2018-05-08 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107493655A (en) * | 2017-08-28 | 2017-12-19 | 郑州云海信息技术有限公司 | The method and system that circuit easily fuses at a kind of solution DIP device solder joints |
| CN117371073A (en) * | 2023-10-07 | 2024-01-09 | 上海弘快科技有限公司 | Method for realizing chip packaging design tear drop |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102510676A (en) * | 2011-10-20 | 2012-06-20 | 东莞生益电子有限公司 | Method for adding teardrop in printed circuit board (PCB) during computer aided manufacturing (CAM) |
| CN102982199A (en) * | 2012-11-02 | 2013-03-20 | 中国兵器科学研究院 | Simulation method and device of optical lens |
| CN104994685A (en) * | 2015-07-13 | 2015-10-21 | 竞陆电子(昆山)有限公司 | PCB bonding pad/line connection structure |
-
2016
- 2016-05-06 CN CN201610301319.7A patent/CN105792532B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102510676A (en) * | 2011-10-20 | 2012-06-20 | 东莞生益电子有限公司 | Method for adding teardrop in printed circuit board (PCB) during computer aided manufacturing (CAM) |
| CN102982199A (en) * | 2012-11-02 | 2013-03-20 | 中国兵器科学研究院 | Simulation method and device of optical lens |
| CN104994685A (en) * | 2015-07-13 | 2015-10-21 | 竞陆电子(昆山)有限公司 | PCB bonding pad/line connection structure |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107493655A (en) * | 2017-08-28 | 2017-12-19 | 郑州云海信息技术有限公司 | The method and system that circuit easily fuses at a kind of solution DIP device solder joints |
| CN107493655B (en) * | 2017-08-28 | 2019-05-14 | 郑州云海信息技术有限公司 | It is a kind of to solve the method and system that route easily fuses at DIP device solder joint |
| CN117371073A (en) * | 2023-10-07 | 2024-01-09 | 上海弘快科技有限公司 | Method for realizing chip packaging design tear drop |
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| Publication number | Publication date |
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| CN105792532B (en) | 2018-05-08 |
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