JPH04293151A - 並列データ処理方式 - Google Patents

並列データ処理方式

Info

Publication number
JPH04293151A
JPH04293151A JP3057347A JP5734791A JPH04293151A JP H04293151 A JPH04293151 A JP H04293151A JP 3057347 A JP3057347 A JP 3057347A JP 5734791 A JP5734791 A JP 5734791A JP H04293151 A JPH04293151 A JP H04293151A
Authority
JP
Japan
Prior art keywords
tray
data
data processing
input
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3057347A
Other languages
English (en)
Japanese (ja)
Inventor
Hideki Kato
英樹 加藤
Hideki Yoshizawa
英樹 吉沢
Hiromoto Ichiki
宏基 市來
Daiki Masumoto
大器 増本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3057347A priority Critical patent/JPH04293151A/ja
Priority to EP92104904A priority patent/EP0504932A2/en
Publication of JPH04293151A publication Critical patent/JPH04293151A/ja
Priority to US08/261,889 priority patent/US5506998A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/10—Interfaces, programming languages or software development kits, e.g. for simulating neural networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Artificial Intelligence (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Evolutionary Computation (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Complex Calculations (AREA)
JP3057347A 1991-03-20 1991-03-20 並列データ処理方式 Withdrawn JPH04293151A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP3057347A JPH04293151A (ja) 1991-03-20 1991-03-20 並列データ処理方式
EP92104904A EP0504932A2 (en) 1991-03-20 1992-03-20 A parallel data processing system
US08/261,889 US5506998A (en) 1991-03-20 1994-06-17 Parallel data processing system using a plurality of processing elements to process data and a plurality of trays connected to some of the processing elements to store and transfer data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3057347A JPH04293151A (ja) 1991-03-20 1991-03-20 並列データ処理方式

Publications (1)

Publication Number Publication Date
JPH04293151A true JPH04293151A (ja) 1992-10-16

Family

ID=13053042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3057347A Withdrawn JPH04293151A (ja) 1991-03-20 1991-03-20 並列データ処理方式

Country Status (3)

Country Link
US (1) US5506998A (OSRAM)
EP (1) EP0504932A2 (OSRAM)
JP (1) JPH04293151A (OSRAM)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8510534B2 (en) 2002-05-24 2013-08-13 St-Ericsson Sa Scalar/vector processor that includes a functional unit with a vector section and a scalar section
JP2022169552A (ja) * 2017-12-12 2022-11-09 アマゾン テクノロジーズ インコーポレイテッド オンチップの計算ネットワーク
US12314837B2 (en) 2017-12-12 2025-05-27 Amazon Technologies, Inc. Multi-memory on-chip computational network

Families Citing this family (56)

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JPH076146A (ja) * 1993-06-18 1995-01-10 Fujitsu Ltd 並列データ処理システム
US6145071A (en) * 1994-03-03 2000-11-07 The George Washington University Multi-layer multi-processor information conveyor with periodic transferring of processors' states for on-the-fly transformation of continuous information flows and operating method therefor
JPH10506492A (ja) * 1995-07-21 1998-06-23 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ 高性能密度を有するマルチメディアプロセッサアーキテクチャ
US5943242A (en) 1995-11-17 1999-08-24 Pact Gmbh Dynamically reconfigurable data processing system
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
JP3136088B2 (ja) * 1996-02-22 2001-02-19 シャープ株式会社 データ処理装置及びデータ処理方法
GB2315888A (en) * 1996-07-31 1998-02-11 Ibm Controlling the degree of parallelism when performing parallel processing on an inherently serial computer program
US5778244A (en) * 1996-10-07 1998-07-07 Timeplex, Inc. Digital signal processing unit using digital signal processor array with recirculation
DE19651075A1 (de) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
DE19654593A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Umkonfigurierungs-Verfahren für programmierbare Bausteine zur Laufzeit
US6338106B1 (en) * 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
JP3961028B2 (ja) * 1996-12-27 2007-08-15 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト データフロープロセッサ（ｄｆｐ）の自動的なダイナミックアンロード方法並びに２次元または３次元のプログラミング可能なセルストラクチャを有するモジュール（ｆｐｇａ，ｄｐｇａ等）
DE19654846A1 (de) 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
DE19704044A1 (de) * 1997-02-04 1998-08-13 Pact Inf Tech Gmbh Verfahren zur automatischen Adressgenerierung von Bausteinen innerhalb Clustern aus einer Vielzahl dieser Bausteine
US6542998B1 (en) * 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704728A1 (de) * 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
DE19704742A1 (de) * 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internes Bussystem für DFPs, sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen, zur Bewältigung großer Datenmengen mit hohem Vernetzungsaufwand
US5907693A (en) * 1997-09-24 1999-05-25 Theseus Logic, Inc. Autonomously cycling data processing architecture
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
DE19807872A1 (de) 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Verfahren zur Verwaltung von Konfigurationsdaten in Datenflußprozessoren sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstruktur (FPGAs, DPGAs, o. dgl.
US6275890B1 (en) * 1998-08-19 2001-08-14 International Business Machines Corporation Low latency data path in a cross-bar switch providing dynamically prioritized bus arbitration
US6323755B1 (en) * 1998-08-19 2001-11-27 International Business Machines Corporation Dynamic bus locking in a cross bar switch
AU5805300A (en) 1999-06-10 2001-01-02 Pact Informationstechnologie Gmbh Sequence partitioning in cell structures
JP2004506261A (ja) 2000-06-13 2004-02-26 ペーアーツェーテー　イクスペーペー　テクノロジーズ　アクチエンゲゼルシャフト パイプラインｃｔプロトコルおよびｃｔ通信
US6754805B1 (en) * 2000-08-07 2004-06-22 Transwitch Corporation Method and apparatus for configurable multi-cell digital signal processing employing global parallel configuration
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
ATE437476T1 (de) 2000-10-06 2009-08-15 Pact Xpp Technologies Ag Zellenanordnung mit segmentierter zwischenzellstruktur
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US6990555B2 (en) * 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US7444531B2 (en) * 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7844796B2 (en) * 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
WO2002103532A2 (de) 2001-06-20 2002-12-27 Pact Xpp Technologies Ag Verfahren zur bearbeitung von daten
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) * 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
EP1483682A2 (de) 2002-01-19 2004-12-08 PACT XPP Technologies AG Reconfigurierbarer prozessor
DE10390689D2 (de) 2002-02-18 2005-02-10 Pact Xpp Technologies Ag Bussysteme und Rekonfigurationsverfahren
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
WO2004021176A2 (de) 2002-08-07 2004-03-11 Pact Xpp Technologies Ag Verfahren und vorrichtung zur datenverarbeitung
EP1537486A1 (de) 2002-09-06 2005-06-08 PACT XPP Technologies AG Rekonfigurierbare sequenzerstruktur
EP1676208A2 (en) 2003-08-28 2006-07-05 PACT XPP Technologies AG Data processing device and method
WO2007062327A2 (en) * 2005-11-18 2007-05-31 Ideal Industries, Inc. Releasable wire connector
EP1974265A1 (de) 2006-01-18 2008-10-01 PACT XPP Technologies AG Hardwaredefinitionsverfahren
WO2010113340A1 (en) * 2009-03-30 2010-10-07 Nec Corporation Single instruction multiple data (simd) processor having a plurality of processing elements interconnected by a ring bus
EP2457155B1 (en) * 2009-07-21 2017-10-11 Tadao Nakamura A lower energy comsumption and high speed computer without the memory bottleneck
US9015093B1 (en) 2010-10-26 2015-04-21 Michael Lamport Commons Intelligent control with hierarchical stacked neural networks
US8775341B1 (en) 2010-10-26 2014-07-08 Michael Lamport Commons Intelligent control with hierarchical stacked neural networks
WO2015125960A1 (ja) * 2014-02-24 2015-08-27 株式会社ニコン 情報処理装置、デジタルカメラおよびプロセッサ
KR102294108B1 (ko) * 2018-01-23 2021-08-26 다다오 나카무라 마칭 메모리 및 컴퓨터 시스템

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FR2470996B1 (fr) * 1979-11-30 1986-01-31 Quinquis Jean Paul Perfectionnements aux systemes electroniques multiprocesseurs destines au traitement de donnees numeriques et logiques
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JPH0740252B2 (ja) * 1986-03-08 1995-05-01 株式会社日立製作所 マルチプロセツサシステム
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US5168572A (en) * 1989-03-10 1992-12-01 The Boeing Company System for dynamic selection of globally-determined optimal data path
US5367642A (en) * 1990-09-28 1994-11-22 Massachusetts Institute Of Technology System of express channels in an interconnection network that automatically bypasses local channel addressable nodes
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8510534B2 (en) 2002-05-24 2013-08-13 St-Ericsson Sa Scalar/vector processor that includes a functional unit with a vector section and a scalar section
JP2022169552A (ja) * 2017-12-12 2022-11-09 アマゾン テクノロジーズ インコーポレイテッド オンチップの計算ネットワーク
US12314837B2 (en) 2017-12-12 2025-05-27 Amazon Technologies, Inc. Multi-memory on-chip computational network

Also Published As

Publication number Publication date
EP0504932A2 (en) 1992-09-23
US5506998A (en) 1996-04-09
EP0504932A3 (OSRAM) 1994-12-14

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Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19980514