JPH04293147A - Wait cycle joining system to access - Google Patents

Abstract

PURPOSE:To enhance the degree of freedom at the time of changing the transmission time of a ready signal. CONSTITUTION:In the system in which from a device side 5 which receives an address signal from a CPU 1, a ready signal of the device designated by this address signal is sent to the CPU 1 through a common bus, and subsequently, the CPU 1 joins a wait cycle in order to set its own access to the time corresponding to this ready signal, a time setting part 3 which can change programmably the contents is provided on the device side 5, and to this time setting part 3, an address of each device, and time information for showing to which time point it is necessary to send newly the ready signal with regard to each are coordinated and set in advance. The system is constituted so that when the access is executed, the time information corresponding to the address signal is selected from the time setting part 3, and while it is designated by this time information, the new ready signal is sent to the CPU 1.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention relates to a wait cycle participation method for access, and in particular to a wait cycle participation method for access,
The CPU via a common bus to which input/output devices are connected.
The device side that has received the address signal from the address signal sends a ready signal for the device specified by this address signal to the CPU, and then the CPU performs a wait cycle in order to make its own access the length corresponding to this ready signal. .

[0002] When the performance of the CPU increases and its speed increases, the access cycle (clock cycle) of the CPU becomes shorter and the previously set access time cannot be secured. Since the operating cycle on the device side that receives addresses, etc. remains the same, the CPU adds a new wait cycle depending on the degree of speed increase to lengthen the access time (by the amount of time shortened due to speed increase). Therefore, it is necessary to enable devices that receive address signals and the like to respond within the access time as before. The present invention relates to a wait cycle participation method in such a case.

0003

2. Description of the Related Art An overview of conventional weight cycle participation will be explained with reference to FIG. In the figure, the portion excluding the ready signal generation control section 40 and the trace memory 50 is the conventional device portion.

The existing device (IC board) 30 includes a storage device 31 and a plurality of input/output devices 35, etc., and the storage device 31 consists of an address recorder 32, a ready signal generation circuit 33, a memory 34, etc. The output device 35 includes an address recorder 36, a ready signal generation circuit 37,
It consists of IO ports 38, etc., and 20 is a CPU, 2
1 to 23 are common buses, and 21 is an address and data bus.
22 is a control line, and 23 is a ready signal line.

Here, the address signals, status signals, strobe signals, etc. sent by the access operation from the CPU 20 are decoded by the address recorders 32 and 36 of each device 31 and 35, and the access operation is performed for the own device. If it is confirmed that it is a ready signal, it operates its own ready signal generation circuit and sends the output signal to the CPU.
I sent it to the 20th.

[0006]Then, the CPU 20 adds a wait cycle to make its own access cycle a time corresponding to this ready signal, and sends an address signal with a longer time than the original access cycle to each device 31. , 35 can complete the response within that time.

FIG. 4 is an explanatory diagram showing the relationship among address signals, wait cycles, and ready signals. In the figure, 61 is the initial address signal sent from the CPU 20, 62 is the read command also sent from the CPU 20, 63 is the ready signal of the device selected by the address signal, and 64 is the ready signal after adding a wait cycle. A new address signal 65 whose length corresponds to the signal 63 indicates the operating time of the selected device in the read mode.

[0008] In this way, the initial address signal 61
By adding a wait cycle corresponding to the ready signal 63 to lengthen the access cycle, access from the CPU 20 is executed until the read mode in the device selected by the address signal ends.

[0009]

[Problem to be Solved by the Invention] In the conventional wait cycle joining method, the ready signal generation circuit of each device is fixed, and the contents of the ready signal, that is, the contents of the wait cycle joining the access, are also fixed. It was uniquely determined for each device.

Therefore, C connected to the common bus
When the speed of the PU is increased, the clock cycle becomes shorter, that is, the access cycle of the CPU becomes shorter, and the previously set access cycle time is no longer secured, but the operation of the device that performs this access Since the cycle remains the same as before, it is necessary to add a wait cycle corresponding to this shortened access time so that the device can respond within the access cycle time. The ready signal generation circuit must be modified.

- When evaluating the performance when low-speed devices are connected to a common bus, the evaluation is performed with the low-speed devices actually connected. case) When evaluating a virtual state, the ready signal generation circuit must be changed to include a longer wait cycle.

- When tracing signals on a common bus,
Address data is output by each strobe signal on this common bus.
Since each status data is written to the trace memory, when tracing a storage device consisting of a high-speed SRAM, the trace memory must be a high-speed memory that is equivalent to or higher than this SRAM. Alternatively, it may be necessary to latch the trace data once and then store it in low-speed memory. There were problems such as:

Therefore, in the present invention, a ready signal generation control section is provided on the side accessed by the CPU, and is equipped with a time setting section whose contents can be changed programmably.
This time setting section is set in advance by associating the address of each device with time information indicating the point at which a new ready signal needs to be sent for each device, and setting the address based on this time information. The purpose is to increase the degree of freedom in changing the transmission time of the ready signal by sending the ready signal to the CPU.

[0014]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, 1 is a CPU, to which ready signals are sent from the ready signal generation control section and each device. Reference numeral 2 denotes a ready signal generation control unit, which sends ready signals with different transmission times to the CPU in response to increased speed of the CPU. 3 is a time setting section, which is set by associating the address of each device accessed by the CPU with time information indicating up to which point a new ready signal needs to be sent for each device. , its contents can be changed programmably. 4 is a common bus to which a CPU, a storage device, an input/output device, a ready signal generation control section, etc. are connected. 5 is an existing device, and each accessed device sends its own ready signal to the CPU.

Here, when a certain device is accessed from the CPU 1, the ready signal from that device and the ready signal from the ready signal generation control unit 2 are ORed and the C
Sent to PU. The transmission time of the ready signal from the ready signal generation control section 2 is longer than that of the ready signal.

Note that the CPU 1 changes the number and length of wait cycles to participate in access based on the sent ready signal. Also, among the two ready signals,
A wait cycle may be added using only the ready signal from the ready signal generation control section 2.

[0017]

[Operation] In this way, in the present invention, in addition to the ready signal from the existing device, a new ready signal with a longer transmission time is also sent to the CPU. Even if the wait cycle addition operation is completed, the wait cycle addition operation is executed by the latter ready signal, so that the access from the CPU is as long as necessary from the viewpoint of the storage device or input/output device connected to the common bus. Time will definitely be secured. In addition, the CPU
When the wait cycle is added using only a new ready signal, the wait cycle adding operation based on the ready signal from the existing device is not performed.

[0018]

[Embodiment] An embodiment of the present invention will be explained using FIG. 2. Here, both the ready signal generation control unit 40 and the trace memory 50 are newly added parts in the present invention, and other parts are the same as described in "Prior Art".

In the ready signal generation control section 40, 41
are various cycles of the common bus, such as memory cycles,
A bus cycle monitoring unit 42 for monitoring input/output cycles, read cycles, write cycles, etc. specifies the input/output device that needs to newly transmit a ready signal, and assigns an area to each of these space addresses. An IO address register 43 for setting a number is a memory address register 43 for specifying a storage device to which a new ready signal needs to be sent and setting an area number to each of these space addresses. 44 is a ready time setting register for setting the transmission time for each area number set in the IO address register 42 and memory address register 43, and 45 is a ready signal for the transmission time selected by the ready time setting register 44. CPU2
This is a control circuit for sending data to 0.

Note that the space address used in the memory address register 43 is, for example, the address of a register constituting the controller of each input/output device 35 such as a CRT or printer.

FIG. 3 shows the flow when sending a ready signal from the device side to the CPU. In other words, ■CPU2
Upon receiving the address signal from 0, the storage device 31,
The group of input/output devices 35 and the ready signal generation control unit 40 each operate as follows (the former operates as shown in ■, and the latter as shown in ■).
~■ operations).

■In the storage device 31 and the input/output device 35,
The device identified by the address signal sends its own ready signal to C.
Send to PU.

■Using the data in the IO address register 42 and memory address register 43, the CPU 2 generates a new ready signal for the device specified by the address signal.
Check whether it is necessary to send to 0. In the embodiment of FIG. 3, it is checked whether an area number is set for the space address of the device. Here, no area number is set for devices that do not need to send a new ready signal to the CPU 20.

(2) When it is necessary to send a new ready signal to the CPU 20, a corresponding one is selected from among the transmission times stored in the ready time setting register 44. Note that in this register 44, the previous area number and transmission time are set in a corresponding manner. ■Send a ready signal to the CPU 20 during this determined time. Through such processing, a ready signal is sent from the device side to the CPU.

In this way, the IO address register 42 and memory address register 43 specify the input/output device or storage device for which a new ready signal needs to be created, and the ready time setting register 44 specifies the transmission time. It is decided in this part. And IO address register 4
2. The settings in the memory address register 43 and the ready time setting register 44 can be programmably changed as necessary, and the trace memory 50 uses a large-capacity, low-speed memory.

[0026]

[Effects of the Invention] The present invention provides a ready signal creation control section equipped with a time setting section whose contents can be changed programmably on the device side accessed by the CPU, and this time setting section includes the address and address of each device. By associating and setting time information indicating up to which point a new ready signal needs to be sent for each device, and sending a ready signal based on this time information to the CPU, the ready signal This increases the degree of freedom when changing the transmission time of Easily change the wait cycles involved in access, which is necessary when applying a load (evaluation in a virtual state), when tracing signals on a common bus using low-speed memory, etc. Can be done.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is an explanatory diagram showing an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a flow when sending a ready signal to a CPU according to the present invention.

FIG. 4 is an explanatory diagram showing the relationship between an address signal, a wait cycle, and a ready signal.

[Explanation of symbols]

In Figure 1, 1...CPU 2...Ready signal creation control section 3...Time setting section 4...Common bus

Claims (2)

[Claims] 1. A device that receives an address signal from the CPU via a common bus to which the CPU, storage device, and input/output device are connected transmits a ready signal of the device specified by this address signal to the CPU. and then the CPU
In this method of adding a wait cycle to access, the device adds a wait cycle in order to set its own access to a time corresponding to this ready signal. A ready signal generation control unit is provided, and this time setting unit includes the address of each device and time information indicating up to which point a new ready signal needs to be sent for each device. are set in association with each other, and the ready signal generation control section selects time information corresponding to the address signal from the time setting section and sends a ready signal based on this time information to the CPU. A wait cycle subscription method for access. 2. The wait cycle joining method for access according to claim 1, wherein a low-speed operation memory is connected to the common bus, and the signals on the common bus are traced to this memory.