JPH0429294A - Method and device fro inspecting tft picture element on lcd substrate - Google Patents

Method and device fro inspecting tft picture element on lcd substrate

Info

Publication number
JPH0429294A
JPH0429294A JP2134139A JP13413990A JPH0429294A JP H0429294 A JPH0429294 A JP H0429294A JP 2134139 A JP2134139 A JP 2134139A JP 13413990 A JP13413990 A JP 13413990A JP H0429294 A JPH0429294 A JP H0429294A
Authority
JP
Japan
Prior art keywords
drain
tft
gate
voltage
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2134139A
Other languages
Japanese (ja)
Inventor
Shinji Adachi
安立 信治
Yuji Yamaguchi
雄二 山口
Shingo Iwase
岩瀬 新午
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ADOTETSUKU ENG KK
Original Assignee
ADOTETSUKU ENG KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ADOTETSUKU ENG KK filed Critical ADOTETSUKU ENG KK
Priority to JP2134139A priority Critical patent/JPH0429294A/en
Publication of JPH0429294A publication Critical patent/JPH0429294A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To quickly inspect a large quantity of TFT picture elements with a high precision by applying a positive or negative voltage to the drain of the FT and applying a turning-on signal to the gate to measure the drain current and changing the drain voltage to measure the drain current and comparing two measured drain currents with each other. CONSTITUTION:Picture elements are formed in a matrix on an LCD substrate 50 as the object to be inspected, and a TFT 51 is formed in each picture element and has the gate connected to a gate electrode 53 and has the drain connected to a drain electrode 52. The positive or negative voltage is applied to the drain of the TFT 51 and the turning-on signal is applied to the gate to measure the drain current, and the drain voltage of the TFT 51 is changed and the turning-on signal is applied to the gate to measure the drain current, and two measured drain currents are compared with each other to discriminate whether the TFT picture element is good or not. Thus, a large quantity of TFT picture elements are quickly and surely inspected.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 この発明はLCD基板上のTFT画素の検査方法及び検
査装置に関する。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method and apparatus for testing TFT pixels on an LCD substrate.

〈従来の技術〉 近年LCD基板は種々の電子機器の表示装置として広く
利用されている。このLCD基板は通常ガラス基板に液
晶の画素と回路パターンを形成している。液晶テレビ特
にカラー液晶テレビ等においては液晶の応答速度を速く
し且つその画質を向上させるために、各液晶画素毎にT
FT (薄膜トランジスタ)を形成したLCD基板を用
いるのが普通である。
<Prior Art> In recent years, LCD substrates have been widely used as display devices for various electronic devices. This LCD substrate usually has liquid crystal pixels and circuit patterns formed on a glass substrate. In liquid crystal televisions, especially color liquid crystal televisions, etc., in order to increase the response speed of the liquid crystal and improve its image quality, T is applied to each liquid crystal pixel.
It is common to use an LCD substrate on which FTs (thin film transistors) are formed.

この方式はTFTのソース側にキャパシタンスを形成し
ておき、該キャパシタンスにより液晶に印加する電圧を
保持するように構成されている。
In this method, a capacitance is formed on the source side of the TFT, and the voltage applied to the liquid crystal is maintained by the capacitance.

〈発明が解決しようとする課題〉 このようなLC,D基板の良否の検査は製品の品質を維
持する上で非常に重要であり、特にTFTの特性の良否
がLCD基板の品質を決定している。
<Problem to be solved by the invention> Inspecting the quality of the LC and D substrates as described above is very important in maintaining product quality, and in particular, the quality of the LCD substrate is determined by the quality of the TFT characteristics. There is.

しかし従来は基板段階におけるテストはパターンのオー
プンショートのみしか行っておらず、画素の良否は実際
に基板に液晶を封入して点灯してチエツクする方法が採
られていた。
However, in the past, tests at the board stage were only performed by opening and shorting patterns, and the quality of pixels was checked by actually filling the board with liquid crystal and lighting it up.

しかしながら基板段階で画素の良否が判定できれば、実
際に点灯してチエツクする必要がなく。
However, if the quality of pixels can be determined at the board stage, there is no need to actually turn them on to check.

また不良画素の修理も可能になるため、大量にしかも速
く確実にLCD基板のTFT画素の良否の検査を行う方
法及び装置が望まれていた。
Furthermore, since it becomes possible to repair defective pixels, there has been a desire for a method and apparatus that can quickly and reliably test the quality of TFT pixels on an LCD substrate in large quantities.

く課題を解決するための手段〉 本発明の検査方法は上記した要望に応えるためになされ
たもので、LCD基板上のTFTのドレインに正又は負
の電圧を加えておき、ゲートにオン信号を加えて、この
時のドレイン電流を測定し、次に該TFTのドレイン電
圧を変化させて、ゲートにオン信号を加え、この時のド
レイン電流を測定し、前記2つの測定ドレイン電流を比
較することにより該TFT画素の良否を判定することを
基本的な特徴とする。
Means for Solving the Problems> The inspection method of the present invention was developed in response to the above-mentioned demands, and involves applying a positive or negative voltage to the drain of the TFT on the LCD substrate and applying an on signal to the gate. In addition, measure the drain current at this time, then change the drain voltage of the TFT, apply an on signal to the gate, measure the drain current at this time, and compare the two measured drain currents. The basic feature is that the quality of the TFT pixel is determined by the following.

〈実施例〉 以下本発明を図面に示す実施例に基づいて説明する。<Example> The present invention will be described below based on embodiments shown in the drawings.

第1図において、被検査対象であるLCD基板50には
画素がマトリクス状に形成され、各画素にTFT51が
形成されている。TFT51はそのゲート側がゲート電
極53に接続し、ドレイン側がドレイン電極52に接続
されている。ドレイン電極52とゲート電極53はLC
D基板50の縁に縦横に配設されている。各TFT51
のソース側には画素電極54と補助容量電極55から成
るキャパシタンスCが形成されており、このキャパシタ
ンスCにより液晶56に電圧が掛けられるように構成さ
れている。
In FIG. 1, pixels are formed in a matrix on an LCD substrate 50 to be inspected, and a TFT 51 is formed in each pixel. The TFT 51 has its gate side connected to a gate electrode 53 and its drain side connected to a drain electrode 52. The drain electrode 52 and gate electrode 53 are LC
They are arranged vertically and horizontally on the edge of the D board 50. Each TFT51
A capacitance C consisting of a pixel electrode 54 and an auxiliary capacitance electrode 55 is formed on the source side of the liquid crystal 56, and a voltage is applied to the liquid crystal 56 by this capacitance C.

パルス発振器1は所定周期のパルス電圧をゲト電極53
とドレイン電極52に供給する。パルス発振器1とドレ
イン電極52の間には位相調整器2が介装されており、
所定周期該パルスを遅らせるように構成されている。即
ち、第2図に示すようにドレイン電圧が所定電圧の時に
ゲート電圧をオンとし、また第3図に示すようにドレイ
ン電圧がゼロの時にゲート電圧をオンとするようにパル
ス発振器1からのパルスの位相を調整するようになって
いる。位相調整器2からのパルス電圧は抵抗Rを介して
ドレイン電極52に供給し、TFT51のドレイン電流
をこの抵抗Rの電圧として検出するようになっている。
The pulse oscillator 1 applies a pulse voltage of a predetermined period to a gate electrode 53.
and is supplied to the drain electrode 52. A phase adjuster 2 is interposed between the pulse oscillator 1 and the drain electrode 52,
The pulse is configured to be delayed by a predetermined period. That is, as shown in FIG. 2, the gate voltage is turned on when the drain voltage is a predetermined voltage, and as shown in FIG. 3, the gate voltage is turned on when the drain voltage is zero. It is designed to adjust the phase of the The pulse voltage from the phase adjuster 2 is supplied to the drain electrode 52 via a resistor R, and the drain current of the TFT 51 is detected as the voltage of this resistor R.

この実施例ではドレイン電極52とゲート電極53にコ
ネクタ7とコネクタ8を装着し、且つスイッチング装置
9とスイッチング装置10により各電極を走査して、該
電極を順次パルス発振器1及び位相調整器2に接続させ
て各TFT51の特性を順次測定するように構成してい
る。スイッチング装置19及びスイッチング装置10と
しては通常のリレースイッチやマルチプレクサ等の電子
スイッチを用いることが可能であり、各電極をスキャン
することによりパルス電圧の供給とドレイン電流の測定
を順次行うように構成している。 抵抗Rには電圧検出
器3が接続され、電圧検出器3の出力はA/D変換器4
を介して判定装置5に入力されて、ここでTFT51及
び画素電極54と補助容量電極55の良否が判定される
ように構成されている。6はメモリである。
In this embodiment, a connector 7 and a connector 8 are attached to a drain electrode 52 and a gate electrode 53, and each electrode is scanned by a switching device 9 and a switching device 10, and the electrode is sequentially connected to a pulse oscillator 1 and a phase adjuster 2. The configuration is such that the characteristics of each TFT 51 are sequentially measured by connecting them. As the switching device 19 and the switching device 10, it is possible to use an ordinary electronic switch such as a relay switch or a multiplexer, and the device is configured to sequentially supply a pulse voltage and measure the drain current by scanning each electrode. ing. A voltage detector 3 is connected to the resistor R, and the output of the voltage detector 3 is sent to an A/D converter 4.
The signal is inputted to the determination device 5 via the device 5, where it is determined whether the TFT 51, the pixel electrode 54, and the auxiliary capacitor electrode 55 are good or bad. 6 is a memory.

パルス発振器1から第2図に示すように位相調整器2、
スイッチング装置10、コネクタ8を介してドレイン電
極52からドレイン電圧が所定時間供給される。ドレイ
ン電圧が加えられた瞬間ドレインパターンとコモン端子
の間の容量により第2図に示すように電流60aが流れ
る。このドレイン電圧がある間パルス発振器1からスイ
ッチング装置9とコネクタ7を介してゲート電極53か
らゲート電圧が供給され、ゲートがオンになると、TF
T51のドレイン−ソース間に電流が流れて、キャパシ
タンスCが充電される。この時のドレイン電流を第2図
に示すように検出ドレイン電流61aとし、抵抗Rの電
圧として電圧検出器3で検出する。この値はA/D変換
器4によりデジタル量に変換され、判定装置5を介して
メモリ6に記憶される。
From the pulse oscillator 1 to the phase adjuster 2 as shown in FIG.
Drain voltage is supplied from the drain electrode 52 via the switching device 10 and the connector 8 for a predetermined period of time. The moment a drain voltage is applied, a current 60a flows as shown in FIG. 2 due to the capacitance between the drain pattern and the common terminal. While this drain voltage is present, a gate voltage is supplied from the gate electrode 53 from the pulse oscillator 1 via the switching device 9 and the connector 7, and when the gate is turned on, the TF
A current flows between the drain and source of T51, and the capacitance C is charged. The drain current at this time is defined as a detected drain current 61a as shown in FIG. 2, and is detected as the voltage across the resistor R by the voltage detector 3. This value is converted into a digital quantity by the A/D converter 4 and stored in the memory 6 via the determination device 5.

次に第3図に示すように位相調整器2からのドレイン電
圧をOvにするとドレインパターンに充電されていた電
荷が放電され、これが第3図に示すように電流60bと
して観測される。放電が完了した後ドレイン電圧がゼロ
の時に、パルス発振器1からのゲート電圧をオンとする
と、TFT51のキャパシタンスCに充電された電荷が
放電さtl、てTFT51のソースからドレイン、抵抗
R方向に逆方向のドレイン電流が流れる。これを第3図
に示すように検出ドレイン電流61bとして電圧検出器
3により検出し、判定装W5を介してメモリ6に記憶さ
せる。
Next, as shown in FIG. 3, when the drain voltage from the phase adjuster 2 is set to Ov, the charges stored in the drain pattern are discharged, and this is observed as a current 60b as shown in FIG. When the gate voltage from the pulse oscillator 1 is turned on when the drain voltage is zero after the discharge is completed, the electric charge charged in the capacitance C of the TFT 51 is discharged tl, and reverses from the source to the drain of the TFT 51 and in the direction of the resistor R. A drain current flows in the direction. As shown in FIG. 3, this is detected by the voltage detector 3 as a detected drain current 61b, and is stored in the memory 6 via the determining device W5.

検出ドレイン電流61aと検出ドレイン電流61bは夫
々、ゲートとドレイン間及びゲートパターンとドレイン
パターン間の漏れ電流を含んでおり、検出ドレイン電流
61aとbの差を採ることによりこの漏れ電流を除去す
ることができる。
The detected drain current 61a and the detected drain current 61b each include leakage current between the gate and the drain and between the gate pattern and the drain pattern, and this leakage current can be removed by taking the difference between the detected drain currents 61a and 61b. I can do it.

いまゲートオンの時の漏れ電流をieとし、実際にTF
T51オンによりキャパシタンスCを流れる電流をic
とすると、検出ドレイン電流61a=ie−icとなる
。一方TFT51オンによりキャパシタンスCに蓄えら
れた電荷の放電電流をidとすると、検出ドレイン電流
61b=ie+idとなる。したがって検出ドレイン電
流61aとbの差はic+idとなり、漏れ電流ieの
影響は取り除かれる。TFT51及び画素電極54、補
助容量電極55が正常であるなら、キャパシタンスCへ
の充放電が正常に行われるから、第4図に示すようにそ
の差は大きくなる。逆に異常であれば、第5図に示すよ
うに差は小さくなる。
Let the leakage current when the gate is on be ie, and actually TF
When T51 is turned on, the current flowing through the capacitance C becomes ic
Then, the detected drain current 61a=ie-ic. On the other hand, if the discharge current of the charge stored in the capacitance C due to the TFT 51 being turned on is id, then the detected drain current 61b=ie+id. Therefore, the difference between the detected drain currents 61a and 61b is ic+id, and the influence of the leakage current ie is removed. If the TFT 51, the pixel electrode 54, and the auxiliary capacitance electrode 55 are normal, charging and discharging to the capacitance C is performed normally, so the difference becomes large as shown in FIG. 4. On the other hand, if it is abnormal, the difference becomes small as shown in FIG.

この実施例では判定装置5において該検出ドレイン電流
61aとbのゲートオン信号印加後の所定時刻における
瞬時値の差を求めており、この差が所定以上か否かによ
りTFT51及び画素電極54、補助容量電極55の良
否の判定を行っている。
In this embodiment, the determination device 5 determines the difference between the instantaneous values of the detected drain currents 61a and 61b at a predetermined time after the application of the gate-on signal, and depending on whether this difference is greater than or equal to a predetermined value, the TFT 51, the pixel electrode 54, the auxiliary capacitor The quality of the electrode 55 is determined.

次に測定の手順を説明する。Next, the measurement procedure will be explained.

まずドレイン電圧をOvにしてゲートにオン電圧を加え
て放電させ、画素電極54と補助容量電極55に充電さ
れているかもしれない電荷を取り除く。そして、ドレイ
ン電圧を加えて、まずパターンの浮遊8竃の充電を行い
、これが終了したらゲートにオン電圧を加えて、所定時
間後にドレイン電流を電圧検出器3により検出する。該
所定時間はゲートの漏れ電流が小さくなり且つ充電電流
が小さくなっていない時間とし、これはTFT51の特
性或はLCD基板50のサイズ、パターン特性により決
定されるが、約スイッチング装置10μ〜40μsec
である。この電圧検出器3で検出した信号をホールドし
てA/D変換器4によりデジタル量に変換し、判定装置
5を介してメモリ6に記憶させる。この値は上記した検
出ドレイン電流61a=ie−icである。
First, the drain voltage is set to Ov, and an on-voltage is applied to the gate to discharge it, thereby removing any charges that may have been stored in the pixel electrode 54 and the auxiliary capacitor electrode 55. Then, a drain voltage is applied to first charge the floating eight wires of the pattern, and when this is completed, an on-voltage is applied to the gate, and the drain current is detected by the voltage detector 3 after a predetermined period of time. The predetermined time is a time during which the leakage current of the gate becomes small and the charging current does not become small, and this is determined by the characteristics of the TFT 51 or the size and pattern characteristics of the LCD substrate 50, but it is approximately 10 to 40 μsec for the switching device.
It is. The signal detected by this voltage detector 3 is held, converted into a digital quantity by an A/D converter 4, and stored in a memory 6 via a determination device 5. This value is the above-mentioned detected drain current 61a=ie-ic.

次にドレイン電圧をOvにして、ドレインパターン等に
蓄積されていた電荷を取り除き、Ovのままでゲートに
オン電圧を加える。そして、上記した所定時間と同じ時
間後に電圧検出器3によりドレイン電流を検出する。こ
の値を同様にメモリ6に記憶する。この値は上記した検
出ドレイン電流61b=ie+idである。そして判定
装置5において検出ドレイン電流61aと61bの差を
算出し、i c + j、 dの値を得る。この値はT
FT51と画素電極54、補助容1電極55が良品であ
れば大きく、不良品であれば小さいから、該差により良
不良の判定が可能になる。
Next, the drain voltage is set to Ov to remove the charge accumulated in the drain pattern, etc., and an on-voltage is applied to the gate while keeping Ov. Then, the drain current is detected by the voltage detector 3 after the same time as the above-mentioned predetermined time. This value is similarly stored in the memory 6. This value is the above-mentioned detected drain current 61b=ie+id. Then, the determination device 5 calculates the difference between the detected drain currents 61a and 61b, and obtains the value of ic + j, d. This value is T
If the FT 51, the pixel electrode 54, and the auxiliary capacitor 1 electrode 55 are good, they are large, and if they are defective, they are small, so it is possible to determine good or bad based on the difference.

以上説明したように本発明の検査方法によれば、LCD
基板50の内部パターンに接触することなく、確実にT
FT51及び画素電極54、補助容量電極55の良否の
判定を行える。また、コネクタ7.8及びスイッチング
装W9.10を用いることにより、高速で検査を行うこ
とが可能になる。
As explained above, according to the inspection method of the present invention, LCD
T is securely connected without contacting the internal pattern of the substrate 50.
It is possible to determine the quality of the FT 51, the pixel electrode 54, and the auxiliary capacitor electrode 55. Furthermore, by using the connector 7.8 and the switching device W9.10, it is possible to perform inspections at high speed.

〈発明の効果〉 以上説明したように本発明のLCD基板上のTFTの検
査方法は、LCD基板上のTFTのドレインに正又は負
の電圧を加えておき、ゲートにオン信号を加えて、この
時のドレイン電流を測定し。
<Effects of the Invention> As explained above, the method for inspecting TFTs on an LCD substrate of the present invention is to apply a positive or negative voltage to the drain of the TFT on the LCD substrate, apply an on signal to the gate, and test this TFT. Measure the drain current at .

次に該TFTのドレイン電圧を変化させて、ゲートにオ
ン信号を加え、この時のドレイン電流を測定し、前記2
つの測定ドレイン電流を比較することにより該TFT画
素の良否を判定するようにしているため、LCD基板の
内部パターンに接触することなく、大量且つ高速に精度
の高い検査を行うことができる効果がある。
Next, change the drain voltage of the TFT, apply an on signal to the gate, measure the drain current at this time, and
Since the quality of the TFT pixel is determined by comparing two measured drain currents, it is possible to perform high-accuracy inspection in large quantities and at high speed without touching the internal patterns of the LCD board. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の方法及びその装置を示す一実施例のブ
ロック図、第2図と第3図は動作説明図、第4図と第5
図は検出電流波形の説明図である。 1:パルス発振器、2:位相調整器、3:電圧検出器、
4 : A/D変換器、5:判定装置、6:メモリ、7
:コネクタ、8:コネクタ、9ニスイツチング装置、1
0ニスイツチング装置、50:LCD基板、51 : 
TFT、52ニドレイン電極、53:ゲート電極、54
:画素電極、55:補助容量電極、56:液晶、60:
電流、61:検出ドレイン電流。 第 図 ドレイン11圧 ゴー一−ヒ ゲート電圧 =「−一 第 図 ドレイン電圧 ]−m−「 ゲート電圧 」−一 区 寸 昧 り較田
FIG. 1 is a block diagram of an embodiment of the method and apparatus of the present invention, FIGS. 2 and 3 are operation explanatory diagrams, and FIGS. 4 and 5.
The figure is an explanatory diagram of a detected current waveform. 1: Pulse oscillator, 2: Phase adjuster, 3: Voltage detector,
4: A/D converter, 5: Determination device, 6: Memory, 7
: Connector, 8: Connector, 9 Switching device, 1
0ni switching device, 50: LCD board, 51:
TFT, 52 Nidrain electrode, 53: Gate electrode, 54
: Pixel electrode, 55: Storage capacitor electrode, 56: Liquid crystal, 60:
Current, 61: Detection drain current. Diagram Drain 11 Voltage - High Gate Voltage = "-1 Diagram Drain Voltage" - m - "Gate Voltage" - 1 sec.

Claims (1)

【特許請求の範囲】 1)LCD基板上のTFTのドレインに正又は負の電圧
を加えておき、ゲートにオン信号を加えて、この時のド
レイン電流を測定し、 次に該TFTのドレイン電圧を変化させて、ゲートにオ
ン信号を加え、この時のドレイン電流を測定し、 前記2つの測定ドレイン電流を比較することにより該T
FT画素の良否を判定する、 ことを特徴とするLCD基板上のTFT画素の検査方法
。 2)LCD基板上のTFTのドレインに正又は負の電圧
を加えてゲートにオン信号を加え、次に該TFTのドレ
イン電圧を変化させてゲートにオン信号を加える手段と
、 前記ドレインに正又は負の電圧を加えた時とドレイン電
圧を変化させた時のドレイン電流を測定し、この2つの
測定ドレイン電流を比較することにより該TFT画素の
良否を判定する手段と、を備えたことを特徴とするLC
D基板上のTFT画素の検査装置。
[Claims] 1) Apply a positive or negative voltage to the drain of the TFT on the LCD substrate, apply an on signal to the gate, measure the drain current at this time, and then measure the drain voltage of the TFT. By changing the T and applying an on signal to the gate, measuring the drain current at this time and comparing the two measured drain currents, the T
A method for inspecting TFT pixels on an LCD substrate, the method comprising: determining the quality of the FT pixels. 2) means for applying a positive or negative voltage to the drain of a TFT on the LCD substrate to apply an on signal to the gate, and then applying a positive or negative voltage to the gate by changing the drain voltage of the TFT; It is characterized by comprising means for measuring the drain current when applying a negative voltage and when changing the drain voltage, and determining the quality of the TFT pixel by comparing these two measured drain currents. LC
Inspection device for TFT pixels on D substrate.
JP2134139A 1990-05-25 1990-05-25 Method and device fro inspecting tft picture element on lcd substrate Pending JPH0429294A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2134139A JPH0429294A (en) 1990-05-25 1990-05-25 Method and device fro inspecting tft picture element on lcd substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2134139A JPH0429294A (en) 1990-05-25 1990-05-25 Method and device fro inspecting tft picture element on lcd substrate

Publications (1)

Publication Number Publication Date
JPH0429294A true JPH0429294A (en) 1992-01-31

Family

ID=15121386

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2134139A Pending JPH0429294A (en) 1990-05-25 1990-05-25 Method and device fro inspecting tft picture element on lcd substrate

Country Status (1)

Country Link
JP (1) JPH0429294A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100970366B1 (en) * 2003-02-14 2010-07-16 윈테스트 가부시키가이샤 Inspection method and inspection device for active matrix substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100970366B1 (en) * 2003-02-14 2010-07-16 윈테스트 가부시키가이샤 Inspection method and inspection device for active matrix substrate

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