JPH04291817A - Logic circuit - Google Patents

Abstract

PURPOSE:To attain high circuit integration and high speed processing by devising the constitution of transistor(TR) elements of a data selection circuit outputting one of plural input data based on a selection signal, utilizing a load amplifier characteristic of the TR and forming the data selection circuit with a few TRs. CONSTITUTION:The logic circuit outputting selectively either a 1st input data A or a 2nd input data B is provided with a 1st logical arithmetic circuit 11 exclusively ORing the 1st input data A and a data selection signal S and with a 2nd logical arithmetic circuit 12 implementing 3-input majority arithmetic operation based on the 1st input data A, the 2nd input data B and a resulting output data SER of the 1st logical arithmetic circuit 11, and the 1st and 2nd logical arithmetic circuits 11,12 each has an active element RHET having a negative amplifier characteristic.

Description

[Detailed description of the invention]

[Table of Contents] Industrial applications Conventional technology (Figure 6) Problems that the invention aims to solve Means (Figures 1 and 2) to solve the problem Examples (Figures 3-5) Effect of the invention

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit, and more particularly to a data selection circuit that outputs one of a plurality of input data based on a selection signal.

In recent years, semiconductor integrated circuit (hereinafter referred to as LSI) devices have been improved in performance and functionality, and data selection circuits consisting of bipolar transistor circuits and complementary field effect transistor circuits that select and output input logic signals at high speed have been developed. is used.

For example, a data selection circuit using bipolar transistors is composed of three two-input NAND circuits, an inverter, and the like. For this reason, when the data selection circuit is implemented as an LSI device, there is a problem that the number of active elements increases, which hinders higher integration and higher speed.

[0005] Therefore, by devising the structure of the transistor element and utilizing the negative amplification characteristic 6 of the transistor, a logic circuit that can construct a data selection circuit with a small number of transistors and achieve high integration and high speed has been developed. desired.

[0006]

2. Description of the Related Art FIGS. 6(a) and 6(b) are explanatory diagrams of a conventional example. FIG. 6(a) shows a configuration diagram of a logic circuit according to a conventional example.

In the same figure (a), two input data A
, B based on the selection signal S is, for example, a first two-input NAND circuit (hereinafter referred to as the first logic circuit) 1, an inverter 2, and a second two-input NAND circuit. It consists of a circuit (hereinafter referred to as a second logic circuit) 3 and a two-input NAND circuit (hereinafter referred to as a third logic circuit) 4.

The function of the logic circuit is as follows: First, the first logic circuit 1 performs a two-input NAND operation on the input data A and the selection signal S. On the other hand, the inverted selection signal S inverted by the inverter 2 and the input data B are sent to the second logic circuit 3.
A two-input NAND operation is performed. These result signals are calculated by the third logic circuit 4, and the following calculation signal Q is obtained.
is output.

[0009]

[Math 1]

As a result, one of the two input data A and B is selectively outputted from the data selection circuit to the next stage logic circuit or the like.

[0011]

By the way, according to the conventional example, the first and second logic circuits 1 as shown in FIG.
, 3. When a data selection circuit is configured by the inverter 2 and the third logic circuit 4, several transistors are required for each gate. Further, a delay corresponding to three stages of gates occurs.

For this reason, when the data selection circuit is implemented as an LSI device, there is a problem in that the number of active elements increases, which hinders higher integration and higher speed.

Furthermore, as shown in the problem shown in FIG. 6(b), in the case of an ECL (emitter-coupled logic) circuit using bipolar transistors that is composed of a relatively small number of circuit elements, the selection signal S is non-inverted or inverted. A large number of transistors are required, such as a differential amplifier circuit that outputs input data A and B, a differential amplifier circuit that outputs non-inverted and inverted signals of input data A and B, and a constant current circuit that sets their biases. Also, in general, the VBE (emitter-base voltage) of a transistor vs. I
The C (collector current) characteristic becomes an exponential characteristic (diode characteristic), and only two operating points can be set to determine the "H" level and "L" level of the logic circuit.

[0014] Also, in a data selection circuit constituted by field effect transistors, a large number of transistors are required due to the combinational logic circuit of ordinary gate circuits. This may impede high integration due to an increase in the number of active elements, and may impede high-speed logic output operations due to an increase in the number of delay stages such as inverter circuits.

The present invention was created in view of the problems of the conventional example, and the configuration of the transistor element is devised to utilize the negative amplification characteristic of the transistor, thereby realizing a data selection circuit with a small number of transistors. The object of the present invention is to provide a logic circuit that can be configured to achieve higher integration and higher speed.

[0016]

[Means for Solving the Problems] FIG. 1 is a principle diagram (part 1) of a logic circuit according to the present invention, and FIGS. 2(a) to (c)
1A and 1B respectively show principle diagrams (Part 2) of the logic circuit according to the present invention.

As shown in FIG. 1, the logic circuit of the present invention is a logic circuit that selectively outputs one of first input data A and second input data B based on a data selection signal S. a first logical operation circuit 11 that performs an exclusive OR operation on the input data A and the data selection signal S;
a second logic operation circuit 12 that performs a three-input majority decision operation based on input data A, second input data B, and result output data SER of the first logic operation circuit 11; It is characterized in that the second logical operation circuits 11 and 12 are composed of active elements RHET having negative amplification characteristics.

In the logic circuit of the present invention, the first logic operation circuit 11 includes a first transistor T1 and a first transistor T1.
- Consisting of fourth resistance elements R1 to R4, the base B of the first transistor T1 is connected to the first to third resistance elements R1 to
The emitter E of the first transistor T1 is connected to the second power supply line GND, and the collector C of the first transistor T1 is connected to the first power supply line GND through the fourth resistance element R4. The other end of the first resistance element R1 is connected to the input part of the first input data A, and the other end of the second resistance element R2 is connected to the input part of the data selection signal S. The other end of the third resistance element R3 is connected to the second power supply line GND, and the second logic operation circuit 12 has second and third transistors T2, T3 and Fifth to tenth resistance elements R5 to
R10, the base B of the second transistor T2 is connected to one end of the fifth to seventh resistance elements R5 to R7, and the collector C of the second transistor T2 is connected to the second transistor T2. The emitter E of the transistor T2 is the second
The second transistor T2 is connected to the power supply line GND of
The collector C of is connected to the base B of the third transistor T3 via the eighth resistance element R8, the emitter E of the third transistor T3 is connected to the second power supply line GND, and the third The collector C of the transistor T3 is the first
0, the other end of the fifth resistive element R5 is connected to the collector C of the first transistor T1, and the sixth resistive element R6 The other end of the seventh resistance element R7 is connected to the input part of the second input data B, the other end of the seventh resistance element R7 is connected to the input part of the first input data A, and the third transistor T3 The ninth resistance element R9 is connected between the base B of the power source B and the second power supply line GND, and the above object is achieved.

[0019]

According to the logic circuit of the present invention, as shown in FIG. 2(a), first and second logic operation circuits 11 and 12 each comprising an active element RHET having negative amplification characteristics are provided.

For example, the first input data A and the data selection signal S are subjected to an exclusive OR operation by the first logic operation circuit 11. At this time, an active element with negative amplification characteristics,
For example, a first transistor consisting of a resonant tunneling diode, a resonant tunneling hot electron transistor, a resonant tunneling bipolar transistor RHET, etc.
In the logical operation circuit 11, the VBE (emitter-base voltage) vs. IC (collector current) characteristic of the transistor becomes a negative differential function characteristic (negative differential conductance characteristic), and the logic circuit has an "H" level and a "L" level. The operating points for determining the level can be set at 3 to 4 locations. As a result, Figure 2
As shown in (b), when one of the first input data A and the data selection signal S is at the "H" level and the other is at the "L" level, the logic operation circuit 11 outputs the "L" level (SER).
When both inputs are at "H" and "L" levels, the output is at "H" level (SER=1).

Furthermore, the first input data A, the second input data B, and the result output data S of the first logic operation circuit 11
ER is subjected to a three-input majority vote calculation by the second logical operation circuit 12. At this time, in the second logic operation circuit 11 made of the active element RHET which similarly has negative amplification characteristics, if the input "H" level (A, B or SER = 1) is 1 or less, the output "H" ” level, and when the input “H” level is 2 or more, it operates as the output “L” level. That is, the negation of the logic value of the larger one of the three inputs is output. As a result, the first
One negation of the input data A or the second input data B is selectively output.

For example, when the data selection signal S is at the "H" level (S=1), the resultant output data SER of the first logic operation circuit 11 becomes equal to the input data A. From this, the content of the input signal to the second logical operation circuit 12 is 2
becomes input data A. Therefore, the second logic operation circuit 12 outputs the negation of the value of data A regardless of input data B (see FIG. 2(b)).

Furthermore, the data selection signal S is at the "L" level (
S=0), the result output data SER of the first logical operation circuit 11 becomes the negation of the input data A. From this, the content of the input signal to the second logical operation circuit 12 is that the "H" level of the input data A is on one side, and the "L" level on the other side.
The level will be entered. Therefore, in this case, it is determined by the value of input data B, and the negation of that value is output from the second logic operation circuit 12 (see FIG. 2(c)).

The logical formula is shown below.

[0025]

[Math 2]

[0026] However, A and B represent first and second input logical values, S represents a data selection logical value, and Q represents a data selection output logical value, respectively.

Therefore, it is possible to configure the data selection circuit by three resonant tunneling bipolar transistors RHET, and it is possible to reduce the number of active elements as much as possible compared to the conventional example. Further, by reducing the number of amplification stages, it is possible to speed up the logic output operation.

[0028] This makes it possible to achieve higher integration and higher performance of semiconductor integrated circuit (hereinafter referred to as LSI) devices than in the prior art.

[0029]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. 3 to 5 are explanatory diagrams of a logic circuit according to an embodiment of the present invention, and FIGS. 3(a) and 3(b) are diagrams showing a configuration diagram and a transistor characteristic diagram of a data selection circuit according to an embodiment of the present invention. It shows.

In FIG. 3(a), two input data A
, B based on the selection signal S is composed of a two-input negative exclusive OR circuit 21 and a three-input negative majority logic circuit 22.

That is, the two-input exclusive OR circuit (hereinafter referred to as the first logic circuit) 21 is the first logic operation circuit 1.
1, which outputs the negative output of the exclusive OR of the first input data A and the data selection signal S. The first logic circuit 21 includes a first resonant tunneling bipolar transistor RHET (hereinafter referred to as a first transistor T1).
) and circuit constant setting resistance elements (hereinafter simply referred to as resistances) R1 to R4.

The collector of the first transistor T1 is connected to the power supply line VCC via a resistor R4, and is also connected to the resistor R5 of the three-input negative majority logic circuit 22, respectively. Its base is connected to the input point Din1 of the first input data A and the input point Sin of the data selection signal S via resistors R1 and R2, and to the ground line GND via a resistor R3. In addition, the emitter is connected to the ground wire GND.
It is connected to the.

A three-input negative majority logic circuit (hereinafter referred to as a second logic circuit) 22 is an embodiment of the second logic operation circuit 12, and is a three-input negative majority logic circuit (hereinafter referred to as a second logic circuit). Based on the result output data SER of the logical operation circuit 11, the negative output of the three-input majority logic is performed. The second logic circuit 22 consists of second and third resonant tunneling bipolar transistors RHET (hereinafter referred to as second and third transistors T2 and T3) and circuit constant setting resistance elements (hereinafter simply referred to as resistors) R5 to R10. .

The collector of the second transistor T2 is connected to the base (diode connection), and its connection point p is connected to the input point Din1 of the first input data A via a resistor R7. Further, the connection point p is connected to the collector of the first logic circuit 21 via a resistor R5, to the input point Din2 of the second input data B via a resistor R6, and further to the next stage via a resistor R8. are respectively connected to the bases of the third transistors T3. In addition, the emitter is connected to the ground wire G.
Connected to ND.

The collector of the third transistor T3 is connected to the power supply line VCC via the resistor R10, and is also connected to the output point Dout of the three-input negative majority logic circuit 22, respectively. Its base is connected to the previous connection point p via a resistor R8, and to the ground line GND via a resistor R9. Note that the emitter is connected to a ground line GND.

FIG. 3(b) shows the current I versus voltage VB of the transistor constituting the data selection circuit according to the embodiment of the present invention.
An E characteristic diagram is shown.

In FIG. 3(b), the first to third transistors T constituting the first and second logic circuits 21 and 22
The transistor characteristics of 1 to T3 are negative differential conductance (
(hereinafter also referred to as negative amplification characteristics or resonant tunneling current characteristics)
have. That is, the vertical axis is current I, and indicates emitter current IE, collector current IC, base current IB, etc., respectively. The horizontal axis is voltage, indicating emitter-base voltage VBE.

Further, the negative differential conductance (negative amplification characteristic) is the resonance tunneling bipolar transistor RH.
In the case of ET, this is a characteristic that occurs when the number of electrons injected from the emitter to the base increases when the voltage VBE between the emitter and base of the transistor is a certain value. This is a characteristic that occurs because electrons injected into the base become hot electrons, run through the base at high speed, and then reach the collector, excluding some electrons that have lost energy due to scattering phenomena.

In the embodiment of the present invention, by setting operating points on the negative differential conductance curves of the first to third transistors T1 to T3, the two-input negative exclusive OR operation function and the three-input negative majority decision function can be achieved. It becomes possible to achieve logical operation functions.

FIGS. 4(a) to 4(c) are explanatory diagrams of the operation of the two-input ENOR circuit according to the embodiment of the present invention, and FIGS.
) indicates a logic gate of a two-input exclusive OR circuit.

In FIG. 4(a), a two-input exclusive NOT OR circuit (hereinafter referred to as a two-input ENOR circuit) 21 has a first
The operation result data SER based on the two-input negative exclusive OR of the input data A and the data selection signal S is output to the three-input negative majority logic circuit 22.

That is, FIG. 4(b) is a circuit diagram in which only the two-input ENOR circuit 21 is extracted, and in FIG. 4(b), the base B of the first transistor T1 is driven by voltage. This is because resistors R1, R2, and R3 smaller than the equivalent input resistance are connected to the base B of the first transistor T1. Further, assuming that the resistors R1 and R2 do not change, the base voltage of the first transistor T1 is the intermediate voltage of the two input voltages related to the first input data A and the data selection signal S. A voltage divided by the parallel resistor and resistor R3 is applied.

Therefore, three load lines having an inclination θ1 can be set in the negative differential conductance characteristic curve of the first transistor T1 shown in FIG. 4(c). That is, in FIG. 2C, the vertical axis represents the collector current IC of the first transistor T1 and its base current IB, and the horizontal axis represents its emitter-base voltage VBE.

Here, regarding the base voltage of the first transistor T1, the first input data A, the data selection signal S
The operating point p1 is set so that it is located near the rising voltage when both are at the "L" level. Further, when one of the first input data A or the data selection signal S is at the "L" level and the other is at the "H" level, the operating point p2 is similarly set to be located near the peak voltage Vp. . Furthermore, when the first input data A and the data selection signal S are both at the "L" level, the operating point p3 is similarly set to be located near the valley voltage Vb.

Note that the slope θ1 of the load line is determined by the resistances R1 to R3.
Set by parallel resistance. As a result, the collector current I
A large amount of C flows, and the output voltage of the two-input ENOR circuit 21 decreases (SER=0). In other cases, the collector current does not flow and the output voltage remains high (SER=
1).

With this, the input of the logic operation circuit 11,
That is, the first input data A and the data selection signal S are "
In the case of "H" level or "L" level, the output operates as "L" level (SER=0), and both inputs are "H".
, "L" level, the output "H" level (SER
=1), a two-input negative exclusive OR operation can be performed.

FIGS. 5(a) to 5(c) are explanatory diagrams of the operation of the three-input negative majority circuit according to the embodiment of the present invention.
A) shows a simplified circuit diagram of a three-input negative majority circuit.

In FIG. 5(a), the three-input negative majority circuit performs a majority vote on the first input data A, the second input data B, and the operation result data SER of the two-input ENOR circuit, and selects the first input. The negative of either data A or second input data B is selectively output.

That is, FIG. 5(b) is a circuit diagram in which only the three-input negative majority circuit 22 is extracted, and in FIG. 5(b), the output of the three-input negative majority circuit 22 is connected to a diode-connected second transistor. This can be changed by the number of "H" levels of the input voltages v1, v2, v3 related to the first and second input data A, B and the calculation result data SER input to T2.

This means that the negative differential conductance characteristic curve of the second transistor T2 in FIG. 5(c) has a slope of 4 of θ2.
Obtained when setting a load line of 1. That is, in FIG. 3(c), the vertical axis represents the emitter current IE of the second transistor T2, and the horizontal axis represents its emitter-base voltage VBE.

Here, the operating points p1 to p4 of the second transistor T2 are the intersections of the emitter current IE and four load lines drawn by the emitter-base resonant tunneling current characteristic. Note that the load lines are input voltages v1, v2, v3 related to the first and second input data A, B, the calculation result data SER of the two-input ENOR circuit 21, and the resistances R5 to R7 of the input section.
It is determined by the resistance (R8+R9) of the output section. For example, at each operating point p1 to p4, the number of "H" levels of the first and second input data A, B and calculation result data SER is 2 and 3 at the intersection of the four load lines and the emitter current IE.
In this case, the input section resistances R5 to R7 and the output section resistances (R8+R9
). Also, the number of "H" levels of the first and second input data A, B and operation result data SER is 0 and 1.
In this case, the input section resistances R5 to R7 and the output section resistance (R8+R9)
Set.

[0052] As a result, the second transistor T2 is
There is a large difference in the base voltage between the case where the number of first and second input data A, B and calculation result data SER, etc. at the "H" level is 1 or less and the case where the number is 2 or more. Further, the base voltage of the second transistor T2 is resistance-divided by resistors R8 and R9 and applied to the base of the third transistor T3.

In the third transistor T3, the first and second
"H" of input data A, B and operation result data SER, etc.
'' If the number of levels is 2 or more, it is turned on and the collector current flows, and the output point Dout becomes ``L'' level. Further, when the third transistor T3 is OFF, no collector current flows, so the output point Dout becomes "H" level.

Therefore, the data selection circuit functions as an output "H" level when the number of inputs at "H" level is 1 or less, and as an output "L" level when it is 2 or more. , it is equivalent to a circuit in which a negative circuit is connected to a three-input majority circuit.

In this way, according to the logic circuit according to the embodiment of the present invention, as shown in FIGS. 2 to 4, a two-input ENOR circuit 21 and a three-input A negative majority logic circuit 22 is provided.

Therefore, the first input data A and the data selection signal S are subjected to an exclusive OR operation by the two-input ENOR circuit 21. At this time, VBE of the first transistor T1
Since the (emitter-base voltage) vs. IC (collector current) characteristic has a negative differential conductance characteristic, the E
Three operating points can be set for determining the "H" level and "L" level of the NOR circuit 21. As a result, when one of the first input data A and the data selection signal S is at the "H" level and the other is at the "L" level, the two-input ENOR circuit 21 outputs the "L" level (SER=0). When both inputs are at "H" and "L" levels, the output is at "H" level (SER=1).

In addition, the first input data A, the second input data B, and the resultant output data S of the two-input ENOR circuit 21
ER is subjected to a three-input negative majority calculation by a three-input negative majority vote circuit 22. At this time, a resonant tunneling bipolar transistor R having a negative differential conductance as well
In the three-input negative majority logic circuit 22 consisting of HET,
When the input "H" level (A, B or SER = 1) is 1 or less, it operates as an output "H" level, and when the input "H" level is 2 or more, it operates as an output "L" level. . As a result, the negative of one of the first input data A or the second input data B is selectively output based on the data selection signal S.

That is, when the data selection signal S is at the "H" level (S=1), the resultant output data SER of the two-input ENOR circuit 21 becomes equal to the input data A. From this, two input signals are input data A to the three-input negative majority logic circuit 22. Therefore, the majority logic circuit 22 outputs the negation of the value of data A regardless of input data B.

Furthermore, the data selection signal S is at the "L" level (
S=0), the resultant output data SER of the two-input ENOR circuit 21 becomes the negation of the input data A. From this, the contents of the input signals of the three-input negative majority logic circuit 22 are such that the "H" level of the input data A is input to one side, and the "L" level thereof is input to the other side. Therefore, in this case, it is determined by the value of input data B, and the negation of that value is output from the majority logic circuit 22.

The logical formula is shown below.

[0061]

[Math 3]

[0062] However, A and B represent first and second input logical values, S represents a data selection logical value, and Q represents a data selection output logical value, respectively.

[0063] This makes it possible to configure a data selection circuit using the three resonant tunneling bipolar transistors T1 to T3, and it becomes possible to reduce the number of active elements as much as possible compared to the conventional example. Further, by reducing the number of amplification stages, it is possible to speed up the logic output operation.

[0064] This makes it possible to achieve higher integration and higher performance of semiconductor integrated circuit (hereinafter referred to as LSI) devices than in the prior art.

In the embodiment of the present invention, the data selection output logical value Q is directly output from the collector of the third transistor T3, but the driving capability may be increased by using an emitter follower circuit or the like.

[0066]

Effects of the Invention As explained above, according to the logic circuit of the present invention, the first
A second logic operation circuit is provided.

Therefore, the output of the first logic operation circuit can be switched to a value equivalent to the first input data or its negation according to the data selection signal, and the output and the first
, the three signals of the second input data in the second logic operation circuit, the first input data or the second input data
It becomes possible to selectively output either one of the input data.

[0068] This makes it possible to configure a data selection circuit using three resonant tunneling bipolar transistors, making it possible to reduce the number of active elements as much as possible compared to the conventional example. Further, by reducing the number of amplification stages, it is possible to speed up the logic output operation.

This greatly contributes to higher integration and higher performance of semiconductor integrated circuit devices than the conventional example.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram (Part 1) of a logic circuit according to the present invention.

FIG. 2 is a principle diagram (part 2) of the logic circuit according to the present invention.

FIG. 3 is a configuration diagram and a transistor characteristic diagram of a data selection circuit according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of the operation of the two-input ENOR circuit according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram of the operation of the three-input negative majority circuit according to the embodiment of the present invention.

FIG. 6 is a configuration diagram of a data selection circuit according to a conventional example.

[Explanation of symbols]

11...first logic operation circuit, 12...Second logic operation circuit, A...first input data, B...second input data, S...Data selection signal. SER...Computation result data.

Claims (2)

[Claims] 1. A logic circuit that selectively outputs one of first input data (A) or second input data (B) based on a data selection signal (S), wherein the first input data (A) ) and a data selection signal (S); a second logic operation circuit (12) that performs a three-input majority operation based on the result output data (SER) of the logic operation circuit (11);
), the first and second logical operation circuits (11,
12) is an active element (RHET) with negative amplification characteristics.
). 2. The logic circuit according to claim 1, wherein the first logic operation circuit (11) includes a first transistor (T
1) and first to fourth resistance elements (R1 to R4), and the base (B) of the first transistor (T1) is connected to one end of the first to third resistance elements (R1 to R3). is,
The emitter (E) of the first transistor (T1) is the second
The collector (C) of the first transistor (T1) is connected to the first power supply line (VCC) via the fourth resistance element (R4), and the first The other end of the resistance element (R1) is connected to the first input data (
A) is connected to the input part of the second resistance element (R2).
The other end of the third resistance element (R3) is connected to the input part of the data selection signal (S), and the other end of the third resistance element (R3) is connected to the second power supply line (GND). The 2-logic operation circuit (12) has second and third transistors (T2,
T3) and fifth to tenth resistance elements (R5 to R10), and the base (B
) is connected to one end of the fifth to seventh resistance elements (R5 to R7), is connected to the collector (C) of the second transistor (T2), and is connected to the emitter of the second transistor (T2). (E) is connected to the second power line (GND),
The collector (C) of the second transistor (T2) is the eighth
The third transistor (
T3) is connected to the base (B) of the third transistor (T3), and the emitter (E) of the third transistor (T3) is connected to the second power supply line (GND
), the collector (C) of the third transistor (T3) is connected to the first power supply line (VCC) via the tenth resistance element (R10), and the collector (C) of the third transistor (T3) is connected to the first power supply line (VCC) via the tenth resistance element (R10).
5) The other end is connected to the collector (C) of the first transistor (T1), and the sixth resistance element (R6)
The other end is connected to the input part of the second input data (B), and the other end of the seventh resistance element (R7) is connected to the input part of the first input data (A), The base (B) of the third transistor (T3) and the second power supply line (
A logic circuit characterized in that the ninth resistive element (R9) is connected between the ninth resistive element (R9) and GND.