JPH04291439A - Inter-bus connection system - Google Patents

Abstract

PURPOSE:To attain the effective use of a bus by omitting substantially the discontinuation of transfer of the data to the reception side even when the data are transferred to a low speed data transfer bus from a high speed data transfer bus. CONSTITUTION:The dual port memories 13 and 14 which contain the dual ports in a multi-state queue form are provided to the data buses 16, 17, 18 and 19 where a packet bus connection part 11 and processor bus connection part 12 which are connected to a packet bus 40 and a processor bus 50 respectively to fetch the data on both buses and to sent them to the partner buses secure the connection between both buses 40 and 50. Then the data received from both buses 40 and 50 are immediately written into the memories 13 and 14 and transmitted to the partner buses. The transfer of data is discontinued to both buses 40 and 50 of the reception side until all data are transmitted and both memories 13 and 14 become empty as long as these memories store the data. However the data to be transmitted to the buses 40 and 50 are read out concurrently with the end of read of the data and transmitted onto both buses.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-bus connection system for transferring data between two buses.

0002

2. Description of the Related Art Conventionally, in this type of inter-bus connection system, a bus interface unit is provided between the buses, and data transfer on the receiving side bus is continued until the buffer memory of this bus interface unit becomes empty. It was temporarily stopped.

[0003] This will be explained with reference to FIG. FIG. 2 is a block diagram showing an example of this conventional method.

As shown in FIG. 2, a bus interface is provided between a packet bus 40, which is a high-speed data transfer bus, and a processor bus 50, which connects the processor 20 and main memory 30 to construct a system for functional processing. A unit 60 is provided.

The bus interface unit 60 includes a packet bus connection section 61 connected to the packet bus 40 and a processor bus connection section 6 connected to the processor bus 50.
It has 2.

The packet bus connection unit 61 disassembles and temporarily stores data in a packet format received from the packet bus 40 that transfers data at high speed.
After receiving transmission data to be transmitted to the data bus 63 and assembling it into packets, the packets are sequentially transmitted to the packet bus 40.

The processor bus connection section 62 is connected to the packet bus connection section 61 via a control bus 64 to send and receive control signals.
The packet bus connection unit 61 takes out the temporarily stored data received from the packet bus 40 via the data bus 65 and writes it into the main memory 30 via the processor bus 50, while the data received from the processor bus 50 is transferred via the data bus 63. and transfers it to the packet bus connection section 61.

The buffer memory built into the packet bus connection section 61 has a capacity of at most four packets, and is a transfer memory synchronized with the clock of the transmission side bus.

When this buffer memory has stored data, reception of data is stopped until all of this stored data is transferred.

0010

[Problems to be Solved by the Invention] The conventional inter-bus connection method described above requires an interface unit disposed between the buses so that received data is temporarily stored in a small-capacity buffer memory and sent out after changing the clock. For example, when transferring data from a high-speed packet bus to a low-speed processor bus, the buffer memory quickly fills up with data received from the high-speed transfer bus, and the main data is transferred via the processor bus. Writes to memory sequentially, and data transfer on the high-speed transfer bus is temporarily stopped until the buffer memory is all empty.

[0011]Therefore, there has been a problem in that the effect of one processor bus having a low transfer capacity impairs the performance of the other bus having a high transfer capacity.

An object of the present invention is to provide an inter-bus connection system that solves the above problems by providing a duplex port memory as an additional buffer memory between the bus connection parts that connect to each of two buses. be.

[0013]

[Means for Solving the Problems] The bus-to-bus connection method according to the present invention is a bus-to-bus connection method for transferring data between two buses, in which the bus is directly connected to each bus, and the data on the bus is taken in and sent to the other party. On the other hand, the data fetched from the other party is sent to the directly connected bus, and the control bus is connected to the two bus connection parts that are connected to each other and controlled, and the redundant port is in a queue format with multiple stages. and a duplex port memory that temporarily writes data input from one of the bus connection units and then outputs it to the other side, and the duplex port memory that the bus connection unit reads and writes from the bus has all written data. In this case, an instruction to stop data transfer is sent to the receiving bus, and when data is written to the dual port memory from which data to be sent onto the bus is taken out, the data is read out and sent onto the bus at the same time as the writing is completed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.

Bus interface unit 1 shown in FIG.
0 is arranged between the packet bus 40 and the processor bus 50 that connects the processor 20 and the main memory 30, and this configuration is the same as the conventional one. The bus interface unit 10 includes, in addition to a packet bus connection section 11 and a processor bus connection section 12, two duplex port memories 13,
It has 14.

The control bus 15 interconnects the packet bus connection section 11 and the processor bus connection section 12, and also connects to the dual port memories 13 and 14 to transfer control signals.

The data received from the packet bus 40 is
The packet is transferred from the packet bus connection unit 11 to the processor bus connection unit 12 via the data bus 16, the duplex port memory 13, and the data bus 17 in order, and is transferred to the processor bus connection unit 12.
2 writes to main memory 30 via processor bus 50.

Transfer data on the processor bus 50 is received by the processor bus connection unit 12 and transferred to the data buses 18,
The data is sequentially transferred to the packet bus connection section 11 via the duplex port memory 14 and the data bus 19, and the packet bus connection section 11 transmits it to the packet bus 40.

Next, the operation of this embodiment will be explained with reference to FIG.

First, the processor 20 connects to the processor bus 5.
0 to the packet bus 40 is issued to the bus interface unit 10, the processor bus connection section 12 receives the command.

The processor bus connection section 12 connects the main memory 3
Necessary data is read into the duplex port memory 14 in the bus interface unit 10 from the specified address of 0, and when this is completed, a transfer request to the packet bus 40 is issued to the packet bus connection unit 11.

On the other hand, when a transfer request from the packet bus 40 to the processor bus 50 occurs, the packet bus connection section 11 temporarily writes data to the duplex port memory 13 in the bus interface unit 10. At the same time, the processor bus connection unit 12 reads data from the duplex port memory 13 and writes it to the main memory 30.

The duplex port memories 13 and 14 are in the form of a multi-stage queue, and have a storage capacity of, for example, 20 packets. Therefore, the packet bus 4 of the high-speed data transfer bus
The data received and stored by the buffer memory of the packet bus connection section 11 from data bus 11 can be immediately transferred to the duplex port memory 13 via the data bus 16, thereby almost eliminating the need to stop data transfer to the packet bus 40.

The data transferred from the low-speed processor bus 50 to the high-speed packet bus 40 shown in FIG. 1 has sufficient capacity for temporary storage because the buffer memory of the packet bus connection section 11 is used for assembling packets. Redundant port memory may be deleted.

[0025]

[Effects of the Invention] As explained above, in the present invention, a bus interface unit that transfers data between two buses is connected to a bus and a redundant port memory is arranged between a bus connection section that transmits and receives data. By doing so, even when data is transferred from a high-speed bus to a low-speed bus, there is almost no need to instruct the high-speed bus on the receiving side to stop data transfer, and the bus can be used effectively.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an inter-bus connection system of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

10 Bus interface unit 11, 12
Bus connection parts 13, 14 Duplex port memory 15 Control bus

Claims (1)

[Claims] [Claim 1] In a bus-to-bus connection method that transfers data between two buses, a bus is directly connected to each bus, data on the bus is captured and sent to the other party, and data captured from the other party is transmitted to the directly connected bus. At the same time,
The control bus is connected to two bus connection parts that are connected and controlled by a control bus, and the duplex port forms a multi-stage queue, and data input from one of the bus connection parts is temporarily written. and a duplex port memory that is later output to the other bus, and if all the duplex port memories that the bus connection unit takes in from the bus and writes have been written, the bus connection unit sends an instruction to stop data transfer to the receiving bus, while An inter-bus connection method characterized in that when data is written to a dual port memory from which data to be transmitted upward is retrieved, the data is read out and transmitted onto the bus at the same time as the writing is completed.