JPH04291390A - Image display device and clock signal generating circuit for the same - Google Patents

Abstract

PURPOSE:To easily latch signal data by selecting a delay synchronizing signal corresponding to each dot clock through a data selecting means which is controlled with a display mode signal. CONSTITUTION:Delay synchronizing signals H1-Hn selected with adjusted setting signals S1-S3 are supplied from respective data selectors 23-25 to a data selector 26, so one of them is selected according to a mode decision signal and a reference signal at the time of adjustment becomes a reference signal at the time of use as it is. Thus, respective image adjustment switches corresponding to respective mode decision signals from a signal source are set at the time of the adjustment to make image adjustments in those modes. Even when the selection of the dot clock of the signal source is altered during afterward use, the reference signal at the set point of time is automatically selected by a 4th data selector 26, so display data are latched corresponding to the respective display modes without altering the settings and an image at the time of adjustment can be reproduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device and a clock signal generation circuit for the image display device, and more particularly to an image display device suitable as a flat display device such as a liquid crystal display or a plasma display, and images thereof. The present invention relates to a clock signal generation circuit for display devices.

In recent years, flat panel liquid crystal displays, plasma displays, EL displays, and the like have come to be used as image display devices that receive signals from signal sources such as personal computers and display data. These are different from CRT displays,
Since it operates using digital signals, it requires a dot clock to latch the display data sent from the signal source.

[0003] However, in general, in personal computer systems, conventional CR
In addition, the T-display was often used as an image display device, and the dot clock has a high frequency, so if it is transmitted via cables, it will cause radiation noise to the computer itself and other peripheral devices, which is not desirable. Therefore, the dot clock is usually not sent from the personal computer itself.

[0004] Due to the above-mentioned circumstances, in a flat display device or the like that receives display data from a signal source such as a personal computer and displays it, it is necessary to reproduce the necessary dot clock on the display device side. A signal generation circuit is built into or added to the main body of the image display device. When reproducing a dot clock, generally a horizontal synchronization signal, which is one of the synchronization signals sent from a signal source together with display data, is used as a reference point for determining the phase of the dot clock.

[0005]

2. Description of the Related Art One of the conventional clock signal generation circuits will be explained with reference to FIG. The reference signal generation circuit 1 is composed of a delay line 2 which constitutes a delayed synchronization signal generation means, and a data selector 3 which constitutes a delay synchronization signal selection means.
The delay line 2 receives a horizontal synchronizing signal HSYNC from a computer main body (not shown), and generates a large number of delayed synchronizing signals H1 to Hn from this horizontal synchronizing signal. The delayed synchronization signals H1 to Hn have mutually different delay times as shown in FIG. 5(a), and are formed to have respective delay times that differ stepwise from the horizontal synchronization signal HSYNC.

The data selector 3 receives a selection signal SELECT from an image adjustment switch (not shown), selects one of the horizontal synchronization signal and each delayed synchronization signal, and uses this as a reference signal HS for PLL (phase control). The signal is applied to a comparator circuit 4 forming a part of a clock signal reproducing means 8 configured as a synchronous loop) circuit. The PLL circuit 8 includes the comparison circuit 4, a voltage controlled oscillator (VCO) 5, and an N-ary counter 6, and uses the rising phase of the output signal CLK of the voltage controlled oscillator 5 as a reference via the N-ary counter 6 and the comparison circuit 4. For example, synchronize with the falling phase of the signal HS (Figure 5
b). As a result, the clock signal generation circuit generates a clock signal CLK of the optimum phase for latching the display data, and sends this clock signal CL to the main body of the image display device (not shown).
Give K. As a clock signal with an optimal phase, for example, the clock signal CLK3 or CL shown in FIG. 5(c) is used.
K4, in which case the display data DT is latched at the rising edge of the clock signal CLK3 or CLK4 at the central position where the data occurs.

Selection signal SE from the image adjustment switch
LECT is set in the initial adjustment at the time of shipment of this image display device, and in some cases, the setting is changed in readjustment at the site of use, and one of the delayed synchronization signals is selected via the selection signal at the time of these adjustments. This signal is applied to the PLL circuit as a reference signal, and the image device is adjusted to the optimum screen state.

By the way, some personal computers, for example, are equipped with a plurality of dot clock generating means and are activated by selecting any one of the dot clocks. FIG. 6 shows an example of a conventional clock signal generation circuit used in an image display device for this type of signal source. In a signal source that operates with a plurality of dot clocks (three in the case of the figure), information regarding the selection of the dot clocks is outputted by a mode determination signal 11 forming a display mode signal.

Clock signal reproducing means 1 including a PLL circuit
8 is provided with voltage controlled oscillators 13 to 15 that oscillate at the frequency of each dot clock, corresponding to each dot clock, and one of the voltage controlled oscillators is selected by a selector 16 via a mode determination signal 11. Ru. With this configuration, the phase of the output signal CLK of the selected voltage controlled oscillator is synchronized with the phase of the reference signal HS selected by the delay synchronization signal selection means via the N-ary counter 17 and the comparison circuit 12, and as a result, the optimum A clock signal CLK is generated to obtain the image state.

0010

[Problem to be Solved by the Invention] In the case of the above-mentioned conventional clock signal generation circuit used in an image display device with a signal source having a plurality of dot clocks, the reference signal HS is determined to be one by the setting of the image adjustment switch. , the reference signal HS output through the image adjustment switch so as to achieve the optimum image state at one dot clock is independent of display data synchronized with other dot clocks. Therefore, when the selection of the dot clock is changed and the display mode is switched, a problem arises in that the display data cannot be latched unless the image adjustment switch is reset each time.

[0011] In the above case, personal computers have recently become widespread, and the number of users who are unfamiliar with the devices is increasing, and it is difficult to deal with these unfamiliar users, which poses a particular problem.

[0012] Therefore, an object of the present invention is to solve the problems of the conventional clock signal generation circuit and to determine which dot clock is used in a display mode in a signal source that operates with one dot clock selected from a plurality of dot clocks. However, display data can be latched without resetting the image adjustment switch each time, and a clock signal generation circuit for an image display device that is easy to operate, and an image display device equipped with this built-in clock signal generation circuit are provided. The purpose is to provide.

[0013]

FIG. 1 is a block diagram of a clock signal generation circuit according to an embodiment of the present invention.

To achieve the above object, the clock signal generation circuit of the present invention includes display data and a synchronization signal that are synchronized by one dot clock selected from a plurality of dot clocks, as shown in FIG. A clock signal generation circuit for an image display device disposed after a signal source outputting a display signal and a display mode signal corresponding to the selection of the dot clock and displaying the display data on a screen. , delayed synchronization signal generation means (22, 48, 55) which receives the synchronization signal and generates a plurality of delayed synchronization signals each having a different delay time from the synchronization signal; and image adjustment means (41, 42, 43, 51). ) via a selection signal at least in accordance with a configuration signal generated by the selection of
Delayed synchronization signal selection means (23, 24, 25, 49, 55) that selects one from the synchronization signal and each of the delayed synchronization signals and outputs it as a reference signal (35, 50, 56).
and oscillators (28, 29, 30) each oscillating at the same frequency as each of the dot clocks, corresponding to each of the dot clocks, and an output signal of one of the oscillators selected via the display mode signal. A clock signal reproducing means (36) for synchronizing the phase with the phase of the reference signal and outputting the output signal of the selected oscillator, further comprising a data selection means controlled by the display mode signal, The delayed synchronization signal, which is different for each of the oscillators, is selected through the data selection means to be used as the reference signal (3).
5).

[0015]

[Operation] The clock signal generation circuit of the present invention includes data selection means controlled by a display mode signal, and the delayed synchronization signal, which is different for each oscillator, is selected through the data selection means, and the reference signal (35 ), once the image is adjusted under each display mode signal using the setting signal of the image adjustment means, the display mode will remain the same even if the oscillator selection is changed when changing the display mode. A reference signal corresponding to each oscillator during adjustment is output according to the signal, and display data can be latched without requiring reset by the image adjustment means.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A clock signal generation circuit according to an embodiment of the present invention will be described with reference to FIG. In the figure, this clock signal generation circuit includes four data selectors 23 to 26 within a reference signal generation circuit 21. First to third data selectors 23 to 25, which constitute delayed synchronization signal selection means, receive n types of delayed synchronization signals H1 to Hn from delay signal generation means (delay line) 22 and horizontal synchronization signal HSYNC from the outside. In response to input setting signals S1 to S3 from respective image adjustment switches (not shown), one delayed synchronization signal or horizontal synchronization signal, which is one of the input signals, is output to the fourth data selector 26 constituting data selection means. do.

The fourth data selector 26 receives signals from the first to third data selectors 23 to 25, and selects the first to third data selectors according to the mode determination signal (display mode signal) MODE.
One of the output signals of the third data selectors 23 to 25 is selected and outputted as a reference signal 35 for a clock signal reproducing means 36 including a PLL circuit. The PLL circuit of the clock signal reproducing means 36 includes a comparison circuit 27 that serves as a phase comparator.
, three voltage controlled oscillators 28 to 30 corresponding to the type of dot clock of the signal source, and an N-ary counter 32 , and the N-ary counter 32 includes a decoder 33 and a counter 34 .

Each of the voltage controlled oscillators 28 to 30 provides an output signal of, for example, frequencies of 15, 20 and 25 MHz to a fifth data selector 31 forming a part of the clock signal reproducing means 36. The fifth data selector 31 receives the outputs of the voltage controlled oscillators 28 to 30, selects the output of one of the voltage controlled oscillators according to the mode determination signal MODE, and applies the selected output to the counter 34 of the N-ary counter 32. The data decoder 33 decodes the output of the counter 34 and outputs the fall of the most significant bit thereof to the comparison circuit 27. Comparison circuit 27 compares the falling phase of reference signal 35 and the output of decoder 33, and if there is a difference between them, outputs the difference as a control voltage signal to each voltage controlled oscillator 28-30.

With the above configuration, this clock signal generation circuit operates as follows. The horizontal synchronization signal HSYNC and each delayed synchronization signal H1 which is the output of the delay line 22
~Hn is selected one by one through the setting signals S1 to S3 of the image adjustment switch corresponding to each display mode in each of the first to third data selectors 23 to 25, and outputted as selection signals SELECT1 to SELECT3, respectively. Ru. When a specific mode determination signal MODE is applied to the fourth data selector 26, the image is adjusted to the optimum image state in that mode through the setting adjustment of the corresponding one image adjustment switch. This adjustment is similarly performed in each of the other modes.

During actual use, the image adjustment switch is maintained as set above, and each data selector 23 to
25, each one of the delayed synchronization signals selected by the respective adjusted setting signals is sent to the fourth data selector 26.
Since one of them is selected according to the mode determination signal MODE, the reference signal at the time of adjustment is selected as is and becomes the reference signal at the time of use.

As described above, during adjustment, by setting each image adjustment switch corresponding to each mode determination signal from the signal source, image adjustment in that mode is performed, and during subsequent use, the dot clock of the signal source is Even if the selection is changed, the reference signal at the time of setting is automatically selected by the fourth data selector 26, so there is no need to change the settings each time, and the display data is changed corresponding to each display mode. is latched and the image at the time of adjustment is reproduced. In the case of the above embodiment, an image adjustment switch and a delay synchronization signal selection means are provided corresponding to each display mode.

FIG. 2 is a block diagram of a reference signal generation circuit and an image adjustment switch, which are essential parts of a clock signal generation circuit according to a second embodiment of the present invention. In the figure, image adjustment switches 41, 42, and 43 are each configured as a 4-bit code switch, and each code switch 41, 42, and
, 43 are processed into 4-bit selection signals D1 to D4 through first and second data selectors 44 and 46 and an adder 45, which constitute data selection means. A third data selector 49 receives the horizontal synchronizing signal HSYNC and each delayed synchronizing signal H1 to Hn of the delay line 48 as input.

The mode determination signals MODE1 and MODE2 are input to this clock signal generation circuit as 2-bit signals, and each bit is applied to the first and second data selectors 44 and 46, respectively. The first data selector 44 receives the signals of the second and third code switches 42 and 43, and outputs the signal of one of the code switches according to the first bit MODE1 of the mode determination signal.

The adder 45 is connected to the first code switch 41
and the output of the first data selector 44 are inputted and added, and a 4-bit output signal excluding the most significant bit is given to the second data selector 46. The second bit MODE2 of the mode determination signal is input to the second data selector 46 as a control signal, and the second data selector 46 selects the second bit MODE2 of the mode determination signal.
2, the output of the first code switch 41 or the adder 45 is applied as selection signals D1 to D4 to the third data selector 49, which constitutes delayed synchronization signal selection means.

In the case of the second embodiment, first, the second bit MODE2 of the mode determination signal is set to "1",
Initial image adjustment is performed by setting the first code switch, and then by setting the second code switch by setting the first bit MODE1 of the mode determination signal to "1" and the second bit MODE2 to "0". Further, initial image adjustment is similarly performed by setting both bits of the mode determination signal to "0" and setting the third code switch. In actual use, according to the mode determination signal from the signal source,
The signals from each code switch are input to the third data selector 49 as selection signals D1 to D4 with exactly the same values as at the time of initial image adjustment, and the delayed synchronization signal at the time of adjustment is the reference according to each display mode. The signal is input as a signal to the comparison circuit of the PLL circuit of the clock signal reproducing means.

If the optimum image condition cannot be obtained with the initial adjustment due to some reason, such as temperature fluctuation, and image adjustment is required again, the first code switch 41 changes the settings in each display mode. used. Normally, such fluctuations vary in the same way in each display mode, so by changing the settings in any display mode, it can be expected to obtain an optimal image state in all display modes, which is convenient for use.

FIG. 3 is a block diagram of the main parts of the clock signal generation circuit of the third embodiment. In the case of the figure, the selection signal SELECT is generated by one code switch 51 and a nonvolatile memory 52 forming data selection means. In the case of this embodiment, the address of the nonvolatile memory 52 is specified by mode determination signals MODE1 and MODE2 similar to the second embodiment, and the signal of the code switch 51 is stored at the address according to each display mode. With this configuration, the setting signal S7 of the code switch 51 at the time of initial adjustment is read from the corresponding address in accordance with the mode determination signals MODE1 and MODE2 from the signal source even during use and becomes a selection signal, thereby forming a delayed synchronization signal selection means. The data is applied to the data selector 55.

In the third embodiment, when readjustment of the image is required, the code switch 51 is set again in the same manner in the mode concerned, and the data at the address concerned is rewritten. In the case of this embodiment, unlike the case of the second embodiment,
It is likely that each mode will require readjustment.

[0029]

As explained above, according to the present invention, the selection signal can be switched according to the display mode signal and the reference signal can be selected for each oscillator, so that even when changing the selection of the dot clock, readjustment of the image adjustment means is not necessary. The image state at the time of adjustment can be automatically selected without any need, and it has been possible to provide a clock signal generation circuit for an image display device with good operability and an image display device incorporating the clock signal generation circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the invention.

FIG. 2 is a block diagram of a second embodiment of the invention.

FIG. 3 is a block diagram of a third embodiment of the invention.

FIG. 4 is a block diagram of a conventional clock signal generation circuit having one VCO.

FIG. 5 is an explanatory diagram of display data latching, (a) is an explanatory diagram of a delayed synchronization signal, (b) is an explanatory diagram of phase synchronization, (c)
is an explanatory diagram of the optimum phase for latch.

FIG. 6 is a block diagram of a conventional clock signal generation circuit having multiple VCOs.

[Explanation of symbols]

HSYNC
Horizontal synchronization signal H1 to Hn
Delayed synchronization signals S1 to S7
Setting signal 22, 4
8, 54 Delayed synchronization signal generation means 23-25, 49, 55 Delayed synchronization signal selection means 26, 44-46, 52
Data selection means 28-30
Voltage controlled oscillator 36
Clock signal regeneration means including PLL circuit

Claims (4)

[Claims] 1. A signal that outputs a display signal including display data and a synchronization signal synchronized by one dot clock selected from a plurality of dot clocks, and a display mode signal corresponding to the selection of the dot clock. A clock signal generating circuit for an image display device disposed after a source and displaying the display data on a screen, the clock signal generation circuit comprising a plurality of delay synchronizers each receiving the synchronization signal and each having a different delay time from the synchronization signal. Delayed synchronized signal generation means (
22, 48, 55) and image adjustment means (41, 42, 4
One of the synchronization signal and each of the delayed synchronization signals is selected via a selection signal that at least follows the setting signal generated by the selection of the reference signal (35, 51).
delay synchronization signal selection means (23
, 24, 25, 49, 55) and oscillators (28, 29, 30) that oscillate at the same frequency as each dot clock.
) corresponding to each of the dot clocks, synchronizing the phase of the output signal of one of the oscillators selected via the display mode signal with the phase of the reference signal, and synchronizing the output signal of the selected oscillator with the phase of the reference signal. Output clock signal reproducing means (
36), further comprising data selection means controlled by the display mode signal, through which the delayed synchronization signal, which is different for each of the oscillators, is selected and the reference signal (35) A clock signal generation circuit comprising: 2. The clock signal generation circuit according to claim 1, wherein the reference signal for each oscillator is obtained from one image adjustment means (41, 51) common to each oscillator. 3. A memory circuit (52) having a memory cell for storing setting signals for each of the oscillators, and an address of each memory cell is specified by the display mode signal. 2. The clock signal generation circuit according to 2. 4. An image display device incorporating the clock signal generation circuit according to claim 1.