JPH04289936A - Memory control circuit - Google Patents

Abstract

PURPOSE:To improve the performance of memory diagnosing and memory write speed, etc. CONSTITUTION:This circuit is provided with a memory part 3 which has plural pieces of memories constituted of a dynamic CMOSRAM and can read and write data against a microprocessor 1, a memory control part 2 for controlling a read/write operation of the data to the memory part, an input/output address control part 4 which is controlled by the microprocessor and outputs a control signal to a register control part, and a register control part 5 for designating a write system of the data to the memory part to the memory control part by a control signal from the input/output address control part, and at the time of writing the same data to plural memories, the same data is written to plural memories set to the input/output address by writing the data to the input/output address once before writing it.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit used in a data processing device controlled by a microprocessor.

0002

2. Description of the Related Art FIG. 6 is a block diagram showing an example of a conventional memory control circuit, and FIG. 7 is a block diagram showing details of the memory control section of the example shown in FIG. 3 is a block diagram showing details of the memory section of the embodiment of FIG. 1 and the example of FIG. 6, and FIG. 8 is a correspondence between address signals in the memory section of FIG. 3 and row address select signals output therefor. It shows.

A conventional memory control circuit used in a data processing device controlled by a microprocessor includes a memory unit having a plurality of memories that can read and write data to and from a microprocessor 101, as shown in FIG. 3, and a memory control unit 1 that controls reading and writing operations of the memory unit 3.
02.

As shown in FIG. 3, the memory section 3 has 9 bits of input address signals (S0 to S8), 8 bits of output data signals (T0 to T3), and 4 control signals (
E0, E1, WE, OE), and the capacity is 104857
When configured with 16 6-bit dynamic CMOS RAMs, the capacity of one memory (MEM) is 10
Since there are 48,576 bits and the output data signal is 4 bits, one memory (MEM) has 262,144 words, that is, 524,288 bytes, and the address is 4 bits. Assuming that the microprocessor 101 that reads and writes data to and from the memory unit 3 is a 16-bit microprocessor, the data signal is DA0 to DA15, has a capacity of 524288 bytes, and has an address as shown in FIG. If 4-bit memory (MEM) is used, the output data signal requires 16 bits, so by using 4 memories (MEM), 524288
You can read and write data up to bytes. The microprocessor 91 can control 16 bytes with a 4-bit address. Therefore, 524,288 bytes of memory (M
In order to control EM), it is expressed in hexadecimal notation (00
Addresses from (0000) to (07FFFF) are required. In FIG. 3, memories (MEM) 40 and 41
and memory (MEM) 48 and 49, RAU0 (Row Address Uppe
r 0 Bank) signal and RAL0 (Row
Address Lower 0 Bank)
The signal goes from address (000000) to address (07
FFFF), the decoder (DEC) 7 shown in FIG.
4 by AND gate 82 and OR gates 80 and 9
0 is selected and the RAU0 signal and RAL0 signal are output (see FIG. 7). Also, the lower byte D of the data signal
Memories 48 and 49 on A0-7 side and upper byte DA
Switching between the memories 40 and 41 on the sides 8 to 15 is performed using address 0 (AD) output from the microprocessor 101.
0) Signal and UBE (Upper Byte Ena)
ble) signal.

Similarly, 52 is used for memories (MEM) 42 and 43 and memories (MEM) 50 and 50.
Since 4288 bytes can be controlled, the input address of the decoder (DEC) 74 is AD1 from address (080000) to address (0FFFFF).
9, AND gate 83, OR gate 87 and 9
1 is selected and the RAU1 signal and RAL1 signal are output (see FIG. 7), and the memories (MEM) 42 and 43 are output.
and memories (MEM) 50 and 51 are selected.

Therefore, in the memory configuration shown in FIG.
The memory capacity is 24288 x 4 = 2097152 bytes, and the addresses to control all memories are from address (000000) to address (1FFFFF).
becomes. Among other control signals for the memory, the memory read signal MRD and the memory write signal MWR are common to all memories, and the column address upper byte signal CAU is for the upper byte side memory.
The column address lower byte signal CAL is common to the memories on the lower byte side.

FIG. 8 is a correspondence diagram showing the correspondence between addresses, RAU0-3 signals and RAL0-3 signals output correspondingly, and memories selected thereby in the above-mentioned memory configuration. be.

[0008]

[Problems to be Solved by the Invention] In the conventional memory control circuit as described above, when writing the same data to each bank of memory constituting the memory section, the control signal is low in the memory of each bank. Address select signal (RAU
There is a drawback that writing must be performed by switching between RAL0-3 signals and RAL0-3 signals.

[0009]

[Means for Solving the Problems] A memory control circuit of the present invention is a memory control circuit used in a data processing device controlled by a microprocessor.
a memory section that has a plurality of memories configured with MOSRAMs and is capable of reading and writing data to and from the microprocessor; a memory control section that controls data reading and writing operations with respect to the memory section; an input/output address control section that is controlled by a processor and outputs a control signal to the register control section; and a control signal from the input/output address control section that specifies to the memory control section a method of writing data to the memory section. and the register control section.

0010

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing details of the memory control section of the embodiment of FIG. 1, and FIG. 3 is a block diagram of the embodiment of FIG. 1 and the example of FIG. 4 is a block diagram showing details of the input/output address control section and register control section of the embodiment of FIG. 1; FIG. 5 is a waveform diagram showing the operation of the memory control section of FIG. 2;
FIG. 9 is a correspondence diagram showing a correspondence relationship between data set in an input/output address and a memory bank set signal outputted in the register control section of FIG. 4.

In FIG. 1, the microprocessor 1 includes:
Address 0 is sent to the memory control unit 2 as a control signal 6.
~20 signals and reset signals RST and UBE (U
p-per Byte Enable) signal, a refresh signal REF, a read signal RD, a write signal WR, and a clock signal CLK. 15, and when reading data, data signals DA0 to DA15 are input together with the read signal RD.

The microprocessor 1 also sends input/output address signals AD1-2 and an input/output address write signal I as control signals 9 to the input/output address control unit 4.
OWR is output. The register control unit 5 receives register setting data signals DA12 to DA12 as control signals 11.
15 and a reset signal RST.

As shown in FIG. 4, the input/output address control section 4 includes a decoder (D) having a 2-bit input and a 4-bit output.
EC) 40, which outputs a register latch signal as a control signal 10 to the register control unit 5.

The register control unit 5, as shown in FIG.
It consists of a decoder 56 with 2 bits of input and 4 bits of output, and as a control signal 10 to the register control section 5,
Outputs register latch signal. The register control unit 5 is
It is composed of four D type flip-flops 57 to 60, and as a control signal 12 to the memory control section 2,
Outputs memory bank set signals MS0 to MS3 for selecting each bank of memory.

As shown in FIG. 2, when the microprocessor 1 reads data from the memory, the memory control unit 2 converts the read signal RD output from the microprocessor 1 into D.
A clock signal CLK is input to the data terminal 0A of a type flip-flop (flip-flop) 16, and the latch terminal CP thereof. Therefore, the MRD signal obtained by latching the read signal RD at the rising edge of the clock signal CLK is output to the data output terminal T0 of the flip-flop 16 to the memory section 3. Also, flip-flop 16
The input signal XIII of the master reset terminal MR is +5
The reset signal RST output from the microprocessor 1 is connected to the master set terminal MS.
, the data output terminal T0 of the flip-flop 16 is initially set to a high level when the power is turned on. Flip-flops 17-21 are similarly set. Since the input signals of the master reset terminal MR and master set terminal MS of the flip-flop 15 are opposite to those of the flip-flop 16, the input signals of the flip-flop 15 are reversed to the data output terminal T0 when the power is turned on.
is initially set to low level. FIG. 5 is a waveform diagram of the MRD signal outputted to the memory section 3 in this manner.

The write signal WR output by the microprocessor 1 when writing data into the memory is the read signal R.
Similarly to D, the MWR signal is latched in the flip-flop 17 at the rising edge of the clock signal CLK and is output to the memory unit 3. FIG. 5 also shows the waveform of the MWR signal outputted to the memory section 3 in this manner.

Since each of the memories 40 to 55 in the memory section 3 is a dynamic CMOS RAM, control signals are sent to the row address select terminal E0, column address select terminal E1, write terminal WE, and output enable terminal OE to control them. needs to be input, but the write terminal WE and output enable terminal OE are
The above MWR signal and MRD signal are respectively input. Since the control signal for the column address select terminal E1 must be input when reading data from the memory section 3 and when writing data to the memory section 3, the MR
The output signal of the flip-flop 16 controlling the D signal and the output signal of the flip-flop 17 controlling the MWR signal are input to the AND gate 34, and the output signal of the AND gate 34 is input to the two-input OR gate 35 and the output signal of the flip-flop 17 controlling the MWR signal. In addition, in order to select the lower byte side of the memory section 3, the UBE (Upper Byte Enable) signal is input from the microprocessor 1 to the OR gate 35, and the UBE (Upper Byte Enable) signal is input from the microprocessor 1 to the OR gate 36.
The AD0 signal of the least significant bit of the address is input from the address. As a result, the OR gate 35 outputs a signal when the memories 40 to 47 on the upper byte side are selected, and the OR gate 36 outputs a signal when the memories 40 to 47 on the lower byte side are selected.
A signal is output when 55 is selected.

Memory 40 on the upper byte side of the memory section 3
C input to column address select terminal E1 of ~47
The AU signal inputs the output signal of the OR gate 35 to the data terminal 0A of the flip-flop 18, and outputs the latch terminal C.
The clock signal CLK is input to P, and the signal latched at the rising edge is input to the data terminal 0A of the flip-flop 19, and the clock signal CL is input to the latch terminal CP.
The output signal of the flip-flop 18 is latched at the falling edge of the clock signal CLK by inputting a signal obtained by inverting K at the NOT gate 39. Similarly to the CAU signal, the CAL signal input to the column address select terminal E1 of the memories 48 to 55 on the lower byte side is input by inputting the output signal of the OR gate 36 to the data terminal 0A of the flip-flop 20, and inputting the clock signal to the latch terminal CP. CLK is input and a signal latched at the rising edge of the clock signal is input to the data terminal 0A of the flip-flop 21, and a signal obtained by inverting the clock signal CLK by the NOT gate 39 is input to the latch terminal CP. This is a signal obtained by latching the output signal of CLK at the falling edge of clock signal CLK. FIG. 5 also shows a waveform diagram of the CAU signal and CAL signal outputted to the memory section 3 in this manner.

Since each of the memories 40 to 55 in the memory section 3 is a dynamic CMOS RAM, the memories 40 to 55
The address output for each memory is RAU0 to RAU3 or RAU3 to the row address select terminal E0 of each memory.
When outputting AL0 to AL3, the row address must be output, and the CAU signal or CAL signal must be output to the column address select terminal E1. Therefore, the address signals AD1 to AD9 output by the microprocessor 1 are input to the XA terminal of the selector 13, and the address signals AD10 to AD18 output by the microprocessor 1 are input to the selector 13.
By inputting to the XB terminal of 3, the S of selector 13
When the 0 terminal is at a low level, the selector 13 uses the address signals AD1 to AD9 input to the XA terminal as a row address.
Outputs from the TX terminal of the memory unit 3 to the selector 1.
When the S0 terminal of the selector 13 is at a high level, the address signals AD10 to AD18 input to the XA terminal are outputted from the TX terminal of the selector 13 to the memory section 3 as row addresses. The CAG signal input to the S0 terminal of the selector 13 must be input both when reading data from the memory section 3 and when writing data to the memory section 3.
The output signal of the flip-flop 16 controlling the signal and the output signal of the flip-flop 17 controlling the MWR signal are input to the AND gate 34.
4 output signal to the data terminal 0A of flip-flop 15.
A clock signal CLK is input to the latch terminal CP, and a signal obtained by latching the output signal of the AND gate 34 at the rising edge of the clock signal CLK is output from the output terminal F0 of the flip-flop 15 as a CAG signal. Moreover, the output terminal F0 of the flip-flop 15 has
Since a signal obtained by inverting the signal output from the output terminal T0 of the flip-flop 15 is also input, the CAG signal output from the output terminal F0 becomes a switching signal between the row address and column address in the selector 13. In Figure 5,
The CAG output to the selector 13 in this way
The waveform of the signal is also shown.

The control signal for the lower address select terminal E0 of each of the memories 40 to 55 in the memory section 3 is divided into an upper byte side and a lower byte side, by converting the output signal of an AND gate 34 into an OR gate 35 and an OR gate 36.
The UBE signal from the microprocessor 1 is input to the other input terminal of the OR gate 35, and the AD0 signal of the least significant bit of the address is input from the microprocessor 1 to the other input terminal of the OR gate 36. input. Therefore, the output signal of the OR gate 35 is output when controlling the upper byte side, and the output signal of the OR gate 36 is output when controlling the lower byte side. The output signal of the OR gate 35 is inputted to the AND gate 37, the output signal of the OR gate 36 is inputted to the AND gate 38, and the refresh signal REF outputted by the microprocessor 1 (each memory 40 to 55 of the memory section 3 is a dynamic CMOS RAM) is input. Therefore, refresh is required periodically, and when refresh is performed, a refresh signal REF is output from the microprocessor 1) is input to the AND gates 37 and 38. As a result, the refresh signal R from the microprocessor 1
When EF is being output, a row address select signal is unconditionally output. The output signal of the AND gate 37 is input to the OR gates 26 to 29 to select signals RAU0 to 3 to be output to the lower address select terminals E0 of the memories 40 to 47 on the upper byte side of the memory section 3. For memories 40 and 41, the address (000000
) to (07FFFF), address signals AD19 and AD20 are used as the two input signals of the decoder 14. When address signals AD19 and AD20 are both at low level, the output signal from output terminal F0 of decoder 14 is enabled, and AND gate 22 and OR gates 26 and 30 are enabled.
is selected. For the memories 42 and 43, the signal RAU1 is output from address (080000) to (0FFFFF), so it must be
The output signal from output terminal F1 of decoder 14 is input to AND gate 23, and OR gates 27 and 31 are selected. When memory refresh control is performed, a refresh signal REF is input from the microprocessor 1 to the AND gates 22 to 25 in order to select all row address signals regardless of the output of the decoder 14.

Addresses for controlling all memory spaces in the memory section 3 are from (000000) to (1FFFF
F) and is controlled by the output signal of the decoder 14 so that the row address select signals RAU0-3 and RAL0-3 are switched every 524288 bytes. Address at this time and row address select signal RAU0-3
- The correspondence relationship with RAL0-3 is as shown in FIG.

As shown in FIG. 3, the memory unit 3 has a 9-bit address input (S0 to S8) and a 4-bit data output.
bits (T0 to T3), and four control signals (E0,
E1, WE, OE), 1 with a capacity of 1048576 bits
6 dynamic CMOS RAM memories 40-55
It consists of Since the microprocessor 1 is a 16-bit microprocessor, the total capacity of the memory section 3 is 524288 bytes x 4 = 2097152 bytes, and the address necessary to control this is expressed in hexadecimal notation (000000 ) to (1FFFFF).

The input/output address control unit 4, as shown in FIG. Address signal A
D2 and AD1 input. Further, an input/output write signal IOWR outputted when the microprocessor 1 writes an input/output address is input to the enable terminal E0. On the other hand, the output signal from the output terminal F1 of the decoder 56 is output to the register control section 5. The output signal from the output terminal F1 is enabled when the input/output write signal IOWR is input to the enable terminal E0 and the input signal at the input terminal S1 is at a high level. Since the address signal AD1 is input to the input terminal S1, by setting the input/output address (20) as the input/output write signal IOWR, the output signal from the output terminal F1 of the decoder 56 is enabled.

The register control unit 5, as shown in FIG.
4 D-type flip-flops (DF) 57-60
The data signal DA12 output from the microprocessor 1 is input to the data input terminal 0A of the flip-flop (DF) 57, and the flip-flop (DF)
The data signal DA13 output from the microprocessor 1 is input to the data input terminal 0A of the DF) 58, and the data signal DA14 output from the microprocessor 1 is input to the data input terminal 0A of the flip-flop (DF) 59.
The data signal DA15 output from the microprocessor 1 is input to the data input terminal 0A of the flip-flop (DF) 60. An output signal from the output terminal F1 of the decoder 56 of the input/output address control section 4 is commonly input to these latch terminals CP. Further, the master set terminal MS is pulled up to +5v (XIII), and the reset signal RST of the microprocessor 1 is input to the master reset terminal MR. Therefore, when the power is turned on, the flip-flops (DF) 57 to 60 have output terminals T
0 is initially set to a low level, and the output terminal F0 is initially set to a high level.

Since the flip-flop (DF) 57 latches the data signal DA12 inputted to the data input terminal 0A by the output signal of the decoder 56, the data signal DA12 input to the data input terminal 0A is latched by the output signal of the decoder 56. Signal MBS0 is input/output address (2
Output by writing data (1000) to 0). Further, the flip-flop (DF) 58 converts the data signal DA13 input to the data input terminal 0A into the decoder 56.
The memory bank set 1 bank signal MBS1 from the output terminal F0 of the flip-flop (DF) 58 is latched by the output signal of the input/output address (20).
Output by writing data (2000) to. Similarly, the flip-flop (DF) 59 has an output terminal F
Memory bank set 2 bank signal MBS2 from 0,
Data (4000) is written to input/output address (20), and flip-flop (DF) 60 receives memory bank set 3 bank signal MBS3 from output terminal F0 and writes data (8000) to input/output address (20). Write. When writing data (3000) to input/output address (20), a memory bank set 0 bank signal MBS0 and a memory bank set 1 bank signal MBS1 are output. In this way, depending on the data written to the input/output address (20), 16 signals combining the four memory bank set signals described above are output as shown in FIG.

Each memory bank set signal (MBS) is output to write data to input/output address (20).
0 to MBS3) are input to the AND gates 22 to 25 of the memory control unit 2, respectively, so the memory bank set 0
When the bank signal MBS0 is output, the AND gate 22 is selected regardless of the output of the decoder 14,
Since the OR gates 26 and 30 are selected by the output of the AND gate 22, the RAU0 signal and the RAL0 signal are output, and the memories 40 and 41 and 48 and 49 of the memory section 3 are selected. Similarly, when the memory bank set 1 bank signal MBS1 is output,
When memories 42 and 43 and 50 and 51 are selected and memory bank set 2 bank signal MBS2 is output, memories 44 and 45 and 52 and 53 are selected and memory bank set 3 bank signal MB is output.
When S3 is being output, memories 46 and 47 and 54 and 55 are selected.

Therefore, by writing data to the input/output address (20) and then writing the data to the memory with a capacity of 524,288 bytes, the data can be written to the multiple memories of 524,288 bytes set at the input/output address. It becomes possible to write the same data.

In this way, in the conventional memory control circuit, when writing the same data every 524,288 bytes, data was written to each address, whereas in this embodiment, the data is written to each address. After writing data to output address (20), from address (000000) to (
By writing data up to 07FFFF), the same data can be written to the 524288-byte memory set at that input/output address.

[0030]

Effects of the Invention As explained above, when writing the same data to multiple memories, the memory control circuit of the present invention writes the data to the input/output address once before writing, thereby making it possible to write the data to the input/output address. Since the same data can be written to a plurality of established memories, it is possible to improve performance such as memory diagnosis and memory writing speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing details of a memory control unit in the embodiment of FIG. 1;

FIG. 3 is a block diagram showing details of the memory of the embodiment of FIG. 1 and the example of FIG. 6;

FIG. 4 is a block diagram showing details of an input/output address control section and a register control section in the embodiment of FIG. 1;

FIG. 5 is a waveform diagram showing the operation of the memory control section in FIG. 2;

FIG. 6 is a block diagram showing an example of a conventional memory control circuit.

FIG. 7 is a block diagram showing details of a memory control unit in the example of FIG. 6;

8 is a correspondence diagram showing a correspondence relationship between addresses in the memory section of FIG. 3, RAU and RAL signals output thereto, and memories selected by the addresses; FIG.

9 is a correspondence diagram showing a correspondence relationship between data set to an input/output address and a memory bank set signal outputted in the register control section of FIG. 4; FIG.

[Explanation of symbols]

1 Microprocessor 2 Memory control section 3 Memory section 4 Input/output address control section 5 Register control section 6-12 Control signal 13 Selector 14/56 Decoder 15-21/57-60 Flip-flop 22
~25・34・37~38 ANDGATE 26~
33.35-36 Or Gate 40-55
memory

Claims (1)

[Claims] 1. A memory control circuit used in a data processing device controlled by a microprocessor, the circuit having a plurality of memories configured of dynamic CMOS RAMs and capable of reading and writing data with the microprocessor. a memory section, a memory control section that controls data read/write operations with respect to the memory section, an input/output address control section that is controlled by the microprocessor and outputs a control signal to the register control section, and the input/output address control section. 1. A memory control circuit comprising: the register control section that specifies a data write method for the memory section to the memory control section based on a control signal from the memory section.