JPH04289935A - Computer system - Google Patents

Abstract

PURPOSE:To reduce the execution step for a transfer, and to execute the processing at a high speed by dividing a transfer of a fraction part before and after a memory to be transferred, and a transfer of 8 bytes each from an 8-byte boundary in which the memory is accessed quickly. CONSTITUTION:A storage device 4 contains many memory areas 7 constituted of plural registers R1-Rn of arbitrary length of >=256 bytes for storing the data by an 8-byte boundary unit. In a processor 6 of a controller 1, at the time of executing a transfer to one memory area 7, data of a fraction byte to a first 8-byte boundary is transferred by a heat processing means 8. Subsequently, the data is transferred by an 8-byte unit at every 8-byte boundary by an intermediate processing means 9, and the data of a fraction the tail end byte of less 8 bytes is transferred by a tail end processing means 10.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is directed to RISC (Reduc
ed Instruction Set Compute
er) is used for memory transfer in computer equipment. The present invention relates to a computer device that can speed up memory transfer processing.

0002

2. Description of the Related Art Conventionally, memory-to-memory transfer in a RISC-based computer device is performed using CISC (Complex In
Since there is no character string transfer instruction unlike in a computer system using the ``Struction Set Computer'' method, loads and stores are repeated on registers one byte at a time.

0003

[Problem to be Solved by the Invention] Conventional memory-to-memory transfer from an 8-byte boundary using a RISC computer system that allows quick memory access in 8-byte units repeatedly loads or stores each byte on a register. Because of this, there was a problem that the processing speed performance originally provided could not be achieved.

[0004] The present invention solves these problems and aims to provide an apparatus that can reduce the number of execution steps for data transfer and increase processing speed.

[0005]

[Means for Solving the Problems] The present invention includes a control device and a storage device, the control device includes an arithmetic unit and a processing device, and the storage device stores data in units of 8-byte boundaries.256 In a computer device including a large number of memory areas having an arbitrary length of bytes or more, the processing device includes a first processing means for transferring fractional byte data up to a first 8-byte boundary when transferring data to one memory area; , an intermediate processing means for transferring data in 8-byte units at every 8-byte boundary, a tail processing means for transferring data of fractional bytes less than the last 8 bytes, and means for starting each of the means in the above-mentioned order. It is characterized by having the following.

[0006]

[Operation] When transferring data to a memory area of arbitrary length of 256 bytes or more, first transfer fractional bytes up to the first 8-byte boundary, then 8 bytes at each 8-byte boundary. Finally, the last fractional bytes less than 8 bytes are transferred.

In this way, by separately performing the transfer of the fractional portion before and after the number of bytes to be transferred and the transfer of 8 bytes at a time from the 8-byte boundary where memory access is quick, the execution steps for the transfer can be simplified. can be reduced and processing speed can be increased.

[0008]

Embodiments Next, embodiments of the present invention will be explained based on the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

The embodiment of the present invention includes a control device 1 and an input device 2.
, an output device 3, and a storage device 4, the control device 1 includes an arithmetic device 5 and a processing device 6, and the storage device 4 includes:
It includes a large number of memory areas 7 consisting of a plurality of registers R1 to Rn of any length of 256 bytes or more, which store data in units of 8-byte boundaries. When transferring data to the memory area 7, there is a first processing means 8 that transfers fractional byte data up to the first 8-byte boundary, an intermediate processing means 9 that transfers data in 8-byte units at every 8-byte boundary, and a last processing means 8 that transfers data in fractional bytes up to the first 8-byte boundary. The last processing means 10 transfers fractional byte data of less than 8 bytes, and means for activating each of the means in the order described above is provided.

Next, the operation of the embodiment of the present invention constructed as described above will be explained. FIG. 2 is a flowchart showing the overall flow of data transfer processing in the embodiment of the present invention, FIG. 3 is a flowchart showing the flow of the head processing in the embodiment of the invention, and FIG. 4 is a flowchart showing the flow of intermediate processing in the embodiment of the invention. , FIG. 5 is a flowchart showing the flow of the tail end processing in the embodiment of the present invention, and FIG. 6 is a diagram illustrating the operation when transferring from memory area X to memory area Y in the embodiment of the present invention.

[0011] As shown in FIG. 2, the processing in the embodiment of the present invention is comprised of a header process (S1), an intermediate process (S2), and a tailer process (S3).

First, the leading processing means 8 performs the leading processing (S
In 1), as shown in FIG. 3, fractional bytes up to the first 8-byte boundary are transferred. In other words, the transfer source X shown in FIG.
The 8-byte boundary address Px including the first address of the transfer destination Y and the similar address Py of the transfer destination Y are determined (step 11). At this time, offsets a and b within the 8-byte boundary from Px and Py to X and Y are also obtained at the same time. Next, 16 bytes from Px are loaded into consecutive registers R1 and R2, each having a length of 8 bytes, and 8 bytes from Py are loaded into register R3, which is also 8 bytes long (step 12).

Next, the magnitudes of the byte offset a from Px to X and the byte offset b from Py to Y are compared (step 13). When a≧b, a-b
is the shift number s, the processing flag f is turned off, and the registers R1 and R2 are double shifted to the left by s bytes (with a shift command for two consecutive registers, in the case of a left shift, the contents of the lower registers do not change).

When a<b, the shift number s is set to b-a, the processing flag f is turned on, and the register R1 is shifted to the right by s bytes (steps 14 to 17).

Next, the information to be stored in the 8 bytes pointed to by Py on register R3 is created by an AND or OR instruction of the shift of register R1 and the mask data (
Steps 18-1a). Here, mask 1 is 8-byte data in which the upper b bytes are zero and the rest are all ones. Mask 2 is a capture number of Mask 1, and mask data is created by a mask generation command.

After that, store the contents of register R3 in the location pointed to by Py (step 1b), subtract the (8-b) bytes just transferred from the number of bytes to be transferred, and obtain Px,
Shift Py by 8 bytes (steps 1c to 1d).

Next, intermediate processing (S
2) will be explained. In the intermediate processing, as shown in FIG. 4, transfer is performed in units of 8 bytes from an 8-byte boundary. The process described below is sequentially repeated until the number n of bytes to be transferred becomes smaller than 8 (step 21). If f is on, load the 8 bytes pointed to by Px into register R1 (steps 22 to 23), double shift registers R1 and R2 to the left by s bytes, and store the obtained contents of R1 into the 8 bytes pointed to by Py. (Steps 24-25). Then n
Subtract the 8 bytes just transferred from , shift Px and Py by 8 bytes, and load 16 bytes from Px into consecutive registers R1 and R2 (steps 26 to 28).

The last tail processing by the last tail processing means 10 (
In S3), as shown in FIG. 5, fractional bytes less than the last 8 bytes are transferred. That is, intermediate processing (S2)
At the end, if n is zero, it is finished, and if it is other than zero, f is o.
If n, register R1 is shifted to the left by s bytes (steps 31 to 33). Next, fractional bytes are transferred (steps 34 to 38) in the same way as steps 18 to 1b of the head processing (S1). Here, mask 3 is 8-byte data in which the upper n bytes are 1 and the rest are all zeros. Mask 2 is a capture number of Mask 1, and mask data is created by a mask generation command.

[0019]

As explained above, according to the present invention, by separating the transfer of the fractional portion before and after the memory to be transferred and the transfer of 8 bytes each from the 8-byte boundary where memory access is fast, the transfer can be performed easily. This has the effect of reducing the number of execution steps and speeding up the processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing the overall flow of data transfer processing in the embodiment of the present invention.

FIG. 3 is a flowchart showing the flow of head processing in the embodiment of the present invention.

FIG. 4 is a flowchart showing the flow of intermediate processing according to the embodiment of the present invention.

FIG. 5 is a flowchart showing the flow of tail end processing in the embodiment of the present invention.

FIG. 6 is an explanatory diagram of the operation when transferring from memory area X to memory area Y in the embodiment of the present invention.

[Explanation of symbols]

1 Control device 2 Input device 3 Output device 4. Storage device 5 Arithmetic device 6 Processing equipment 7 Memory area 8 Head processing means 9. Intermediate processing means 10 Last processing means

Claims (1)

[Claims] 1. A 256-bit computer comprising a control device and a storage device, wherein the control device includes an arithmetic unit and a processing device, and the storage device stores data in units of 8-byte boundaries.
In a computer device including a large number of memory areas having an arbitrary length of bytes or more, the processing device includes a first processing means for transferring fractional byte data up to a first 8-byte boundary when transferring data to one memory area; , an intermediate processing means for transferring data in 8-byte units at every 8-byte boundary, a tail processing means for transferring data of fractional bytes less than the last 8 bytes, and means for starting each of the means in the above-mentioned order. A computer device comprising: