JPH04289475A - Apparatus for inspecting semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make a complicated test of a semiconductor integrated circuit in an extremely simple manner in low cost. CONSTITUTION:A voltage detection circuit 2 detecting the voltage level of the pulse applied to the input terminal 1 of a semiconductor integrated circuit and a pulse width detection circuit 10 detecting the pulse width of a voltage pulse are provided and the output of the pulse width detection circuit 10 is connected to the decoding input of a decoder 7. When an applied voltage level is a proper voltage level, the output of the decoder 7 is selected corresponding to the pulse width thereof and a proper test circuit 8 is selected.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a testing device for semiconductor integrated circuits.

0002

[Prior Art] In extremely high-performance semiconductor integrated circuits such as large-scale semiconductor integrated circuits such as system-on-chip, block-by-block inspection, bus protocol inspection between blocks, and inspection of rare cases during actual use are performed. Complex tests are required, such as checking the arbitration function in the event of a signal collision, and checking the function to avoid a huge number of abnormalities, and testing that simply inputs a test pattern to the input terminal and monitors the signal pattern output from the output terminal is insufficient. Enough and so many test modes must be prepared. Therefore, testing of semiconductor integrated circuits first requires a function to set the semiconductor integrated circuit in multiple test modes. Conventionally, testing circuits for semiconductor integrated circuits apply voltage pulses to the input terminals of the integrated circuit. There was a method in which after setting a test mode, address signals for selecting and setting each test mode were input to a plurality of external terminals.

The contents will be explained below with reference to FIG. As shown in the figure, by applying a voltage level exceeding the upper limit of the voltage range during normal operation, that is, a pulse signal of approximately 8V, to input terminal 1, which applies a signal within the voltage range of 0V to 5V during normal operation. , it was transitioning from normal operating mode to test mode.

[0004] Hereinafter, the pulse signal of approximately 8V as described above will be defined as a voltage pulse. A voltage pulse for setting the test mode applied to the input terminal 1 is detected by the voltage detection circuit 2 and sets the first flip-flop 3. The output signal of the first flip-flop 3 is used as a test signal 4 to control a circuit used in the test mode. Since the test mode consists of multiple modes, in order to set each test mode as necessary, after transitioning from the normal operation mode to the test mode using the above procedure, set the second flip-flop 5 corresponding to each test mode. need to be set. Reference numeral 6 denotes a group of terminals of the semiconductor integrated circuit, which serve as address signal terminals for selecting each test mode in the test mode by the multiplexer 11 which is enabled and operated by the test signal 4. In other words, the function of the terminal is switched from the normal operation function to the test mode function. The address signal input to the terminal group 6 is decoded by the decoder 7, and the output of the decoder 7 selects and sets one flip-flop from the second flip-flop 5. Then, the output of the set second flip-flop 5 activates the test circuit 8 to set the test mode, and the test circuit 8 adds a test function to the normal operation circuit 9 according to the selected test mode. or provide a test environment by supplying test signals.

[0005]

[Problems to be Solved by the Invention] However, in the conventional configuration described above, flip-flops are selected by address signals input from the terminal group as described above to set multiple test modes. The normal operating functions of individual terminals are lost. Therefore, inspection in each test mode could only be performed with multiple terminal functions removed.

Particularly, in cases where the aforementioned large-scale semiconductor integrated circuit has a huge number of functions, the signals assigned to each terminal are intricately intertwined, and many test modes are required, resulting in incomplete inspection. That's all I could do.

Furthermore, when a semiconductor integrated circuit mounted on a board is in actual use, a desired test mode is entered at an appropriate timing, the test circuit is made to function, and the functions of each terminal of the semiconductor integrated circuit are maintained in the actual use state. A test that is
This was not possible in the state where multiple terminal functions were lost during the test mode as described above.

[0008] The present invention solves the above-mentioned problems, and allows multiple test modes to be set very easily even during actual use, such as after mounting on a board, without losing much of the terminal function, making complex inspections flexible. The purpose of the present invention is to provide a test device for semiconductor integrated circuits that can be implemented.

[0009]

Means for Solving the Problems In order to achieve this object, a semiconductor integrated circuit testing device of the present invention includes a voltage detection circuit that detects a voltage pulse input applied to an input terminal of a semiconductor integrated circuit, and a voltage detection circuit that detects a voltage pulse input applied to an input terminal of a semiconductor integrated circuit. a first flip-flop that is set by the detection output signal of the circuit; a plurality of pulse width detection circuits that detect the pulse width of the detection output signal of the voltage detection circuit; and a plurality of pulse width detection circuits that are enabled by the output of the first flip-flop; A test mode setting circuit including a decoder that decodes the output of the pulse width detection circuit, a second flip-flop set by the output of the decoder, and a test function for the normal operation circuit according to the test mode set by the test mode setting circuit. It is equipped with a test circuit that adds

0010

[Operation] With this configuration, when the voltage level of the voltage pulse applied to the input terminal of the semiconductor integrated circuit exceeds the threshold level of the voltage detection circuit, the voltage detection circuit detects the level and sets the first flip-flop. At the same time, the pulse width of the output signal of the voltage detection circuit, that is, the voltage pulse width, is detected by the pulse width detection circuit corresponding to the pulse width, and the output is decoded. After that, the second flip-flop is set to activate the test circuit corresponding to the voltage pulse width. The activated test circuit can add a test mode-specific test function corresponding to the voltage pulse width to the normal operation circuit, or can provide a unique test environment.

[0011]

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, reference numeral 1 denotes an input terminal of the semiconductor integrated circuit, which is connected to a normal operation circuit 9 used during normal operation within the semiconductor integrated circuit, and is also connected to a voltage detection circuit 2. The detection output signal of the voltage detection circuit 2 serves as a set input to the first flip-flop 3 and is also input to the test mode setting circuit 15. The test mode setting circuit 15 includes pulse width detection circuits 10a to 10x and a decoder 7.
and a second flip-flop 5.

The detection output signal of the voltage detection circuit 2 is input to pulse width detection circuits 10a to 10x. The pulse width detection circuits 10a to 10x are connected to the delay elements 12a to 12x and the AN
It is composed of D gates 13a to 13x, and the number of gates is arranged according to the type of pulse width to be detected. The delay times of the delay elements 12a to 12x of the pulse width detection circuits 10a to 10x are set to different values depending on the pulse width to be detected. The output of the first flip-flop 3 is input to the decoder 7 as an enable signal, and the output signals 17a to 17 of the pulse width detection circuits 10a to 10x
x is input to the decoder 7 as a decode input. The outputs 16 of the decoders 7 are each connected to a set input of a second flip-flop 5. However, in this circuit, one of the outputs 16 of the decoder 7 is connected to the reset inputs of the first flip-flop 3 and the second flip-flop 5 as the reset signal 14. The output of the second flip-flop 5 is input as an enable signal to the test circuit 8, which activates the test circuit 8 and activates the normal operation circuit 9.
Add test function to .

A signal 2a is sent from the external terminal 1 to the voltage detection circuit 2.
In other words, when a voltage pulse is input, the voltage detection circuit 2
It detects the voltage level, converts the voltage level, and outputs the signal 2b. FIG. 2A is a timing chart showing an example of the relationship between the signal 2a and the signal 2b, that is, an example of the input and output of the voltage detection circuit 2, respectively. The signal 2b is input to the pulse width detection circuits 10a to 10x, but the delay element 1
The outputs of the pulse width detection circuits 10a to 10x become high only when the delay times 2a to 12x are smaller than the pulse width of the signal 2b. For example, the delay times of the delay elements 12a to 12x are Da to Dx, the pulse width of the signal 2b is W, and the output signals of the pulse width detection circuits 10a to 10x are 1, respectively.
7a to 17x, W, 1 when Da<W<Db
The relationship between 7a and 17b is as shown in the timing chart of FIG. 2(b). W when Da<Db<W
, 17a, and 17b are as shown in the timing chart of FIG. 2(c). Then, the outputs 17a to 17x of the pulse width detection circuits 10a to 10x are decoded by the decoder 7, one of the second flip-flops 5 is set, and the corresponding test circuit 8 is started to operate normally. A test function is added to circuit 9.

As described above, according to the semiconductor integrated circuit testing apparatus of the embodiment of the present invention, a large number of test modes can be implemented very easily by providing one test terminal on the semiconductor integrated circuit. Further, only the voltage level and pulse width of the voltage pulse determine the setting items, and the number of pulses can be ignored. In other words, the test pulse does not need to be a one-shot pulse, so the test pulse can be generated very easily and at low cost.

[0016]

As is clear from the above embodiments, according to the present invention, the pulse width can be changed by simply changing the voltage holding time of the applied pulse, that is, the pulse width, by utilizing changes in the voltage level and pulse width of the applied pulse. Since it is possible to select and set the appropriate test mode from multiple test modes depending on the situation, it is possible to perform inspections in multiple modes very easily without losing the terminal function under actual use conditions. . Therefore, it is possible to reliably and at low cost test large-scale integrated circuits that have a huge number of functions, the signals assigned to each terminal are intricately intertwined, and cannot be tested if even one terminal loses its function. Furthermore, it is possible to provide a semiconductor integrated circuit testing device that can perform complex testing such as entering an appropriate test mode at an appropriate timing in actual use and making additional test circuits function.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor integrated circuit testing device according to an embodiment of the present invention.

[Fig. 2] Timing chart for explaining the operation of the voltage detection circuit and pulse width detection circuit in the same embodiment.

[Figure 3
]Block diagram of conventional semiconductor integrated circuit testing equipment

[Explanation of symbols]

2 Voltage detection circuit 3 First flip-flop 5 Second flip-flop 7 Decoder 8 Test circuit 9 Normal operation circuit 10a~10x Pulse width detection circuit 15 Test mode setting circuit

Claims (1)

[Claims] 1. A voltage detection circuit that detects a voltage pulse input applied to an input terminal of a semiconductor integrated circuit, a first flip-flop set by a detection output signal of the voltage detection circuit, and a detection circuit of the voltage detection circuit. a plurality of pulse width detection circuits for outputting the pulse width of an output signal; a decoder enabled by the output of the first flip-flop to decode the output of the pulse width detection circuit; a second flip-flop set by the output of the decoder; A semiconductor integrated circuit testing device comprising: a test mode setting circuit including a flip-flop; and a test circuit that adds a test function to a normal operation circuit according to the test mode set by the test mode setting circuit.