JPH04287930A - Thin film transistor and manufacture thereof, and cmos semiconductor device - Google Patents

Abstract

PURPOSE:To acquire a thin film transistor which has less parasitic capacity and enables fast operation by constituting source region and a drain region of a semiconductor thin film having different film thicknesses and by making impurity concentration thereof different each other. CONSTITUTION:Pads 502, 503 are formed on an insulating substrate 501. A pattern is provided in contact with an upper side of an end part of the pads 502, 503. An entire thereof is coated with a gate insulating film 504 and a gate electrode 505 is formed thereon. Here, impurities are added to a silicon thin film. Regions 506, 507 whereto impurities are added form a source region and a drain region. A region whereto impurities are not added becomes a channel part 508. Furthermore, an entire thereof is coated with a layer insulating film 509. Here, impurity concentration of the pads 502, 503 is set high and impurity concentration of other source region and drain region 506, 507 is set low. A film thickness of the pad parts 502, 503 is made thicker than that of other source region 506, and drain region 507.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor particularly applied to active matrix liquid crystal displays, image sensors, three-dimensional integrated circuits, etc., a method for manufacturing the same, and a CMOS semiconductor device using the thin film transistor.

0002

2. Description of the Related Art An example of the structure of a conventional thin film transistor will be described with reference to FIG. This figure is a structural cross-sectional view in the channel direction. Insulating substrate 1 made of glass, quartz, sapphire, etc.
01, there are a source region 102 and a drain region 103 made of silicon thin films such as polycrystalline silicon, amorphous silicon, etc. doped with impurities to serve as donors or acceptors.
is formed. A channel region 104 made of a silicon thin film such as polycrystalline silicon or amorphous silicon is provided in contact with the upper side of the end of the source region 102 and the upper side of the end of the drain region 103 so as to connect the two. . A gate insulating film 105 made of an insulating film such as a silicon oxide film covers the entire structure, and a gate electrode 106 made of a metal, transparent conductive film, etc. is formed on both the source region 102 and the drain region 103. , is formed so that at least a portion thereof overlaps. Further, an interlayer insulating film 107 made of an insulating film such as a silicon oxide film is formed to cover the entirety. Further, a source electrode 108 made of metal, a transparent conductive film, etc.
2, similarly, the drain electrode 109 is connected to the drain region 103.
are provided in contact with each other through contact holes 110.

0003

However, the above-mentioned prior art has the following problems to be solved. That is, as described above, the gate electrode, the source region, and the drain region partially overlap each other with the gate insulating film interposed therebetween. Therefore, when a circuit is constructed using this transistor, the load capacitance is large and the speed of circuit operation cannot be increased. Therefore, a self-aligned transistor in which the source/drain region can be formed in self-alignment with the gate electrode is effective.

An example of a method for manufacturing this self-aligned thin film transistor will be explained with reference to FIG. This figure is a structural cross-sectional view in the channel direction. A silicon thin film 202 is formed on an insulating substrate 201, the whole is covered with a gate insulating film 203, and a gate electrode 204 is formed on this (see FIG. 2(a)). Next, using the gate electrode 204 as a mask, an impurity serving as a donor or an acceptor is added to the silicon thin film 202 to form a source region 205 and a drain region 206 in self-alignment with the gate electrode 204. At this time, the region covered by the gate electrode 204 and not doped with impurities becomes a channel region 207 (FIG. 2(b)
)reference). Next, an interlayer insulating film 208 made of a silicon oxide film or the like, a contact hole 209, a source electrode 210 made of metal, a transparent conductive film, etc., and a drain electrode 2
11 are sequentially formed (see FIG. 2(c)).

By the way, the characteristics of a thin film transistor largely depend on the thickness of the silicon film in the channel region, and the thinner the film, the larger the on-current, which is desirable. FIG. 3 shows the relationship between on-current and silicon film thickness in the channel region. However, in such self-aligned thin film transistors, the silicon film thickness in the channel region is equal to the silicon film thickness in the source/drain regions, and by making the film thinner, the source electrode and the source region, as well as the drain electrode and the drain region connection becomes difficult.

To address this problem, padded self-aligned thin film transistors have been devised. An example of a method for manufacturing this padded self-aligned thin film transistor will be described with reference to FIG. This figure is a cross-sectional view of the structure in the channel direction, and patterns (pads) 402 and 403 made of a silicon thin film are formed on an insulating substrate 401. A pattern 404 made of a silicon thin film is provided in contact with the upper side of these pads 402 and 403 so as to connect them. At this time, the thin film of the pattern 404 is formed to be thinner than the film thickness of the pads 402 and 403. Next, a gate insulating film 405 covers the entire structure, and a gate electrode 406 made of metal, a transparent conductive film, etc. is formed thereon (see FIG. 4(a)).

Next, using the gate electrode 406 as a mask, an impurity to serve as a donor or acceptor is applied to the silicon thin film 40.
2, 403, and 404 to form a source region 407 and a drain region 408 in self-alignment with the gate electrode 406. At this time, the region covered by the gate electrode 406 and not doped with impurities becomes a channel region 409 (see FIG. 4(b)). After this, an interlayer insulating film 410, a contact hole 411, a source electrode 412, and a drain electrode 413 are sequentially formed (see FIG. 4(c)).

However, ion implantation is generally used as a method of adding impurities to the silicon thin film 404 to form part of the source region 407 and drain region 408, but this destroys the crystallinity of the silicon thin film. It will be done. Although the crystallinity of the thicker pads 402 and 403 can be recovered by subsequent thermal annealing, the crystallinity of the thinner silicon thin film pattern 404 cannot be recovered and becomes a large resistance component. This has caused a new problem: a decrease in on-state current. As a countermeasure against this problem, it is effective to lower the dose during ion implantation, but in this case, it becomes difficult to connect the source electrode and the source region, as well as the connection between the drain electrode and the drain region. This is particularly a serious problem in Nch transistors, which generally require implantation of heavy ions, which tends to damage crystallinity.

The present invention is intended to solve the above-mentioned problems, and its purpose is to reduce the on-current and to make it difficult to connect the source electrode and the source region, as well as the drain electrode and the drain region. The purpose of the present invention is to form a self-aligned thin film transistor without any process, and as a result, provide a thin film transistor with low parasitic capacitance and capable of high-speed operation.

0010

[Operation] Connections between the source electrode and the source region, and between the drain electrode and the drain region, are made at pads with a thick film thickness and high impurity concentration, so that reliability is not impaired, and other source and drain regions are connected. Reduce the film thickness,
Moreover, by lowering the impurity concentration, the on-current does not decrease.

[0011]

[Examples] The present invention will be explained in detail below based on Examples.

(Example 1) FIG. 5 is a cross-sectional view of the structure in the channel direction. A silicon thin film such as polycrystalline silicon doped with an impurity to serve as a donor or acceptor is formed on an insulating substrate 501 made of glass, quartz, sapphire, etc. Pads 502 and 503 are formed. This pad 50
A pattern made of a thin film of silicon such as polycrystalline silicon is provided in contact with the upper side of the end portions 2 and 503 so as to connect the two. All of these are covered with a gate insulating film 504 made of an insulating film such as a silicon oxide film, and a gate electrode 505 made of a metal, a transparent conductive film, a polycrystalline silicon film doped with impurities, etc. is formed on this. .

Here, a gate electrode 50 is formed on the silicon thin film.
5 and regions 506 and 507 doped with an impurity that becomes a donor or acceptor in a self-aligned manner.
form source and drain regions together with pads 502 and 503. Further, a region to which no impurity is added becomes a channel portion 508. Furthermore, an interlayer insulating film 509 made of an insulating film such as a silicon oxide film covers the entire structure. Also, a source electrode 51 made of metal, transparent conductive film, etc.
0 is in contact with the source region, and similarly, a drain electrode 511 is in contact with the drain region through a contact hole 512, mainly with pads 502 and 503, respectively. At this time, pad 50
2, the impurity concentration of 503 is high, and the other source regions,
The impurity concentration of the drain regions 506 and 507 is set low. In addition, the film thickness of the pad portions 502 and 50 is also
3 is thicker than the other source region 506 and drain region 507.

The thin film transistor of Example 1 can be realized, for example, by the following steps. Figure 6 shows the Nch shown in Figure 5.
FIG. 3 is a process cross-sectional view showing the process for realizing the thin film transistor of FIG. For example, 1×1 phosphorus is placed on the insulating substrate 601.
A thin film of silicon such as polycrystalline silicon doped with about 0.020 cm -3 is deposited to a thickness of about 1500 angstroms. This silicon thin film is selectively etched to form a pad 602.
and 603 are formed. Next, a pattern 604 made of a silicon thin film of polycrystalline silicon or the like with a thickness of about 250 angstroms is placed in contact with the upper side of the two and connects the two.
will be established. Next, the entire structure is covered with a gate insulating film 605 made of an insulating film such as a silicon oxide film, and a gate electrode 606 made of a metal, a transparent conductive film, a polycrystalline silicon film doped with impurities, etc. is formed thereon ( (See Figure 6(a))
.

[0015] Next, 2×10 phosphorus was ion-implanted.
A source region and a drain region are formed in self-alignment with the gate electrode 606 by doping about 14 cm −3 . At this time, the impurity concentration of the source region and the drain region is, for example, 1×1020 cm in the thick pad portions 602 and 603.
-3 or so, 1×101 in thin film thickness parts 607 and 608
It is about 9cm-3. Furthermore, at this time, the region covered by the gate electrode 606 and not doped with impurities becomes a channel region 609 (see FIG. 6(b)).

After that, according to the usual process, a layer insulating film 610 made of a silicon oxide film and a contact hole 611 are formed.
, a source electrode 612 made of metal, a transparent conductive film, etc., and a drain electrode 613 are connected to the source region and the drain region, respectively, to complete an Nch thin film transistor (see FIG. 6).
c).

As described above, in the process for realizing the above-mentioned thin film transistor, for example, the impurity added to the pad is
Anything other than phosphorus may be used as long as it serves as a donor for arsenic or the like. Similarly, the impurity added in the ion implantation process for forming the source region and drain region in self-alignment with the gate electrode may be other than phosphorus as long as it serves as a donor for arsenic or the like. In addition, here, the thickness of the pad part was 1500 angstroms, and the thickness of the other source and drain regions was 250 angstroms.
As long as the pad portion is thinner than the other source and drain regions, the spirit of the present invention will not be missed.

(Embodiment 2) FIG. 7 is an example of a process cross-sectional view showing a process for realizing a Pch thin film transistor according to the present invention. On an insulating substrate 701, a polycrystalline silicon thin film doped with, for example, about 1×10 20 cm −3 of boron is deposited to a thickness of about 1000 angstroms by, for example, ion implantation. This silicon thin film is selectively etched to form pads 702 and 703. Next, a pattern 704 made of a silicon thin film such as polycrystalline silicon having a thickness of about 200 angstroms is provided so as to be in contact with the upper sides of both and to connect them. Next, the entire structure is covered with a gate insulating film 705, and a gate electrode 705 is placed on top of this.
(see FIG. 7(a)).

Next, boron was ion-implanted to form a 2×1
The source region and the drain region are formed in self-alignment with the gate electrode 706 by doping about 0.14 cm -2 . At this time, the impurity concentration of the source region and the drain region is, for example, 1×1020c in the thick pad portions 702 and 703.
m-3, 1×10 at thin film thickness parts 707 and 708
It is about 19cm-3. Further, at this time, the region covered by the gate electrode 706 and not doped with impurities becomes a channel region 709 (see FIG. 7(b)). After that, according to the usual process, an interlayer insulating film 710 made of a silicon oxide film, a contact hole 711, a source electrode 712 made of metal, a transparent conductive film, etc., and a drain electrode 713 are connected to the source region and the drain region, respectively, to form a Pch. Thin film transistor is completed. (See Figure 7(c)).

[0020] For example, the impurity added to the pad is
Any material other than boron may be used as long as it serves as an acceptor. Similarly, the impurities added in the ion implantation process for forming the source and drain regions in self-alignment with the gate electrode may be other than boron as long as they serve as acceptors. Also, here, the film thickness of the pad part is set to 1
000 angstroms, and the thickness of the other drain region is 2
00 angstroms, but the spirit of the present invention does not depart from the spirit of the invention as long as the thickness of the pad portion is thicker than that of the other source and drain regions.

(Embodiment 3) FIG. 8 is an example of a process sectional view showing a process for realizing a CMOS device using Nch and Pch thin film transistors according to the present invention. A silicon thin film of polycrystalline silicon or the like is deposited on an insulating substrate 801 to a thickness of about 1500 angstroms, for example, and selectively etched to form a pad 802 of an Nch transistor section.
and 803, and a pad 804 of the Pch transistor section
and 805 are formed. Next, phosphorus was applied to the pads 802 and 803 of the Nch transistor part at a thickness of 1×1015 cm.
Inject about 2 ions. Similarly, pads 804 and 805 of the Pch transistor part are also covered with boron at 1×1015 cm.
-2 ion implantation. Next, in contact with the upper side of the pads 802 and 803 of the Nch transistor section and pads 804 and 805 of the Pch transistor section,
Patterns 806 and 807 made of a silicon thin film such as polycrystalline silicon having a thickness of about 250 angstroms are provided to connect the pads. Next, the entire structure is covered with a gate insulating film 808 such as a silicon oxide film, and gate electrodes 809 and 810 made of a metal, a transparent conductive film, and a polycrystalline silicon thin film doped with impurities are formed thereon (FIG. 8). a
)reference).

Next, approximately 2×10 14 cm −2 of phosphorus is added to the Nch transistor portion by ion implantation, and N
A source region and a drain region are formed in self-alignment with the gate electrode 809 of the ch transistor. Similarly, Pch
Boron ions of about 2 x 1014 cm-2 were implanted into the transistor part to form the gate electrode 81 of the Pch transistor.
A source region and a drain region are formed in self-alignment with 0. At this time, the impurity concentration of the source region and the drain region is set at the thick pad portions 802, 803, 804, 80 in both the Nch transistor portion and the Pch transistor portion.
5, for example, about 1 x 1020 cm-3, and the thin film parts 811, 812, 813, 814, for example, 1 x 10
It is about 19cm-3. Also, at this time, the regions covered by the gate electrodes 809 and 810 and not doped with impurities become channel regions 815 and 816, respectively (
(See FIG. 8(c)).

After that, according to the usual process, an interlayer insulating film 817 made of a silicon oxide film and a contact hole 818 are formed.
, a source electrode 819 made of metal, a transparent conductive film, etc., and a drain electrode 820 are connected to the source region and the drain region, respectively, to complete a CMOS using an Nch thin film transistor and a Pch thin film transistor according to the present invention (FIG. 8(c)). reference).

(Embodiment 4) FIG. 9 is an example of a process cross-sectional view showing a process for realizing CMOS using an Nch thin film transistor according to the present invention. A silicon thin film of polycrystalline silicon or the like is deposited to a thickness of about 1000 angstroms on an insulating substrate 901, and this is selectively etched to form an Nc
pads 902 and 903 of the h transistor section, and Pc
Pads 904 and 905 of the h transistor section are formed. Next, pads 902 and 9 of the Nch transistor section
In step 03, phosphorus is ion-implanted at a concentration of about 1×10 15 cm −2 . Pads 902 and 903 of Nch transistor section, Pch
For each of the pads 904 and 905 of the transistor section, a 200-m
Patterns 906 and 907 made of silicon thin films such as polycrystalline silicon having a thickness of about angstroms are provided. Next, all of these are covered with a gate insulating film 908 made of an insulating film such as a silicon oxide film, and on top of this, a gate electrode 9 made of a metal, a transparent conductive film, a polycrystalline silicon film doped with impurities, etc.
09 and 910 (see FIG. 9(a)).

Next, approximately 2×10 14 cm −2 of phosphorus is added to the Nch transistor portion by ion implantation, and N
A source region and a drain region are formed in self-alignment with the gate electrode 909 of the channel transistor section. Similarly, Pc
Boron ions of about 1×10 15 cm −2 are implanted into the H transistor portion, and a source region 911 and a drain region 912 are formed in one step in self-alignment with the gate electrode 910 of the Pch transistor portion. At this time, the impurity concentration of the source region and drain region of the Nch transistor is, for example, 1× in the thick pad portions 902 and 903.
Approximately 1020cm-3, thin film thickness parts 913, 914
For example, it is about 1×10 19 cm −3 . Further, at this time, regions covered by the gate electrodes 909 and 910 and not doped with impurities are a channel region 915 and a channel region 915, respectively.
916 (see FIG. 9(b)).

After that, according to the usual process, the interlayer insulating film 91 is formed.
7. Form a contact hole 918 and connect the source electrode 9
19. The drain electrode 920 is connected to the source region and the drain region, respectively, to complete a CMOS using the Nch thin film transistor according to the present invention (see FIG. 9(c)).

(Embodiment 5) FIGS. 10 and 11 are cross-sectional views showing another process for constructing a CMOS using the Nch thin film transistor according to the present invention. Insulating substrate 1
For example, an n-type silicon thin film is placed on 001.
A thickness of about 2000 angstroms is deposited and selectively etched to form pads 1002 and 1003 of the Nch transistor portion (see FIG. 10(a)). Next, N
A pattern 10 of a silicon thin film (intrinsic) of approximately 250 angstroms is in contact with the upper side of pads 1002 and 1003 of the channel transistor section and connects the pads.
04, and a similar pattern 1005 is also provided in the Pch transistor portion (see FIG. 10(b)). continue,
A gate insulating film 1006 made of silicon oxide or the like is formed to a thickness of about 1500 angstroms over the entire surface, and the gate electrode 1
007 and 1008 (see FIG. 10(c)).

[0028] Subsequently, Nch
Mask the transistor part and deposit 1 x 1015 cm of boron.
-2 ion implantation to make the source and drain regions of the silicon thin film pattern 1005 of the Pch transistor part P-type in a self-aligned manner (see FIG. 11(a))
. Next, the resist film 1009 is removed, the Pch transistor part is masked with another resist film 1010, and phosphorus is ion-implanted to a depth of about 1×10 14 cm -2 to form the source region and drain of the silicon thin film pattern 1004 of the Nch transistor part. The region is made into an N type in a self-aligned manner (see FIG. 11(b)). Then, the resist film 1010 is removed, an interlayer insulating film 1011 made of silicon oxide or the like is formed with a thickness of about 5000 angstroms, and the contact hole 1012 is
The structure is completed by forming source electrodes 1013 and 1014 and drain electrodes 1015 and 1016 (see FIG. 11(c)).

Several processes for realizing the thin film transistor according to the present invention have been described above, but even if the material or process changes in addition to those described here, the film thickness of the pad portion may be different from that of other source regions or As long as it is thicker than the drain region, and the impurity concentration in at least a portion of the pad portion is high, it does not depart from the spirit of the present invention. In all cases, the impurity is added to the pad portion before the formation of the gate electrode, but the purpose of the present invention can still be achieved even if the impurity is selectively added to the pad portion after the formation of the gate electrode using, for example, light exposure technology. Don't miss out.

[0030]

[Effects of the Invention] By using the present invention, it is possible to achieve self-conducting connections between a source electrode and a source region, and between a drain electrode and a drain region, without deteriorating the reliability or reducing the on-current. An aligned thin film transistor is obtained. This has made it possible to provide a thin film transistor with low parasitic capacitance, that is, capable of high-speed operation.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an example of the structure of a conventional thin film transistor.

FIG. 2 is a process cross-sectional view showing an example of a conventional method for manufacturing a self-aligned thin film transistor.

FIG. 3 is a graph showing the relationship between the on-current of a conventional thin film transistor and the thickness of a silicon thin film forming a channel portion.

FIG. 4 is a process cross-sectional view showing an example of a conventional method for manufacturing a self-aligned thin film transistor with a pad.

FIG. 5 is a cross-sectional view showing an example of the structure of a padded self-aligned thin film transistor according to the present invention.

FIG. 6: Padded self-aligned type N according to the present invention
FIG. 3 is a process cross-sectional view showing an example of a method for manufacturing a channel thin film transistor.

FIG. 7: Padded self-aligned type P according to the present invention
FIG. 6 is a process cross-sectional view showing another example of the method for manufacturing a channel thin film transistor.

FIG. 8 is a process cross-sectional view showing an embodiment of a manufacturing method when a CMOS is formed using a padded self-aligned thin film transistor according to the present invention.

FIG. 9: Padded self-aligned type N according to the present invention
FIG. 3 is a process cross-sectional view showing an example of a manufacturing method when a CMOS is formed using a channel thin film transistor.

FIG. 10: Padded self-aligned N according to the present invention.
ch thin film transistor and normal self-aligned Pch
FIG. 3 is a step-by-step cross-sectional view showing an example of a manufacturing method (first half) when a CMOS is formed using thin film transistors.

FIG. 11: Padded self-aligned N according to the present invention.
ch thin film transistor and normal self-aligned Pch
FIG. 3 is a step-by-step cross-sectional view showing an example of a manufacturing method (second half) when a CMOS is formed using thin film transistors.

[Explanation of symbols]

101, 201, 401, 501, 601, 701, 8
01, 901, 1001,

...Substrate 40
2, 403, 502, 503, 602, 603, 702
, 703, 802, 803, 804, 805, 902,
903, 904, 905, 1002, 10 03,


...pads 202, 404, 604, 704, 806, 807, 9
06, 907, 1004, 1005,

...Silicon thin film 102, 205, 407
,911,
...source regions 103, 206, 408, 912,
…drain area

Claims (6)

[Claims] 1. A source region and a drain region made of a semiconductor thin film doped with an impurity serving as a donor or an acceptor, and a semiconductor formed between the source region and the drain region in contact with the source region and the drain region. a channel region made of a thin film; a gate insulating film formed to cover at least the channel region;
In a thin film transistor comprising a gate electrode provided on the gate insulating film, the source region and the drain region are composed of semiconductor thin films having at least two different thicknesses, and the impurity concentrations thereof are also different. A thin film transistor characterized by: 2. At least a portion of the thicker semiconductor thin film of at least two different thicknesses constituting the source region and the drain region has a high impurity concentration. The thin film transistor according to claim 1. 3. Among the semiconductor thin films having at least two different thicknesses constituting the source region and the drain region, impurities are added to the thicker semiconductor thin film before forming the gate electrode. 3. The thin film transistor according to claim 2, wherein an impurity is added to the thin semiconductor film after forming the gate electrode. 4. A step of forming a thick semiconductor thin film in a source region and a drain region by adding an impurity to serve as a donor or an acceptor, and forming another semiconductor thin film in at least a channel region so as to be in contact with the source region and the drain region. A method for manufacturing a thin film transistor comprising the steps of forming a thin film thinly, sequentially forming a gate insulating film and a gate electrode, and adding an impurity to the other semiconductor thin film using the gate electrode as a mask. 5. A CMOS semiconductor device characterized in that an Nch thin film transistor having the structure according to claim 1 and a Pch thin film transistor having the structure according to claim 1 are formed on the same substrate to constitute a CMOS circuit. . 6. A CMOS semiconductor device in which an Nch thin film transistor and a Pch thin film transistor are formed on the same substrate, wherein at least the Nch thin film transistor has the structure according to claim 1.