JPH04286423A - Parallel-serial conversion circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution of a parallel-serial conversion circuit by generating internally an S/L (SHIFT/LOAD) signal used to match the switching timing for a parallel input operation and a data shift operation and using also an external S/L signal through the selection. CONSTITUTION:Three kinds of signals, an external S/L signal, a starting signal to generate an internal S/L signal and a selection switching signal for a selection switching circuit 50 to decide which of the external S/L signal and the internal S/L signal is to be selected are given to the parallel-serial conversion circuit through one input signal line. Thus, the number of input terminals is decreased and an IC in which the parallel-serial conversion circuit is incorporated is miniaturized.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel-to-serial conversion circuit for converting N-bit parallel data into serial data.

0002

[Prior Art] In the conventional parallel-to-serial conversion circuit,
Parallel input of N pieces of data and serial output by shifting the data N times were performed alternately. Switching between parallel input and serial output is performed using S/L (SHIF).
This was done using the T/LOAD) signal.

Although this S/L signal may be applied externally, it can be generated internally by adding a simple frequency dividing circuit. Furthermore, it would be very convenient if an external S/L signal applied from the outside and an internal S/L signal generated within the circuit could be freely selected in the same circuit by applying a switching signal from the outside.

FIG. 4 shows a conventional example of a parallel-to-serial conversion circuit capable of switching S/L signals in this manner. The circuit in FIG. 4 includes a shift register 110 that converts parallel data to serial data, a frequency divider circuit 120 that generates an internal S/L signal, and selects either the internal S/L signal or the external S/L signal. The selection circuit 130 is comprised of a selection circuit 130. In this circuit, parallel data given to the shift register 110, a clock signal that matches the operation timing of the shift register 110, and a frequency dividing circuit 120 are provided.
A start signal that matches the startup timing of the , an external S/L signal that switches between parallel input and serial output,
It inputs a selection switching signal given to the selection circuit 130 and outputs serial data.

As an IC using such a parallel-to-serial conversion circuit, for example, SONY's "CXB1113"
B" etc.

[0006]

[Problems to be Solved by the Invention] By the way, in this parallel-serial conversion circuit, when only the internal S/L signal is used, the external S/L signal is not necessary among the input signals mentioned above, and the selection The switching signal is also fixed "internally". Conversely, when only the external S/L signal is used, the start signal used to generate the internal S/L signal becomes unnecessary. Table 1 shows the relationship between the S/L signal selection and the input signal.

[0007]

[Table 1]

As described above, this parallel-to-serial conversion circuit has the advantage of being able to use both the external S/L signal and the internal S/L signal without changing the circuit. An extra input signal terminal is always required compared to circuits using S/L signals. The existence of this extra input signal terminal has hindered the miniaturization of ICs incorporating this parallel-to-serial conversion circuit.

[0009] It is an object of the present invention to solve such problems.

0010

[Means for Solving the Problems] In order to solve the above problems, the parallel-to-serial conversion circuit of the present invention is provided with a clock signal input to a parallel input serial output shift register,
A frequency divider circuit that outputs a square wave signal with a period N times that of this clock signal and a duty ratio of 1/N, a control signal line that is connected to the reset terminal of the frequency divider circuit and provides a control signal, and If the signal is a square wave signal with a period N times that of the clock signal and a duty ratio of 1/N, this signal is applied as a switching signal to the parallel input serial output shift register, and the signal on the control signal line is frequency-divided. A selection circuit is provided for applying the output signal of the frequency dividing circuit as a switching signal to the parallel input serial output shift register when the signal is a monostable signal that maintains the set state of the circuit.

[0011]

[Operation] According to the parallel-to-serial conversion circuit of the present invention,
A signal with a period N times that of the clock signal is sent to the control signal line as a control signal, and the logic value is "0" or 1 during (N-1) clocks.
When a square wave signal holding the logic value "1" during the clock is applied, the frequency dividing circuit is reset every N times the period of the clock signal and outputs a monostable signal with the logic value "0". Therefore, the control signal is directly applied as a switching signal to the parallel input serial output shift register.

Furthermore, when a monostable signal with a logical value of "0" is applied to the control signal line as a control signal, the applied clock signal in the frequency dividing circuit has a logical value of "0" for (N-1) clocks.
0'' and is converted into a square wave signal that holds the logic value ``1'' for one clock. This square wave signal is applied as a switching signal to a parallel input serial output shift register.

Further, the frequency dividing circuit is reset by switching the control signal applied to the control signal line from the logical value "1" to "0", and the operation of the frequency dividing circuit is started at the timing of this switching.

[0014]

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 to 4. FIG. 1 is a circuit configuration diagram of this embodiment. The circuit of this embodiment includes a parallel input serial output shift register 1 that converts parallel data into serial data,
1/4 frequency dividing circuit 40 that generates an internal S/L signal
, a selection circuit 50 that selects either the internal S/L signal or the external S/L signal as the S/L signal, and a delay circuit 60 that delays the selected S/L signal. There is. The parallel input serial output shift register 1 includes a shift register section 10 that temporarily stores parallel data.
and a switching circuit 20 that determines whether the shift register section 10 performs parallel input or serial output operation. The shift register section 10 also includes four flip-flops 11 to 14 connected in series, and an inverting circuit 15 connected to the inverted output terminal of the flip-flop 14. Furthermore, the switching circuit 20
includes NOR circuits 21-24 connected to the input terminals of flip-flops 11-14, respectively, and these NOR circuits 21-24 connected to the input terminals of flip-flops 11-14, respectively.
NOR connected to the output terminals of circuits 21 to 24, respectively
Circuits 25 to 32 and NOR circuits 26, 28, 30, 32
Inverting circuits 33 to 36 connected to are provided. Next, the frequency dividing circuit 40 includes flip-flops 41 and 42 whose control signal lines are connected to respective reset terminals.
Output terminal of flip-flop 41 and flip-flop 4
NOR with the inverted output terminal of 2 connected to the input terminal
A circuit 43, an N circuit in which the output terminal of the flip-flop 41 and the output terminal of the flip-flop 42 are connected to the input terminal.
An OR circuit 44 is also provided. In addition, the selection circuit 50
includes a NOR circuit 51 whose input terminal is connected to the output terminal of the NOR circuit 43 and a control signal line, an inverting circuit 52 connected to the output terminal of the NOR circuit 51, and a NOR circuit 44.
The output terminal and control signal line of NO are connected to the input terminal.
An R circuit 53 and an inverting circuit 54 connected to the output terminal of the NOR circuit 53 are provided.

Furthermore, the circuit of this embodiment is provided with parallel input terminals 70 to 73, a serial input terminal 74, a clock terminal 75, and a control terminal 76 as input system signal terminals. Parallel input terminals 70-73 are NO
It is connected to the input terminals of R circuits 32, 30, 28, and 26, respectively, and receives a parallel input signal. Further, the clock terminal 75 is connected to the clock terminals of the flip-flops 11 to 14 and the clock terminals of the flip-flops 41 and 42, and is supplied with a clock signal. Furthermore, control terminal 7
6 is the reset terminal of flip-flops 41 and 42 and NO
It is connected to the input terminals of R circuits 51 and 52, and is given a control signal. The output system signal terminals include a serial output terminal 80 and a monitor terminal 81 for observing the S/L signal.
, 82 are provided.

Next, the operation of this embodiment will be explained using the waveform diagrams of FIGS. 2 and 3. FIGS. 2A to 2J are waveform diagrams when a monostable signal with a logic value of "0" is given as a control signal. Here, a signal with a logic value of "0" refers to a low level signal, and a signal with a logic value of "1" indicates a high level signal.

To explain each waveform diagram, FIG. 2(a)
2 is a waveform diagram of a control signal applied to the control terminal 76. FIG. FIG. 2(b) is a waveform diagram of the clock signal applied to the clock terminal 75. Figure 2(c) shows the serial input terminal 74.
FIG. 3 is a waveform diagram of input data given to FIG. Figure 2(d)~
(g) is a waveform diagram of parallel input data applied to parallel input terminals 70 to 73, respectively. FIG. 2(h) is a waveform diagram of serial output data applied to the serial output terminal 80. FIG. 2(i) is a waveform diagram of the S/L signal applied to the monitor output terminal 81. FIG. 2(j) is the time axis.

The control signal in FIG. 2(a) has a logic value of "1" at t1.
” to the logical value “0”. At the timing of this inversion, the frequency dividing circuit 40 starts operating from a certain initial state. When the control signal becomes a logical value "0", the frequency divider circuit 40 divides the input clock signal (FIG. 2(b)) into a waveform with a four times period. Since the output of the flip-flop 41 and the inverted output of the flip-flop 42 are given to the NOR circuit 43, the duty ratio is 1/1, which holds the logic value "0" for three clocks and the logic value "1" for one clock. 4 internal S/L signals are output. This internal S/L signal and a control signal with a logic value of "0" are applied to a NOR circuit 51, and further passed through an inversion circuit 52 to generate an S/L signal. This S
/L signal is applied to the switching circuit 20 through the delay circuit 60 (FIG. 2(i)).

In the switching circuit 20, the S/L signal has a logic value of "0".
”, the shift register unit 10 is operated to shift. Then, when the S/L signal has a logical value of "1", parallel data is provided to the shift register section 10. The reason why the operation of the shift register unit 10 is switched in this manner is due to the characteristics of the circuit configuration of the switching circuit 20. To explain this circuit configuration, the output data of the flip-flop 11 and the S/L signal are given to the NOR circuit 27, and the NOR circuit 27 receives
The R circuit 28 is supplied with parallel input data and an inverted S/L signal. Therefore, the S/L signal has a logic value of “1”.
”, the output from the NAND circuit 27 is always the logical value “0” regardless of the output data of the flip-flop 11.
”. On the other hand, the NOR circuit 28 outputs inverted parallel input data. Since these data are given to the NOR circuit 22, the NOR circuit 22 outputs parallel input data. This parallel input data is applied to flip-flop 12. In addition, when the S/L signal has a logical value of "0", conversely,
Output data of flip-flop 11 is applied to flip-flop 12. In other words, a data shift is performed.

Next, to explain the operation of this embodiment, a specific data flow will be described. First, since the S/L signal between t6 and t8 shows the logical value "1", the parallel data of each parallel input terminal 70 to 73 at the time of t8 (logical value "1", "0", "1", "0") ) is flip-flop 11~
14 (Fig. 2(d) to (g)). And t
Since the S/L signal between 8 and t14 changes to the logical value "0", shift operations are performed in the flip-flops 11 to 14, and the input parallel data is sequentially output from the serial output terminal 80. That is, at time t8, data "0" input from the parallel input terminal 73 is output, and t
At time 10, the data "1" input from the parallel input terminal 72 is output. Further, at time t12, the data "0" input from the parallel input terminal 71 is output, and at time t14, the data "1" input from the parallel input terminal 70 is output (FIG. 2(h)).
. Also, at this time t14, the S/L signal has the logical value "
1", parallel input is also performed at the same time as serial output.

FIGS. 3A to 3J are waveform diagrams when an external S/L signal is applied as a control signal. This control signal is a square wave signal with a duty ratio of 1/4 that holds the logical value "0" for three clocks and holds the logical value "1" for one clock (FIG. 3(a)). Since this control signal is applied to the reset terminals of the flip-flops 41 and 42 of the frequency dividing circuit 40, the flip-flops 41 and 42 are reset when the control signal indicates the logical value "1". The NAND circuit 43 has an output “0” from the flip-flop 41 and an inverted output “1” from the flip-flop 42.
is given, a signal with a logical value of "0" is output from the output terminal. The control signal becomes logical value “0” at the next clock.
When the frequency changes to , the frequency dividing circuit 40 starts frequency dividing operation. That is, for the next three clocks, a signal with a logic value of "0" is output from the output terminal of the NAND circuit 43, and a signal with a logic value of "1" is output at the fourth clock. However, at the fourth clock, the control signal is inverted to the logical value "1", so the flip-flops 41 and 42 are reset. Therefore, the output from the NAND circuit 43 is a logical value.
It becomes a monostable signal of "0". Since this monostable signal and an external S/L signal which is a control signal are applied to the NAND circuit 51, an inverted external S/L signal is output from the output terminal. This signal is further inverted by an inverting circuit 52,
An external S/L signal is applied to the switching circuit 20 as an S/L signal (FIG. 3(i)).

A specific data flow in this embodiment using such an S/L signal will be explained below. First, t5~t
Since the S/L signal between 8 and 8 indicates the logical value "1", the parallel data (
Logic values "1", "1", "0", and "0") are applied to flip-flops 11 to 14 (FIGS. 3(d) to 3(g)). Then, since the S/L signal between t8 and t13 changes to the logical value "0", shift operations are performed in the flip-flops 11 to 14, and the input parallel data is sequentially output from the serial output terminal 80. That is, at time t8, the data "0" input from the parallel input terminal 73 is output, and at time t10, the data "0" input from the parallel input terminal 72 is output. Furthermore, at time t12, the data input from the parallel input terminal 71 is
1" is output, and at time t14, the data "1" input from the parallel input terminal 70 is output (see FIG. 3).
h)). Furthermore, at this time point t14, the S/L signal changes to a logical value of "1", so parallel input is performed at the same time as serial output.

In this embodiment, a signal with a logic value of "0" is defined as a low level signal, and a signal with a logic value of "1" is defined as a high level signal. The same implementation can be achieved by using a low level signal as a high level signal or a signal with a logical value of "1".

Furthermore, in this embodiment, a parallel-to-serial conversion circuit using a 4-bit shift register has been described, but the present invention is also applicable to circuits using 8-bit, 16-bit, 32-bit, etc. shift registers. It is possible.

[0025]

Effects of the Invention: With the parallel-to-serial conversion circuit of the present invention, it is possible to select between an external S/L signal and a start signal for generating an internal S/L signal, and between an external S/L signal and an internal S/L signal. Three types of input signals, including selection switching signals for determining whether to select or not, can be applied to the circuit from one input signal line. Therefore, the number of input terminals can be reduced,
It is possible to downsize an IC incorporating a parallel-to-serial conversion circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of this embodiment.

FIG. 2 is a waveform diagram showing the operation of this embodiment.

FIG. 3 is a waveform diagram showing the operation of this embodiment.

FIG. 4 is a circuit configuration diagram of a conventional example.

[Explanation of symbols]

1...Parallel input serial output shift register 10...Shift register section 20...Switching circuit 40...Frequency dividing circuit 41...Flip-flop 42...Flip-flop 43...NAND circuit 44...NAND circuit 50...Selection circuit 51...NAND circuit 52...Inversion circuit 53...NAND circuit 54...Inversion circuit 60...Delay circuit

Claims (2)

[Claims] 1. A parallel-serial device comprising a parallel-input serial-output shift register that performs either parallel input of N pieces of input data (N is a natural number) or serial output by data shifting determined by a switching signal. In the conversion circuit, a frequency dividing circuit inputs a clock signal to the parallel input serial output shift register and outputs a square wave signal having a period N times that of the clock signal and a duty ratio of 1/N; When a control signal line is connected to the reset terminal of the circuit and gives a control signal, and the signal on this control signal line is a square wave signal with a period N times that of the clock signal and a duty ratio of 1/N, A signal is applied to the parallel input serial output shift register as the switching signal, and when the signal on the control signal line is a monostable signal that maintains the set state of the frequency divider circuit, the output signal of the frequency divider circuit is applied to the switch register. 1. A parallel-to-serial conversion circuit comprising: a selection circuit that provides a signal to the parallel input serial output shift register. 2. The parallel control circuit according to claim 1, wherein the selection circuit includes a logic circuit that performs a NOR of the output signal of the frequency dividing circuit and the signal on the control signal line. Serial conversion circuit.