JPH04286022A - Barrel shifter - Google Patents

Abstract

PURPOSE:To output a processing result at a high speed by selecting and outputting one output from more than two outputs among the outputs of plural shifters. CONSTITUTION:A multiplexer 7 as a first output selection means selects and outputs one output from more than two outputs among the outputs of the plural shifters (1-1) to (1-5). The multiplexer 7 selects one of the plural shifters (1-1) to (1-5) and inputs input data. At the time of obtaining a necessary shifting amount, it is unnecessary to permit all the shifters (1-1) to (1-5) to pass through them. Only the shifters of a necessary minimum, which are necessary for obtaining the shifting amount to be obtained, are selected by using the selection of input or output so as to cause them to passing through. Thus, the processing result can be outputted at a high speed since the unnecessary shifter is not required to pass through them.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a barrel shifter, and more particularly to a barrel shifter comprised of a plurality of shifters each having a different amount of shift relative to input data.

[0002] With the recent advances in computers, the amount of shift bits handled has tended to increase, and being constrained by the output time of shift operations that require the longest path may cause a decline in computer performance. Regarding shift operations that can produce results quickly, it is desired that the results can be output quickly.

0003

2. Description of the Related Art FIGS. 8 and 9 show block diagrams of conventional barrel shifters. In FIG. 8, 11-1 to 11-n indicate shifters having mutually different shift amounts. shifter 11
-1 to 11-n are input terminal Tin and output terminal Tout
A subordinate connection is made between the The shifters 11-1 to 11-n are controlled by a control signal from the control circuit 6G to determine whether to shift the input data by the respective shift amounts or to output the data without shifting.

For example, in FIG. 9, when input data is to be shifted by 1 bit, the control circuit 6H causes the 1-bit shifter 11-1 to shift, and the other shifter 11-2
to 11-5 are controlled so that no shift is performed. Furthermore, when shifting by 3 bits, the 1-bit shifter 11-1 and the 2-bit shifter 11-2 are controlled to perform a shifting operation, and the other shifters 11-3 to 11-5 are controlled not to perform the shifting.

[0005]

[Problems to be Solved by the Invention] Conventional barrel shifters are connected in series between a plurality of input/output terminals with different shift amounts as shown in FIGS. For example, in a 32-bit barrel shifter (FIG. 9), in the case of a 24-bit shift, the fourth stage (8-bit shifter) Although only the fifth stage (16-bit shifter) needs to perform a shift operation, the remaining shifters, that is,
The 1st, 2nd, and 3rd stage shifters are also forced to pass through in the form of a 0 shift. Therefore, when the amount of bits to be shifted becomes large, that is, the number of stages of each shifter that makes up the barrel shifter increases. If the number of outputs is increased, even though the shift operation can easily obtain results, the same amount of time as the shift operation that takes the longest time is spent on the output, resulting in problems such as deterioration of the computer's performance. Ta.

The present invention has been made in view of the above points, and an object of the present invention is to provide a barrel shifter capable of high-speed operation.

[0007]

[Means for Solving the Problems] The present invention provides the following means to solve the above problems.

The first output selection means includes a plurality of shifters (1-
1 to 1-5), one output is selected and output from at least two or more outputs.

The first input selection means selects one of the plurality of shifters and inputs the input data.

[0010] The second input selection means is provided corresponding to the plurality of shifters, and selects any one of the input data and the output of the shifter at the other stage and inputs it to the corresponding shifter, and the second output selection means selects and outputs one output from the outputs of a plurality of shifters.

[0011]

[Operation] With the above configuration, it is no longer necessary to pass through all the shifters when trying to obtain the required shift amount, and the desired shift amount can be obtained using the input or output selection means. It is possible to select and pass only the minimum necessary shifters.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a block diagram of a first embodiment of the present invention. In the figure, 1 is a 16-bit shifter, and the input terminal Tin
The input data input to the input terminal is shifted by 16 bits and output. A control signal is input to the 16-bit shifter 1 from the control circuit 6A. The 16-bit shifter 1 shifts input data by 16 bits and outputs it, or outputs it without shifting it, depending on the control signal.

2 is an 8-bit shifter to which the output of the 16-bit shifter 1 is input. 8 bit shifter 2 is control circuit 6
A control signal is input from A, and depending on the control signal, the output of the 16-bit shifter 1 is shifted by 8 bits and output, or is output without being shifted.

3 is a 4-bit shifter, and 8-bit shifter 2
The output of is input. 4 bit shifter 3 is control circuit 6A
A control signal is input from the 8-bit shifter 2, and depending on the control signal, the output of the 8-bit shifter 2 is shifted by 4 bits and output, or is output without being shifted.

4 is a 2-bit shifter, and 4-bit shifter 3
The output of is input. The 2-bit shifter 4 is connected to the control circuit 6, and depending on the control signal, shifts the output of the 4-bit shifter 3 by 2 bits and outputs it, or outputs it without shifting.

5 is a 1-bit shifter, and 2-bit shifter 4
The output of is input. 1 bit shifter 5 is control circuit 6A
The output of the 2-bit shifter 4 is either shifted by 1 bit and outputted, or is output without being shifted, depending on the control signal. The output of 1-bit shifter 5 is sent to multiplexer 7
is input. Multiplexer 7 has a 1-bit shifter 5
In addition to the output of 8-bit shifter 2, the output of 8-bit shifter 2 is input. Further, the multiplexer 7 is connected to the control circuit 6A,
The data to be output to the output terminal Tout is transferred to the 1-bit shifter 5 or 8 according to the control signal supplied from the control circuit 6A.
Switch to the output of bit shifter 2.

Next, the operation of the circuit will be explained.

When the input data input to the input terminal Tin is shifted by 8 bits, 16 bits, or 24 bits, only the 16-bit shifter 1 and the 8-bit shifter 2 may be used. Therefore, the multiplexer 7 is controlled by the control signal from the control circuit 6, and the output data output from the output terminal Tout is output from the 8-bit shifter 2.

First, when it is desired to shift input data by 8 bits, the 16-bit shifter 1 is not operated by a control signal from the control circuit 6A, the input data is passed through as is, and only the 8-bit shifter 2 is operated. Therefore, the input data is shifted by 8 bits and supplied from the multiplexer 7 to the output terminal Tout, and is output.

Further, when it is desired to shift the input data by 16 bits, the 16-bit shifter 1 and the 8-bit shifter 2 are controlled by the control signal of the control circuit 6A, and only the 16-bit shifter 1 is operated. Therefore, the input data is shifted by 16 bits by the 16-bit shifter 1, output from the 8-bit shifter 2, and supplied via the multiplexer 7 to the output terminal Tout.

Further, when it is desired to shift input data by 24 bits, the 16-bit shifter 1 and the 8-bit shifter 2 are controlled by the control signal of the control circuit 6, and the 16-bit shifter 1 and the 8-bit shifter 2 are operated together. The input data is shifted by 16 bits by 16 bit shifter 1,
Further, the data is shifted by 8 bits by the 8-bit shifter 2, for a total of 24 bits. The 24-bit shifted data is input directly from the 8-bit shifter 2 to the multiplexer 7 and is supplied to the output terminal Tout.

When it is desired to obtain another shift amount, the multiplexer 7 is controlled by the control circuit 6, so that the output of the 1-bit shifter 5 is connected to the output terminal Tout, and the input data is sent to the 16-bit shifter 1 and the 8-bit shifter 2. , 4-bit shifter 3, 2-bit shifter 4, and 1-bit shifter 5 to obtain the required shift amount.

In this way, when the shift amount is 8 bits, 16 bits, or 24 bits, it is sufficient to pass through only 16-bit shifter 1 and 8-bit shifter 2, and it is sufficient to pass through two stages of shifters, and the delay is only two stages. Therefore, processing results can be output quickly. It is particularly suitable for alignment processing of load/store data.

[0024] Load/store data alignment processing means that the load/store data is assumed to be 8-bit data (
byte data) or 16-bit data (halfword data), in order to treat it as 32-bit data, you need to know in which part of the 32 bits the 8-bit or 16-bit data should be placed. decided,
This is the process of rearranging 8-bit or 16-bit data into that part.

When alignment processing of load/store data is performed using a 32-bit barrel shifter as shown in FIG. Remaining 1-bit, 2-bit, and 4-bit shifters 1-3, 1-4
, 1-5 are no longer needed.

For this reason, first, the order of construction of each shifter of the barrel shifter is changed from the conventional one shown in FIG.
Bit, 8-bit, 4-bit, 2-bit, and 1-bit shifters are ordered and the output is provided after the 8-bit shifter to quickly obtain aligned load/store data.

FIG. 2 shows a block diagram of the second embodiment. In the figure, the same components as those in FIG. In this embodiment, the multiplexer 7 is used to provide one output terminal Tout in the first embodiment, but the multiplexer 7 is omitted and the shifters 1-1 to 1
-5 is controlled by the control circuit 6B, and the two output terminals To
ut 1 and Tout 2 are provided, and output data can be obtained from each. This configuration has substantially the same effect as the first embodiment, and uses the output terminal Tout 2 when performing alignment processing of load/store data. It is said that

FIG. 3 shows a block diagram of a third embodiment of the invention. In the figure, the same components as those in FIG.

In this embodiment, the shifters are connected in this order from the input terminal Tin side to the output terminal Tout side: 1-bit shifter 5, 2-bit shifter 4, 4-bit shifter 3, 8-bit shifter 2, and 1-bit shifter 1.
A multiplexer 8 is connected between the 8-bit shifter 2 and the 8-bit shifter 2 . The output of the 4-bit shifter 3 is input to the multiplexer 8, and it is also connected to the input terminal Tin, and input data is input thereto. The multiplexer 8 is connected to the control circuit 6C, and switches its output to the output of the 4-bit shifter 3 or the input data input to the input terminal Tin in response to a control signal from the control circuit 6C.

Next, the operation of the circuit will be explained.

When attempting to shift 8, 16, or 24 bits, the control circuit 6C controls the multiplexer 8.
is controlled so that the data input to the input terminal Tin is directly input to the 8-bit shifter 2, and as in the first embodiment, the 8-bit shifter 2 and the 16-bit shifter 1 are controlled by the control circuit 6C to convert the data to 8, 16, and 24 bits. Perform a minute shift. When performing a shift for another number of bits, the control circuit 6C
The output of 4-bit shifter 3 is set to 8 by multiplexer 8.
It is controlled so that it is input to bit shifter 2, and input terminal T
The input data input to in is transferred to 1-bit shifter 5, 2-bit shifter 4, 4-bit shifter 3, 8-bit shifter 2,
The signal passes through all 16-bit shifters 1, and the required shift amount is obtained by controlling these shifters.

Therefore, for shifts of 8, 16, and 24 bits, it is necessary to pass through only the 8-bit shifter 2 and the 16-bit shifter 1, so that output can be obtained quickly. Therefore, like the first embodiment, this embodiment is suitable for alignment processing of load/store data.

Furthermore, FIG. 4 shows a block diagram of the fourth embodiment. In the figure, the same components as in FIG. 3 are designated by the same reference numerals.
The explanation will be omitted. In this embodiment, the configuration of the third embodiment was such that only data from one input terminal Tin was processed, but the configuration was changed to allow data to be input to the multiplexer 8 separately from two input terminals Tin1 and Tin2. Data for alignment processing of load/store data is input from the input terminal Tin2. With such a configuration, effects similar to those of the third embodiment can be obtained.

FIG. 5 shows a block diagram of a fifth embodiment. In the figure, the same components as those in FIGS. 1 to 4 are denoted by the same reference numerals, and the explanation thereof will be omitted.

In this embodiment, the input terminal Tin is connected to the output terminal T.
out, a plurality of shifters 10 with different shift amounts
-1 to 10-n are provided, and a plurality of shifters 10-1 to 10- are provided.
Multiplexers 9-1 to 9-(n-1) are provided between n and multiplexer 9-1 to 9-(n-1) are provided in front of the output terminal Tout.
n is provided. Shifters 10-1 to 10-n and multiplexers 9-1 to 9-n are connected to control circuit 6D and controlled by control signals from control circuit 6D.

The outputs of the shifters 10-1 to 10-(n-1) are input to the multiplexers 9-1 to 9-(n-1), and the input data input to the input terminal Tin is input to the shifters 9-1 to 9-(n-1). Switching between the output and input data is performed.

The multiplexer 9-n also has a shifter 1.
All outputs from 0-1 to 10-n are input to the control circuit 6.
D selects one output from the shifters 10-1 to 10-n and outputs it to the output terminal Tout.

Next, the operation of the circuit will be explained. first,
If you want to shift by 1 bit, operate 1 bit shifter 10-1 and transfer the input data to 1 bit shifter 1.
Shift by 1 bit by 0-1, multiplexer 9
-n is controlled by the control circuit 6D so that the output of the 1-bit shifter 10-1 is output to the output terminal Tout, thereby obtaining an output shifted by 1 bit from the output terminal Tout. Further, when it is desired to perform a shift of 2 bits, the 2-bit shifter 10-2 is operated, and the multiplexer 9-1 is switched to the 2-bit shifter 10-2 by the control circuit 6D.
-2, and controls the multiplexer 9-n so that the output of the 2-bit shifter 10-2 is outputted to the output terminal Tout. Therefore, the input data input to the input terminal Tin is shifted by 2 bits by the 2-bit shifter 10-2 and output from the output terminal Tout.

Furthermore, when it is desired to shift by 3 bits, the 1-bit shifter 10-1 and the 2-bit shifter 10-2 are operated, and the multiplexer 9-1 shifts the output of the 1-bit shifter 10-1 to the 2-bit shifter 10-2. The multiplexer 9-n controls the output of the 2-bit shifter 10-2 to be output to the output terminal Tout. Therefore, the input data input to the input terminal Tin is shifted by 1 bit by the 1-bit shifter 10-1, and then supplied to the 2-bit shifter 10-2.
It is bit shifted and supplied to the output terminal Tout. Therefore, the input data is shifted by 3 bits and the output terminal To
It will be output from ut.

Similar operations are performed for other shift amounts. In this way, the required shift amount can be obtained through only the minimum necessary shifter, so that output can be obtained at high speed.

FIG. 6 shows a block diagram of a sixth embodiment of the invention. In the figure, the same components as those in FIG. 5 are denoted by the same reference numerals, and the explanation thereof will be omitted.

This embodiment uses the shifter 10-1 in the fifth embodiment.
Input multiplexer 9- provided between ~10-n
1 to 9-(n-1), shifters 10-1 to 10-n
n-input multiplexers 12-1 to 12-1 before each input of
12-n is provided, and the output of the other shifter and the input data input to the input terminal Tin can be input to the input of each shifter 10-1 to 10-n. As a result, the same effects as in the fifth embodiment can be obtained, and the order in which the shifters 10-1 to 10-n are connected becomes irrelevant, so that only the necessary shifters corresponding to the required shift amount can be operated.

For example, when trying to obtain a shift amount of 3 bits, the control circuit 6E controls the 1-bit shifters 10-1 and 10-2.
The bit shifter 10-2 is operated and the multiplexer 12
-1 controls the input data input to the input terminal Tin to be input to the 1-bit shifter 10-1, and the multiplexer 12-2 controls the output of the 1-bit shifter 10-1 to input the output to the 2-bit shifter 10-2. Furthermore, the multiplexer 9-n controls the output of the 2-bit shifter 10-2 to be supplied to the output terminal Tout.

Therefore, the input data input to the input terminal Tin is sent to the multiplexer 12-1 and the 1-bit shifter 10.
-1, multiplexer 12-2, 2-bit shifter 10-
2. Output terminal Tout via multiplexer 9-n
is supplied to obtain a 3-bit shift. At this time,
It is also possible to switch the input/output connections of the multiplexers 12-1, 12-2, and 9-n so that the signal passes through the 1-bit multiplexer 10-1 after the 2-bit multiplexer 10-2.

FIG. 7 shows a block diagram of a seventh embodiment of the invention. This embodiment constitutes a 32-bit barrel shifter. In the figure, the same components as in FIG. 5 are designated by the same reference numerals.
The explanation will be omitted.

In this embodiment, contrary to the fifth embodiment, the shifters are arranged in descending order of shift amount, and instead of multiplexers 9-1 to 9-(n-1) in the fifth embodiment, multiplexers 13-1 to 9-(n-1) are used. 13-4 is provided, and the inputs thereof are increased toward the lower stage, so that all the inputs of the stage before each shifter 10-1 to 10-4 and the input data input to the input terminal Tin are input. The structure is as follows.

With this configuration, substantially the same effects as in the fifth embodiment can be obtained.

For example, when trying to obtain a 6-bit shift amount, the control circuit 6F controls the 4-bit shifters 10-3 and 2.
The bit shifter 10-2 is operated and the multiplexer 13
-2 controls the input data input to the input terminal Tin to be input to the 4-bit shifter 10-3, and the multiplexer 12-3 controls the output of the 4-bit shifter 10-3 to be input to the 2-bit shifter 10-2. Furthermore, the multiplexer 9-n controls the output of the 2-bit shifter 10-2 to be supplied to the output terminal Tout.

Therefore, the input data input to the input terminal Tin is sent to the multiplexer 13-3, 4-bit shifter 10.
-3, multiplexer 13-3, 2-bit shifter 10-
2. Output terminal Tout via multiplexer 9-n
is supplied to obtain a 6-bit shift.

[0050]

[Effects of the Invention] As described above, according to the present invention, input data only needs to pass through the necessary shifters according to the shift amount of the input data before being output, so there is no need to pass through unnecessary shifters. It has features such as being able to output processing results at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the invention.

FIG. 3 is a block diagram of a third embodiment of the present invention.

FIG. 4 is a block diagram of a fourth embodiment of the present invention.

FIG. 5 is a block diagram of a fifth embodiment of the present invention.

FIG. 6 is a block diagram of a sixth embodiment of the present invention.

FIG. 7 is a block diagram of a seventh embodiment of the present invention.

FIG. 8 is a block diagram of a conventional example.

FIG. 9 is a block diagram of another conventional example.

[Explanation of symbols]

1-1 16 bit shifter 1-2 8-bit shifter 1-3 4-bit shifter 1-4 2-bit shifter 1-5 1 bit shifter 6 Control circuit 7, 8 Multiplexer 10-1 to 10-n shifter 9-1 to 9-n multiplexer

Claims (3)

[Claims] [Claim 1] A plurality of shifters each having a different shift amount (
1-1 to 1-5) are connected in series, and by controlling the presence or absence of shift operation of the plurality of shifters (1-1 to 1-5), input data is shifted by a predetermined shift amount and output. In the barrel shifter, the plurality of shifters (1-1 to 1
-5) A barrel shifter comprising first output selection means (7) for selecting and outputting one output from at least two or more of the outputs. [Claim 2] A plurality of shifters each having a different shift amount (
1-1 to 1-5) are connected in series, and by controlling the presence or absence of shift operation of the plurality of shifters (1-1 to 1-5), input data is shifted by a predetermined shift amount and output. A barrel shifter comprising a first input selection means (8) for selecting one of the plurality of shifters and inputting the input data. [Claim 3] A plurality of shifters each having a different shift amount (
10-1 to 10-n) are connected in a cascading manner, and the barrel shifter shifts and outputs input data by controlling whether or not each of the plurality of shifters (10-1 to 10-n) performs a shift operation. , the plurality of shifters (10-1 to
a second input selection means (9-1 to 9-n), which is provided corresponding to the input data and the shifter output of the other stage and selects any one of the input data and the output of the shifter of the other stage and inputs the selected one to the corresponding shifter;
-(n-1), 12-1 to 12-n), and second output selection means (9-n) for selecting and outputting one output from the outputs of the plurality of shifters. Barrel shifter.