JPH04281605A - Oscillation control circuit - Google Patents

Oscillation control circuit

Info

Publication number
JPH04281605A
JPH04281605A JP3044944A JP4494491A JPH04281605A JP H04281605 A JPH04281605 A JP H04281605A JP 3044944 A JP3044944 A JP 3044944A JP 4494491 A JP4494491 A JP 4494491A JP H04281605 A JPH04281605 A JP H04281605A
Authority
JP
Japan
Prior art keywords
oscillation
cmos
inverter
output
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3044944A
Other languages
Japanese (ja)
Inventor
青柳 文孝
Fumitaka Aoyanagi
長谷川 栄一
Eiichi Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Precision Circuits Inc
Original Assignee
Nippon Precision Circuits Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Precision Circuits Inc filed Critical Nippon Precision Circuits Inc
Priority to JP3044944A priority Critical patent/JPH04281605A/en
Publication of JPH04281605A publication Critical patent/JPH04281605A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To realize the oscillation control circuit in which a post-stage circuit is not operated for a small amplitude at the start of oscillation and the post stage circuit starts its operation after the amplitude reaches a prescribed amplitude or over. CONSTITUTION:A CMOS Schmitt trigger inverter ST1 whose one inverting potential (2.0V) is lower than an inverting potential (2.5V) of a CMOS inverter and whose the other inverting potential (3.0V) is higher than the inverting potential (2.5V) of the CMOS inverter is connected to an output of the CMOS inverter IV1 forming the oscillation circuit. Thus, till the oscillation output of the CMOS inverter IV1 exceeds any one inverting potential of the CMOS Schmitt trigger inverter ST1, the post-stage circuit connected to the output of the CMOS Schmitt trigger inverter ST1 is inoperative. Thus, noise is generated by the operation of the post-stage but since the amplitude of the oscillation output is sufficiently increased, the prevention of the oscillation due to the effect of noise is not caused.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は発振制御回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation control circuit.

【0002】0002

【従来の技術】CMOSトランジスタを用いた水晶発振
回路の発振出力を後段に伝える場合、発振回路を構成す
る第1CMOSインバ―タの出力に第2CMOSインバ
ータを接続し、この第2CMOSインバータの出力に後
段回路を接続している。この種の回路において、従来は
、第1CMOSインバ―タの反転電位と第2CMOSイ
ンバータの反転電位とは同一であった。
[Prior Art] When transmitting the oscillation output of a crystal oscillation circuit using CMOS transistors to a subsequent stage, a second CMOS inverter is connected to the output of a first CMOS inverter constituting the oscillation circuit, and the output of the second CMOS inverter is connected to the subsequent stage. Connecting the circuit. In this type of circuit, conventionally, the inversion potential of the first CMOS inverter and the inversion potential of the second CMOS inverter were the same.

【0003】0003

【発明が解決しようとする課題】上記従来の回路では、
発振開始時における微少振幅の発振出力が第2CMOS
インバータで反転され、その反転出力により後段回路が
動作状態になる。したがって、後段回路で生じるノイズ
の影響で発振動作が不安定となり、微少振幅の発振動作
から通常振幅の発振動作への移行が妨げられるという問
題点があった。
[Problem to be solved by the invention] In the above conventional circuit,
The oscillation output with minute amplitude at the start of oscillation is the second CMOS.
The signal is inverted by an inverter, and the inverted output puts the subsequent circuit into operation. Therefore, there is a problem in that the oscillation operation becomes unstable due to the influence of noise generated in the subsequent stage circuit, and the transition from a minute amplitude oscillation operation to a normal amplitude oscillation operation is hindered.

【0004】本発明の目的は、発振開始時の微少振幅時
には後段回路が動作せず、振幅が一定以上の大きさにな
ってから後段回路が動作を開始する発振制御回路を提供
することである。
An object of the present invention is to provide an oscillation control circuit in which the subsequent stage circuit does not operate when the amplitude is small at the start of oscillation, but starts operating after the amplitude reaches a certain level. .

【0005】[0005]

【課題を解決するための手段】本発明では、CMOSイ
ンバータとこのCMOSインバータに並列に接続された
水晶振動子とを有する発振回路の出力に、一方の反転電
位がCMOSインバータの反転電位よりも低く他方の反
転電位がCMOSインバータの反転電位よりも高いCM
OSシュミットトリガインバータを接続した。
[Means for Solving the Problems] In the present invention, an inversion potential of one of the outputs of an oscillation circuit having a CMOS inverter and a crystal resonator connected in parallel to the CMOS inverter is lower than the inversion potential of the CMOS inverter. CM whose other inversion potential is higher than that of the CMOS inverter
I connected an OS Schmitt trigger inverter.

【0006】[0006]

【実施例】図1(A)〜(C)は、本発明に係わる発振
制御回路の実施例を示したものである。
Embodiment FIGS. 1A to 1C show an embodiment of an oscillation control circuit according to the present invention.

【0007】図1(A)に示した各回路要素はつぎの通
りである。IV1はCMOSインバータであり、図1(
B)に示すような入出力特性(伝達特性)を有しており
、その反転電位(論理しきい電圧)は2.5ボルトであ
る。ここでいう反転電位とは、入出力特性における立ち
下がり開始入力電圧と立ち下がり終了入力電圧との中点
の入力電圧であり、通常は出力電圧が電源電圧(5ボル
ト)の半分(2.5ボルト)のときの入力電圧である。 QZ1は水晶振動子、R1は帰還抵抗、C1およびC2
はコンデンサである。以上の回路要素により発振回路が
構成される。ST1はCMOSシュミットトリガインバ
ータであり、図1(C)に示すような入出力特性を有し
ており、第1反転電位(2.0ボルト)がCMOSイン
バータIV1の反転電位よりも低く、第2反転電位(3
.0ボルト)がCMOSインバータIV1の反転電位よ
りも高い。このCMOSシュミットトリガインバータS
T1の出力にはCMOS構成の後段回路(図示せず)が
接続されている。なお、以上述べた回路は同一のICチ
ップ内に収められている。
Each circuit element shown in FIG. 1(A) is as follows. IV1 is a CMOS inverter, as shown in Figure 1 (
It has input/output characteristics (transfer characteristics) as shown in B), and its inversion potential (logical threshold voltage) is 2.5 volts. The inversion potential here is the input voltage at the midpoint between the falling start input voltage and the falling end input voltage in the input/output characteristics, and normally the output voltage is half (2.5 volts) of the power supply voltage (5 volts). volts). QZ1 is a crystal oscillator, R1 is a feedback resistor, C1 and C2
is a capacitor. The above circuit elements constitute an oscillation circuit. ST1 is a CMOS Schmitt trigger inverter and has input/output characteristics as shown in FIG. Reversal potential (3
.. 0 volt) is higher than the inversion potential of CMOS inverter IV1. This CMOS Schmitt trigger inverter S
A subsequent stage circuit (not shown) having a CMOS configuration is connected to the output of T1. Note that the circuits described above are housed within the same IC chip.

【0008】つぎに、本実施例の動作を図2を参照して
説明する。図2(A)に示すように、電源投入によりC
MOSインバータIV1からは微少振幅の発振出力が生
じる。この発振出力の振幅はしだいに増大するが、図2
(B)に示すように、その振幅がCMOSシュミットト
リガインバータST1のいずれかの反転電位(同図では
第1反転電位(2.0ボルト))を越えるまでは、CM
OSシュミットトリガインバータST1の出力は反転し
ない。CMOSインバータIV1の発振出力がCMOS
シュミットトリガインバータST1のいずれかの反転電
位を越えると、CMOSシュミットトリガインバータS
T1から反転出力が生じ、後段回路が動作状態になる。 以後、CMOSインバータIV1の発振出力がCMOS
シュミットトリガインバータST1の第1反転電位(2
.0ボルト)および第2反転電位(3.0ボルト)を越
える毎に、CMOSシュミットトリガインバータST1
の出力は反転する。後段回路が動作することによりノイ
ズが発生するが、このときには発振出力の振幅が十分大
きくなっているので、発振動作が妨げられることはない
Next, the operation of this embodiment will be explained with reference to FIG. As shown in Figure 2(A), when the power is turned on, C
An oscillation output with minute amplitude is generated from MOS inverter IV1. The amplitude of this oscillation output gradually increases, but as shown in Fig.
As shown in (B), the CM
The output of the OS Schmitt trigger inverter ST1 is not inverted. The oscillation output of CMOS inverter IV1 is CMOS
When the inversion potential of either Schmitt trigger inverter ST1 is exceeded, the CMOS Schmitt trigger inverter S
An inverted output is generated from T1, and the subsequent circuit becomes operational. After that, the oscillation output of CMOS inverter IV1 becomes CMOS
The first inversion potential (2
.. 0 volts) and the second reversal potential (3.0 volts), the CMOS Schmitt trigger inverter ST1
The output of is inverted. Noise is generated by the operation of the subsequent stage circuit, but at this time the amplitude of the oscillation output is sufficiently large, so the oscillation operation is not hindered.

【0009】[0009]

【発明の効果】本発明では、CMOSインバータの出力
に、一方の反転電位がCMOSインバータの反転電位よ
りも低く、かつ他方の反転電位がCMOSインバータの
反転電位よりも高いCMOSシュミットトリガインバー
タを設けたため、CMOSインバータの発振出力の振幅
が一定以上の大きさになってから後段回路が動作を開始
する。したがって、後段回路で生じるノイズの影響で発
振動作が妨げられることがない。
[Effects of the Invention] In the present invention, a CMOS Schmitt trigger inverter is provided at the output of the CMOS inverter, in which one inversion potential is lower than the inversion potential of the CMOS inverter, and the other inversion potential is higher than the inversion potential of the CMOS inverter. , after the amplitude of the oscillation output of the CMOS inverter reaches a certain level or more, the subsequent circuit starts operating. Therefore, the oscillation operation is not hindered by the influence of noise generated in the subsequent circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明に係わる発振制御回路の実施例を示した
ものである。
FIG. 1 shows an embodiment of an oscillation control circuit according to the present invention.

【図2】図1の動作を説明したものである。FIG. 2 explains the operation of FIG. 1;

【符号の説明】[Explanation of symbols]

IV1……CMOSインバータ ST1……CMOSシュミットトリガインバータQZ1
……水晶振動子
IV1...CMOS inverter ST1...CMOS Schmitt trigger inverter QZ1
……Crystal oscillator

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  CMOSインバータとこのCMOSイ
ンバータに並列に接続された水晶振動子とを有する発振
回路と、上記CMOSインバータからの発振出力を入力
して上記発振回路の発振周波数と同一周波数の信号を出
力し、一方の反転電位が上記CMOSインバータの反転
電位よりも低く他方の反転電位が上記CMOSインバー
タの反転電位よりも高いCMOSシュミットトリガイン
バータとからなる発振制御回路。
1. An oscillation circuit comprising a CMOS inverter and a crystal resonator connected in parallel to the CMOS inverter, and an oscillation output from the CMOS inverter is input to generate a signal having the same frequency as the oscillation frequency of the oscillation circuit. an oscillation control circuit comprising a CMOS Schmitt trigger inverter, one of which has an inverted potential lower than the inverted potential of the CMOS inverter and the other of which has an inverted potential higher than the inverted potential of the CMOS inverter.
JP3044944A 1991-03-11 1991-03-11 Oscillation control circuit Withdrawn JPH04281605A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3044944A JPH04281605A (en) 1991-03-11 1991-03-11 Oscillation control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3044944A JPH04281605A (en) 1991-03-11 1991-03-11 Oscillation control circuit

Publications (1)

Publication Number Publication Date
JPH04281605A true JPH04281605A (en) 1992-10-07

Family

ID=12705597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3044944A Withdrawn JPH04281605A (en) 1991-03-11 1991-03-11 Oscillation control circuit

Country Status (1)

Country Link
JP (1) JPH04281605A (en)

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Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19980514