JP2779581B2 - Reset signal generation circuit for microprocessor - Google Patents

Reset signal generation circuit for microprocessor

Info

Publication number
JP2779581B2
JP2779581B2 JP5140142A JP14014293A JP2779581B2 JP 2779581 B2 JP2779581 B2 JP 2779581B2 JP 5140142 A JP5140142 A JP 5140142A JP 14014293 A JP14014293 A JP 14014293A JP 2779581 B2 JP2779581 B2 JP 2779581B2
Authority
JP
Japan
Prior art keywords
reset signal
resistor
point
microprocessor
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5140142A
Other languages
Japanese (ja)
Other versions
JPH06332578A (en
Inventor
憲和 市川
義治 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP5140142A priority Critical patent/JP2779581B2/en
Publication of JPH06332578A publication Critical patent/JPH06332578A/en
Application granted granted Critical
Publication of JP2779581B2 publication Critical patent/JP2779581B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、マイクロプロセッサー
用のリセット信号発生回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset signal generating circuit for a microprocessor.

【0002】[0002]

【従来の技術】従来の電源ON時のリセット信号発生回
路は、図2に示すようなトランジスタを利用した回路
か、あるいは専用のIC等を利用するのが一般的であっ
た。
2. Description of the Related Art A conventional reset signal generation circuit at power-on is generally a circuit using a transistor as shown in FIG. 2 or a dedicated IC or the like.

【0003】[0003]

【発明が解決しようとする課題】上記従来の技術におい
て述べたリセット信号発生回路は、トランジスタや専用
ICを利用していたためにコストが割高であり且つ広い
スペースが必要である等の欠陥を有していた。
The reset signal generation circuit described in the above prior art has drawbacks such as high cost and a large space requirement due to the use of transistors and dedicated ICs. I was

【0004】抑々、マイクロプロセッサーボードを構成
(設計)する場合には、搭載した汎用ゲートICに未使
用のゲートを残している。
[0004] When configuring (designing) a microprocessor board, unused gates are left on the mounted general-purpose gate IC.

【0005】本発明は、上記未使用のゲートすなわち、
インバータを構成できるゲート(NOT,NOR,NA
NDゲート等)の2個を利用する等の手法により上記欠
陥を解消するようにした、新規のマイクロプロセッサー
用のリセット信号発生回路を提供することを目的とする
ものである。
According to the present invention, the above-mentioned unused gate, that is,
Gates that can constitute inverters (NOT, NOR, NA
It is an object of the present invention to provide a new reset signal generation circuit for a microprocessor in which the above-mentioned defect is solved by a method using two ND gates or the like.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
に本発明に係わるマイクロプロセッサー用のリセット信
号発生回路は、ダイオードDと抵抗Rtを並列に接続
し、当該ダイオードDの一方極をコンデンサCtを介し
て接地し、また同ダイオードDの他方極に+電圧を印加
するようにすると共にダイオードDとコンデンサCt間
の分岐点Aに抵抗Rsの一端を、同抵抗Rsの他端に直
列状態でインバータを、当該インバータの入力端側点B
と出力端側点Cとに対して並列状態として正帰還抵抗R
fの両端をそれぞれ接続し、出力端側点Cにリセット信
号出力線を接続したものである。
In order to achieve the above object, a reset signal generating circuit for a microprocessor according to the present invention comprises a diode D and a resistor Rt connected in parallel, and one terminal of the diode D connected to a capacitor Ct. And a positive voltage is applied to the other pole of the diode D. One end of a resistor Rs is connected in series with the other end of the resistor Rs at a branch point A between the diode D and the capacitor Ct. The inverter is connected to the input end point B of the inverter.
And a positive feedback resistor R in parallel with the output end point C.
f, both ends are connected, and a reset signal output line is connected to an output end side point C.

【0007】[0007]

【実施例】図1に示す本発明に係わるマイクロプロセッ
サー用のリセット信号発生回路は、ダイオードDと抵抗
Rtを並列に接続し、当該ダイオードDの一方極をコン
デンサCtを介して接地し、また同ダイオードDの他方
極に+5Vを印加するようにすると共にダイオードDと
コンデンサCt間の分岐点Aに抵抗Rsの一端を、同抵
抗Rsの他端に直列状態で複数個のCMOSインバータ
1、2を、これらCMOSインバータ1、2の入力端側
点3と出力端側点Cとに対して並列状態として正帰還抵
抗Rfの両端をそれぞれ接続し、出力端側点Cにリセッ
ト出力線3を接続したものである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A reset signal generating circuit for a microprocessor according to the present invention shown in FIG. 1 has a diode D and a resistor Rt connected in parallel, and one pole of the diode D is grounded via a capacitor Ct. A voltage of +5 V is applied to the other pole of the diode D, and one end of a resistor Rs is connected to a branch point A between the diode D and the capacitor Ct, and a plurality of CMOS inverters 1 and 2 are connected in series to the other end of the resistor Rs. Both ends of the positive feedback resistor Rf are connected in parallel with the input end point 3 and the output end point C of the CMOS inverters 1 and 2, and the reset output line 3 is connected to the output end point C. Things.

【0008】[0008]

【作用】上記実施例に依拠した本発明に係わるマイクロ
プロセッサー用のリセット信号発生回路の作用を説明す
る。すなわち、 電源OFF→ON動作:抵抗Rt<<抵抗Rf(R
tの値はRfに比べて十分に小さい)に回路を高した場
合、A点の電圧は電源ONと同時に、抵抗Rt・コンデ
ンサCtの時定数で0Vから5Vまでゆっくり上昇す
る。これに伴ってB点の電圧Vbは Vb=Va・{Rf/(Rs+Rf)} (ただし、Rf/(Rs+Rf)>0.5の条件を満た
すこと。) 式に従って、Vaに連れて上昇する。斯くして、B点の
電圧Vbが2.5V(CMOSのしきい値)に達する
と、C点の電圧が0Vから5Vへ上昇する。このC点の
上昇が正帰還抵抗RfによってB点の電圧を上昇させ、
C点の電圧上昇を加速する(正帰還による加速)。すな
わち、リセット出力Vcは、Vaが2.5・(Rs+R
f)/Rfに上昇するまでの時間(リセットデイレー時
間)に+5Vに反転する。 電源ON→OFFの動作:電源ONの状態では、V
cは+5Vになっている。ここで電源はOFFになると
ダイオードDを経由してコンデンサCtがすみやかに放
電されVaが0Vに下がる。斯くすると、B点も Vb=Vc・{Rs/(Rs+Rf)} 式に従って、Vbはしきい値2.5Vより低くなり、V
cが5Vから0Vへ降下する。このC点の電圧降下が正
帰還抵抗RfによりB点の電圧降下を加速するため、電
源OFFとほぼ同時にリセット出力も0Vとなる。
The operation of the reset signal generating circuit for a microprocessor according to the present invention based on the above embodiment will be described. That is, power supply OFF → ON operation: resistance Rt << resistance Rf (R
When the circuit is raised to a value (t is sufficiently smaller than Rf), the voltage at the point A rises slowly from 0 V to 5 V by the time constant of the resistor Rt and the capacitor Ct at the same time when the power is turned on. Accordingly, the voltage Vb at the point B rises with Va according to the equation: Vb = Va {{Rf / (Rs + Rf)} (where the condition of Rf / (Rs + Rf)> 0.5 is satisfied). Thus, when the voltage Vb at the point B reaches 2.5 V (the threshold value of the CMOS), the voltage at the point C increases from 0 V to 5 V. This rise of the point C causes the voltage of the point B to rise by the positive feedback resistor Rf,
Accelerate the voltage rise at point C (acceleration by positive feedback). That is, as for the reset output Vc, Va is 2.5 · (Rs + R
f) Invert to +5 V during the time until the voltage rises to / Rf (reset delay time). Power ON → OFF operation: When the power is ON, V
c is + 5V. Here, when the power supply is turned off, the capacitor Ct is immediately discharged via the diode D, and Va drops to 0V. In this way, the point B also becomes lower than the threshold value of 2.5 V according to the equation Vb = VcV {Rs / (Rs + Rf)}.
c drops from 5V to 0V. Since the voltage drop at the point C accelerates the voltage drop at the point B by the positive feedback resistor Rf, the reset output becomes 0 V almost at the same time when the power is turned off.

【0009】[0009]

【発明の効果】本発明は係わるマイクロプロセッサー用
のリセット信号発生回路は、上記のような構成であって
上記作用において述べたように機能するものであるの
で、トランジスタや専用ICが不要なものであり、その
分コストおよびスペースを節約できものであり、所期の
目的を充分に達成する優れた効果を奏するものである。
According to the present invention, the reset signal generation circuit for a microprocessor according to the present invention has the above-described configuration and functions as described in the above operation, so that a transistor and a dedicated IC are unnecessary. As a result, the cost and space can be saved correspondingly, and an excellent effect of sufficiently achieving the intended purpose can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例を示す回路図である。FIG. 1 is a circuit diagram showing an embodiment of the present invention.

【図2】従来の実施例を示す回路図である。FIG. 2 is a circuit diagram showing a conventional example.

【符号の説明】[Explanation of symbols]

D ダイオード Rt 抵抗 Ct コンデンサ A 分岐点 Rs 抵抗 1 COMSインバータ 2 COMSインバータ Rf 正帰還抵抗 B 入力端側点 C 出力端側点 3 リセット信号出力線 D Diode Rt Resistance Ct Capacitor A Branch point Rs Resistance 1 COMS inverter 2 COMS inverter Rf Positive feedback resistor B Input end point C Output end point 3 Reset signal output line

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 ダイオードDと抵抗Rtを並列に接続
し、当該ダイオードDの一方極をコンデンサCtを介し
て接地し、また同ダイオードDの他方極に+電圧を印加
するようにすると共にダイオードDとコンデンサCt間
の分岐点Aに抵抗Rsの一端を、同抵抗Rsの他端に直
列状態でインバータを、また当該インバータの入力端側
点Bと出力端側点Cとに対して並列状態として正帰還抵
抗Rfの両端をそれぞれ接続し、出力端側点Cにリセッ
ト信号出力線を接続したことを特徴とするマイクロプロ
セッサー用のリセット信号発生回路。
1. A diode D and a resistor Rt are connected in parallel, one pole of the diode D is grounded via a capacitor Ct, and a positive voltage is applied to the other pole of the diode D. One end of a resistor Rs is connected to a branch point A between the resistor Rs and the capacitor Ct, an inverter is connected in series with the other end of the resistor Rs, and an input end point B and an output end point C of the inverter are connected in parallel. A reset signal generating circuit for a microprocessor, wherein both ends of a positive feedback resistor Rf are connected to each other, and a reset signal output line is connected to an output terminal side point C.
JP5140142A 1993-05-19 1993-05-19 Reset signal generation circuit for microprocessor Expired - Fee Related JP2779581B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5140142A JP2779581B2 (en) 1993-05-19 1993-05-19 Reset signal generation circuit for microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5140142A JP2779581B2 (en) 1993-05-19 1993-05-19 Reset signal generation circuit for microprocessor

Publications (2)

Publication Number Publication Date
JPH06332578A JPH06332578A (en) 1994-12-02
JP2779581B2 true JP2779581B2 (en) 1998-07-23

Family

ID=15261855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5140142A Expired - Fee Related JP2779581B2 (en) 1993-05-19 1993-05-19 Reset signal generation circuit for microprocessor

Country Status (1)

Country Link
JP (1) JP2779581B2 (en)

Also Published As

Publication number Publication date
JPH06332578A (en) 1994-12-02

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