JPH04280492A - Manufacture of optical semiconductor element - Google Patents

Abstract

PURPOSE:To accurately form an end face such as light-emitting face or light- receiving face on a section with difference in level of a semiconductor element with a desired pattern by a method wherein the end face such as light-emitting face or light-receiving face is formed on the section with difference in level in a process in which three layer resist is used. CONSTITUTION:A SiO2 insulating film 12, a flattening resist 13, a Ti intermediate layer 14, and a Ti patterning resist 15 are formed on a laser substrate 11. Then, The patterning is performed on the Ti intermediate layer 14. Then, the flattening resist 13 is vertically dry-etched by using the Ti patterning resist 15 and the patterned Ti intermediate layer 14 as a etching mask. After this, a light-emitting face 16 or light-receiving face is formed on the section with difference in level with dry-etching by using the SiO2 insulating film 12, the flattening resist 13, the Ti intermediate layer 14 as a etching mask. Thus, it is made possible to accurately form an end face such as a light-emitting face 16 or light-receiving face on the section with difference in level of the optical semiconductor element in accordance with the mask pattern.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

[Industrial Application Field] The present invention relates to a method of manufacturing an optical semiconductor element in a semiconductor manufacturing process, in which the light emitting surface or light receiving surface of the optical semiconductor element is The present invention relates to a method of forming an end face of a by dry etching.

0002

[Prior Art] In recent years, III-V compound semiconductors and
- Group VI compound semiconductors are used in optical devices such as semiconductor lasers, light emitting diodes, and light receivers, and because of their high mobility, they are used in electronic devices such as field effect transistors and heterobipolar transistors. In these devices, a dry etching method is used as a technique for creating fine structures at desired locations. Specifically, this includes forming laser end faces for integrating semiconductor lasers, forming isolation grooves to electrically isolate two or more elements made on the same substrate, and creating fine gates in electronic devices. It is. In particular, since the laser end face corresponds to the extraction port for the light emitted from the active layer,
In order to prevent light loss due to decrease in end face reflectance, flatness and perpendicularity equivalent to cleavage planes are required. On the other hand, as optical devices and electronic devices become more integrated and have higher performance, structures with steps are becoming inevitable. In some cases, the level difference may increase to about 3 to 5 μm. When processing such a substrate, if a normal PEP process is performed on the step, the thickness of the resist differs at the top and bottom of the step, resulting in different optimal exposure conditions, making it difficult to pattern the step faithfully to the mask. Figure 7
, as shown in FIG. 8, unevenness reflecting the shape of the step is generated. In other words, when the stepped portion is groove-shaped, FIG. 7 ((a) is a top view,
b) is a cross-sectional view taken along line A-A in (a), as shown in
The resist 72a bulges to the side of the substrate 71a, and in the case of a terrace shape, the resist 72a is shown in FIG.
As shown in the cross-sectional view taken along line B), it is observed that the resist 72b is recessed to the side of the substrate 71b. Due to the above, when applied to the light emitting end face of a semiconductor laser, for example, this end face is bulged or concave and has a curvature, which scatters the laser light compared to a flat cleaved end face, reducing the light extraction efficiency and causing oscillation. There was a problem in that the threshold current increased.

0003

[Problem to be Solved by the Invention] When attempting to form the end faces such as the light emitting surface and the light receiving surface of an optical semiconductor element having steps using a normal PEP process, unevenness occurs at the step portions, which reduces the light extraction efficiency and light receiving efficiency. There were problems such as a decline in the performance. SUMMARY OF THE INVENTION An object of the present invention is to provide a manufacturing method for fine-machining an optical semiconductor element, which allows end faces such as a light emitting surface and a light receiving surface to be formed faithfully in a desired pattern at a stepped portion of the optical semiconductor element.

[Configuration of the invention]

[0005]

[Means for Solving the Problems] The present invention provides an optical semiconductor device having a step, in which an end surface such as a light emitting surface or a light receiving surface is formed at the step by a process using a three-layer resist as described below. It is characterized by the formation of The process using the above three-layer resist is
This process was developed as a process that corresponds to steps of about 1 μm used in microfabrication and multilayer interconnection associated with high integration of LSI etc. (J. Vac. Sci. Technol. B2 (
1) pp34-37 (1984)). Although there are many variations to the process using the three-layer resist, the basic one will be briefly explained below with reference to FIG. 4. As shown in FIG. 4A, a thick organic resist layer 43 is formed on the layer 42 to be patterned of the substrate 41 having steps, so as to fill the steps and make the surface flat. Next, as shown in FIG. 4(b), a thin inorganic intermediate layer 44 and a resist layer 45 are sequentially formed on the layer to be patterned 42, and then the resist layer formed on the intermediate layer is patterned. Then, using the resist layer as a mask, the intermediate layer is etched (FIG. 4(c)). At this time, since the intermediate layer is thin, the initial pattern can be directly transferred to the intermediate layer without causing problems such as undercuts. Next, the resist layer 43 formed for planarization is etched, but since the resist layer is organic, if oxygen plasma or the like is used, etching can be performed using the intermediate layer 44 and the resist layer 45 formed on the intermediate layer as a mask. (Figure 4(d)
)). At this time, the resist layer 45 on the intermediate layer is also etched at the same time, and the intermediate layer 44 is exposed. Finally, in Figure 4 (
As shown in e), the layer 42 to be patterned is etched using the intermediate layer 44 and the flattened resist layer 43 as masks in the patterning method using the three-layer resist described above. Note that the planarization resist layer does not need to be photosensitive, so it is possible to select one that is resistant to high temperatures. A major feature of the present invention is that this three-layer resist is used in an optical semiconductor element with steps to form an end surface such as a light emitting surface or a light receiving surface.

That is, the method for manufacturing an optical semiconductor device according to the present invention involves coating a fluid organic material on a stepped portion of the main surface of a substrate or on a stepped portion of a substrate whose main surface is coated with a thin film. a step of forming an inorganic thin film after heat treatment; a step of patterning the inorganic thin film; and a step of vertically processing the organic member using the pattern of the inorganic thin film as an etching mask. and a step of forming end faces such as a light emitting surface and a light receiving surface on the stepped portion of the substrate using the processed organic member as an etching mask.

[0007]

[Operation] According to the present invention, even if there is a difference in level, the resist is applied thickly, the surface is flattened, and then patterned, the pattern is transferred to the intermediate layer that is highly resistant to dry etching, and this intermediate layer is A dry etching layer using a flattened resist as an etching mask, or an insulating layer etched using a processed resist layer as a mask can be used as an etching mask for a crystal substrate to faithfully create a desired pattern. Therefore, the end faces such as the light emitting surface and the light receiving surface of the optical semiconductor element can be formed without unevenness according to the mask pattern, and it is possible to prevent a decrease in light extraction efficiency and light reception efficiency, an increase in threshold current density, etc.

[0008]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) As a first embodiment of the present invention, the formation of an etched end face of a buried semiconductor laser will be described.

Referring to FIG. 2, which shows a cross-sectional view of the structure of a buried semiconductor laser, 20 is an InP substrate, 21 is an active layer,
22p, 22n are cladding layers, 23 is an ohmic layer, 2
4p and 24n are current blocking regions.

[0011] In its formation, it is processed into an inverted mesa shape,
The active layer 21 is formed into stripes having a width of 1 to 3 μm and is embedded by selective growth of an n-p reverse junction. The active layer 21 is made of InGaAsP and has a lattice constant matching that of InP, and has an emission wavelength of 1 to 1.6 μm. The cladding layers 22p and 22n are InP. In the case of inverted mesa shape embedding, the embedding layer is reliably embedded and a margin is provided so that the embedding layer rises above the processed substrate.
As a result, grooves are formed on the active layer corresponding to the bulges. Defining the width of the groove at its widest point, it is 5 to 10 μm, and the depth is 2 to 3 μm. A p-side electrode is formed on the entire surface, a SiO2 insulating film is formed on it by atmospheric pressure CVD, and an MP-1400 series resist is applied on top of the p-side electrode by adjusting the rotational speed of spin coating to change the groove width and groove depth. Coat to a thickness greater than the critical thickness corresponding to In the case of a groove, the critical film thickness of the resist is determined by the width and depth of the groove. In order to stably adjust the spin coating thickness of the resist, it is preferable to adjust the viscosity of the resist by changing the rate of thinner dilution in addition to the rotation speed of the coater. The thickness of the resist can be increased by slowing down the rotation speed of the coater, but this is a region where the thickness of the resist changes rapidly with respect to the rotation speed, making it difficult to control and causing variations in the in-plane thickness of the resist. This is because it gets bigger. Here, a case will be described in which the substrate groove width is 5 μm and the groove depth is 3 μm. Under this groove condition,
The thickness of the resist needs to be 4 μm or more at the top of the step, so the resist MP-1400-31 is spin coated with 300
Coat for 30 seconds at 0 rpm, bake at 90°C for 10 minutes, then bake at 150°C for 30 minutes or more. Baking at a low temperature for the first time is suddenly 15
This is because the gas components in the resist will foam if baked at 0°C, and baking at 150°C for more than 30 minutes is
This is to promote planarization of the resist and to remove gas components in the resist. There are examples of baking at 250°C, but in order to perform the process at a low temperature, it is better not to raise the temperature more than necessary. Since resist dry etching is performed at a temperature of 100°C or higher, 150°C is sufficient. If this temperature is increased, it becomes difficult to remove the resist hardened by the oxygen plasma asher.

After baking the resist, Ti is formed to a thickness of 200 nm by electron beam evaporation, and a resist for Ti patterning is applied thereon. If the thickness of Ti is too thick, undercuts will occur on the sides during patterning of Ti, resulting in a drop in dimensional accuracy. On the other hand, the critical thickness of the thinner Ti layer is the time it takes for the resist to be etched to the groove (corresponds to the resist thickness + depth of the substrate step)
Determined by the thickness it can withstand. If the thickness of Ti is thin, the resist will become tapered from the point where Ti is removed during etching of the resist, and the mask pattern will not be faithfully reflected. In this way, the SiO2 insulating film 12, the planarization resist 13, the intermediate layer 14, and the Ti patterning resist 15 are formed on the laser substrate 11, as shown in FIG. 1(a).

Next, the intermediate layer Ti is patterned to form the structure shown in FIG. 1(b). The above Ti patterning was performed using reactive ion etching (RIE) using a chlorine gas system.
) or reactive ion beam etching (RIBE). Here, chlorine is 5 x 10-4 Torr, argon is 1
RIBE (extraction voltage 400 V, magnetic field strength 875 Gauss, microwave output 200 W) using a mixed gas of ×10 −3 Torr was performed. Further, the patterning of Ti may be performed by a wet method. For example, this can be done by using an etchant made by diluting a saturated hydrofluoric acid solution ten times. If the thickness of Ti is 200 nm, etching for about 10 seconds is sufficient.

Next, using the Ti patterning resist and the Ti 14 patterned thereby as an etching mask, a flattened resist 13 is formed as shown in FIG. 1(c).
Dry etching vertically. The etching at this time was performed by ECR-RIBE (electron cyclotron resonance reactive ion beam etching) using oxygen gas. In order to faithfully transfer the pattern, it is necessary to make the etching shape of the flattened resist vertical, so it is preferable to perform etching in a relatively high vacuum region where the direction of the ion beam is aligned. Here, oxygen is 1×10-3 Torr (
The extraction voltage was 850 V, the magnetic field strength was 875 Gauss, and the microwave output was 200 W) for 30 minutes. The etched shape of the flattened resist maintains a vertical shape at the top, but near the bottom it becomes a tailed shape, which eventually disturbs the patterning of the etching mask under the flattened resist, resulting in a pattern that is faithful to the mask. Can not. However, if the etching time is increased, the bottom surface of the planarized resist also becomes vertical, making it possible to perform patterning faithful to the mask. That is, the etching time is required to be longer than a certain amount of time corresponding to the thickness of the planarized resist. This dry etching using oxygen simultaneously etches the SiO2 insulating film formed on the p-side electrode of the laser and the p-side electrode, but since the groove is exposed to oxygen plasma for a short time, the bottom of the groove In some cases, the SiO2 insulating film and p-type electrode may not be removed sufficiently, so RIE (reactive ion etching) using CF4 or a mixed gas of CF4 and oxygen gas or RIBE (reactive ion beam etching) may be used. Completely remove the SiO2 insulating film. Wet etching using a mixed solution of HF and NH4F, which is usually used to remove a SiO2 insulating film, may also be used. If the remaining p-side electrode contains Ti, use chlorine gas RI.
E or RIBE, those containing Au, Zn, and Pt are Ar
Remove by sputtering, etc. There is no need to etch the electrodes if the electrodes are patterned in advance and a SiO2 insulating film etching mask is formed thereon so that there are no electrodes where the end faces are to be formed.

After that, as shown in FIG. 1(d), SiO2
Using the insulating film 12, planarization resist 13, and Ti intermediate layer 14 as etching masks, a light emitting end face 16 of the laser element is formed by dry etching.

Etching of the optical semiconductor element substrate will be described below.

The conditions for dry etching are as follows: a microwave output of 200 W and a magnetic field strength of 875 Gauss are used to turn a mixed gas of Cl2 gas and Ar gas introduced into the plasma chamber into plasma, and an extraction voltage of 400 V is used to generate ions and excited states in the sample chamber. of reactive particles. Here, the Cl2 partial pressure in the sample chamber was 7.5 x 10-4 Torr, and the Ar partial pressure was 1.4 x 10-3 Torr. The obtained ion current density was 0.24 mA/cm2, and the surface temperature of the substrate rose from room temperature to 180° C. in about 2 minutes due to ion irradiation, and remained stable thereafter. Etching was performed for 20 minutes, and the depth of the etched groove was 5 μm. Since the Ti in the intermediate layer is removed by RIBE of a gas containing chlorine during etching of the semiconductor substrate, after etching the semiconductor substrate, the resist is removed by an oxygen plasma asher and the Ti layer is formed on the p-side electrode of the laser. The SiO2 insulating film is removed using a wet etchant using a mixed solution of HF and NH4F. Before etching the semiconductor substrate, there is a concern about damage to the crystal due to oxygen plasma asher.
If only the SiO2 insulating film mask is left and the resist and Ti intermediate layer are removed, there is no need to perform plasma ashing after forming the end face.

As described above, when the end face reflectance of the optical semiconductor laser produced is estimated from the ratio of the optical output from the dry etched end face and the cleaved face after cleaving one face, it is 28 to 28%, compared to 32% for the cleaved face. It was in the range of 35%. There was also almost no significant difference in the threshold current between the double-sided dry-etched end face and the double-sided dry-etched end face. Rather, if both end faces are formed according to the present invention, the resonator length can be precisely controlled, and variations due to cleavage errors can also be reduced. Furthermore, without forming a high reflection film on the end face,
Even a short resonator of 0 μm oscillated at 50 mA. If the end face is formed by a normal PEP process without using the present invention, the end face will protrude, and the shape of the protrusion will change depending on the depth and width of the step, so the manner of light scattering will differ. As a result, the reflectance at the end facets varies from 10 to 30%, the oscillation threshold current also varies, and the average value is higher than that of a double-sided cleaved laser (the average oscillation threshold current is 20 to 30 mA). became. This increase in threshold current greatly depends on the resonator length, and the shorter the resonator length, the greater the effect of reflection loss at the end facets on the oscillation threshold current.
The rise was larger compared to the cleavage plane laser. This threshold current does not differ much when the cavity length is 700 μm or more compared to a double-sided cleaved laser, but when the cavity length is 70 μm or more,
When it became 0 μm or less, a sharp increase was observed in the case of double-sided dry etched end faces. Even if one side of the single-sided dry-etched end face was a cleavage plane, a sharp increase was observed when the cavity length was less than 500 μm (Figure 3).

In the above embodiments, an SiO2 insulating film is formed on a semiconductor laser substrate on which electrodes are formed, and this S
Although the iO2 insulating film was used as a dry etching mask for the semiconductor crystal, a flattening resist may be applied directly to the semiconductor laser substrate on which the electrodes are formed, and the laser end face may be formed in the same manner.

Furthermore, it is also possible to form not only the end face of the semiconductor laser but also grooves for isolating adjacent semiconductor lasers at the same time. For example, if a groove deeper than the position of the active layer is formed in the center of the stripe of a laser array substrate in which the active layer stripe spacing is 100 to 400 μm, one dry etching process can simultaneously form the end face of the semiconductor laser and isolate it. be able to.

(Embodiment 2) Next, a second embodiment in which an emission end face is formed in a ridge type semiconductor laser will be described. In this case, when a normal PEP process is performed, the resist recedes in the ridge portion including the active layer stripe and the end face becomes depressed, contrary to the case with the groove. If the thickness of the flattened resist is thin, problems such as breakage of the resist near the corners of the ridge portion and thinning of the portions occur. The active layer is I
The lattice constant of nGaAsP matches that of InP, the emission wavelength is 1 to 1.6 μm, and the cladding layer is InP. As an example, in Figure 5, the stripe width of the ridge part is 10
A structure in which the active layer width is 1 to 3 μm, the height is 3 μm, and the sides are buried by mass transport of InP will be described. There are various methods for mass transporting InP, such as transporting chlorides of InP, hydride vapor phase growth or halide vapor phase growth using chloride and bromide transport, and annealing in a phosphine atmosphere. After forming an electrode on the ridge portion, SiO is etched as an etching mask for the crystal 51.
2. An insulating film 52 is formed to a thickness of 500 nm, a resist 53 is formed to a thickness of 5 μm on top of the insulating film 52 to make it flat, and a laser end face is formed in the same manner as above.

(Embodiment 3) Next, a third embodiment including integration of a semiconductor laser and a photodetector will be described. The laser structure may be an inverted mesa-embedded type or a ridge type, as long as it includes a semiconductor laser and a light receiver for monitoring its emitted light on the same substrate. Here, an example will be described in which a groove of 5 to 50 μm is formed between a semiconductor laser and a light receiver. In addition to the light extraction end face on the front surface of the semiconductor, the end face from which monitor light is taken out on the rear face of the semiconductor, and the light receiving end face of the light receiver are formed at the same time. If the semiconductor laser is a DFB laser, it is better to make the rear surface oblique by 5 to 45 degrees from the cleavage plane in order to suppress the Fabry-Perot mode. Similarly, the light receiving surface is 5
By tilting it at an angle of about 100 degrees, we suppressed the reflected light from the light-receiving surface from entering the rear surface of the laser, causing the wavelength to shift or other modes from arising, which would disturb the laser operation. The present invention is particularly effective when forming the end face deviated from the cleavage plane in a place where there is a step. Ordinary PEP without using the present invention
When a slanted end face is formed due to the process, the angle varies, which causes variations in element characteristics such as threshold current, oscillation spectrum, and mode control in the case of DFB lasers, and the integration of photodetectors actually worsens the yield. Ta. The thickness of the planarized resist is mainly determined by the shape of each step. When the semiconductor laser and receiver are integrated, the rear surface of the laser is tapered at an angle of about 45 degrees with the substrate surface, and this surface is used as a reflector to extract light to the top surface, functioning as a surface-emitting laser. It may also be possible to perform on-wafer inspection.

(Embodiment 4) Next, a fourth embodiment including integration of a semiconductor laser and a waveguide will be described. The semiconductor laser and optical receiver are integrated, except that the wavelength of the light from the active layer of the laser is not absorbed by the waveguide layer of the waveguide, and the attenuation of the light during waveguide is small. Same as in case. In this case, it is necessary that the band gap of the active layer of the laser is smaller than the band gap of the waveguide layer, so it is necessary to change the carrier concentration and composition of each layer. For this reason, it involves multiple selective growths, making it difficult to flatten the structure, and making it impossible to avoid a stepped structure. An example is a structure as shown in FIG. In this case, after vertically etching the end face of the DFB laser, use S as an etching mask for the laser part.
Using the iO2 insulating film as a non-growth mask for selective growth, the waveguide structure is selectively grown, and the entire SiO2 insulating film is used as a non-growth mask for selective growth.
2. After forming an insulating film 61, a flattening resist 62,
A Ti intermediate layer 63 and a patterning resist 64 are sequentially formed, and a groove is formed between the laser and the waveguide in the same manner as above. This groove may be filled with crystal. Even when integrating a laser and a waveguide in this way, it is necessary to process a substrate with steps for selective growth, and the present invention becomes effective. In particular, since there is no decrease in light extraction efficiency or light reception efficiency, flat end faces similar to cleavage can be created in any direction, which not only increases the coupling efficiency with the waveguide but also increases design freedom. It can also be made larger. Of course, it goes without saying that the present invention can also be applied to the formation of the laser end face before the formation of the waveguide structure if the laser has a stepped structure. It can also be applied to devices with complex layer structures such as photonic ICs (PICs) that functionally integrate variable wavelength lasers, waveguides, switching elements, drive circuits for the respective elements, light receivers, and the like.

In the explanation so far, I
Although an nP/InGaAsP semiconductor laser has been described, the present invention is not dependent on the material. Even when an InP substrate is used, the active layer is InGaAsP with a lattice constant matching that of InP, and the emission wavelength is 1 to 1.6μ.
In addition to m, I whose lattice constant matches InP
nGaAs may also be used. In addition, the active layer is made of InGaA
A multiple quantum well structure composed of a combination of sP and a plurality of InGaAsP thin layers having different compositions may be used. In a multi-quantum well structure, each lattice constant does not need to match that of the substrate, and the composition may be intentionally shifted to introduce distortion. The cladding layer is I instead of InP.
A structure using nAlAs or a graded structure in which the composition gradually changes from the active layer to the cladding layer may be used.

When GaAs is used for the substrate, the active layer may be made of GaAlAs, the cladding layer may be made of GaAlAs having a lower refractive index than the active layer, or the active layer may be made of GaAs and a combination of multiple GaAlAs thin layers having different compositions. The cladding layer is made of GaA.
It may be made of lAs or GaAs, or it may have a graded structure in which the composition gradually changes from the active layer to the cladding layer. In a multi-quantum well structure, each lattice constant does not need to match that of the substrate, and the composition may be intentionally shifted to introduce distortion. The substrate is GaAs, the active layer is InGaP, the cladding layer is InGaAlP, InAlP, or GaAlAs, and the active layer is InGaA.
IP with a composition in which the cladding layer has a lower refractive index than the active layer.
nGaAlP, active layer is GaAs and cladding layer is InG
aP, the active layer is InGaP, and multiple In
It has a multiple quantum well structure composed of a combination of GaAlP thin layers, and the cladding layer is InGaP or InGaP.
It may be made of AlP or may have a graded structure in which the composition gradually changes from the active layer to the cladding layer. In a multi-quantum well structure, each lattice constant does not need to match that of the substrate, and the composition may be intentionally shifted to introduce distortion. The substrate is GaP and GaAs is placed on top of it.
Gradually increase the As composition in the direction of P growth from the substrate to 10~
Using a substrate grown to 100 μm and having a GaAsP surface, the active layer is InGaAsP whose lattice constant matches that of GaAsP, and the emission wavelength is 0.65 to 0.75 μm.
The cladding layer may be made of GaAsP. In addition, the present invention can be appropriately modified and applied to any structure as long as the level difference of the optical semiconductor element is determined. For example, CdS, CdS
Se, ZnS, ZnSSe, PbS, PbSSe, Cd
It can also be applied to structures containing II-VI compound semiconductors such as HgTe and CdTe. The present invention is also effective for optical semiconductor elements formed on Si, oxides, etc. that do not themselves emit light.

Furthermore, the material of the intermediate layer is not limited to Ti; if the etching selectivity with respect to the resist is high, Z
r, Nb, V, Cr, Mo, W, Ta, Al, Si, graphite, etc. can be used as appropriate.

[0027] In the above embodiments, ECR-RIBE etching was exemplified as an etching method for the flattened resist, but the present etching method is not limited to this equipment, and may be performed using, for example, RIE, magnetron RIE, or other equipment. It can also be applied to etching.

[0028]

[Effects of the Invention] As explained above, according to the present invention, by using a three-layer resist, end faces such as a light emitting surface and a light receiving surface can be formed faithfully to a mask pattern in a stepped portion of an optical semiconductor element. This prevents a decrease in light extraction efficiency and light reception efficiency.

[Brief explanation of the drawing]

1A to 1D are cross-sectional views for explaining a step of forming an end face on a stepped laser substrate according to an embodiment of the present invention; FIG.

FIG. 2 is a cross-sectional view of an example of an optical semiconductor element formed by the manufacturing method of the present invention.

FIG. 3 is a diagram for explaining the correlation between the resonator length and the oscillation threshold current.

4A and 4B are cross-sectional views showing the patterning of a resist on a step in the order of steps; FIG.

FIGS. 5A and 5B are cross-sectional views for explaining an end face forming process for a ridge-type laser substrate. FIGS.

FIG. 6 is a cross-sectional view showing an example of application to integration of a semiconductor laser and a waveguide.

FIGS. 7(a) and 7(b) show patterning of a resist into steps (grooves) in a conventional example. (a) is a top view, (b)
is a sectional view taken along line A-A in (a).

FIGS. 8(a) and 8(b) show patterning of a resist into steps (terrace-like) in a conventional example. (a) is a top view, (
b) is a sectional view taken along line BB in (a).

[Explanation of symbols]

11 Laser board 12 SiO2 insulation film 13 Planarization resist 14 Middle class

Claims (1)

[Claims] Claim 1: A step of applying a fluid organic material onto the stepped portion of the main surface of the substrate or onto the stepped portion of the substrate whose main surface is coated with a thin film to flatten the upper surface, and heat treatment. Thereafter, a step of forming an inorganic thin film, a step of patterning the inorganic thin film, a step of vertically processing the organic member using the pattern of the inorganic thin film as an etching mask, and etching the processed organic member. A method for manufacturing an optical semiconductor device, which includes the step of forming end surfaces such as a light emitting surface and a light receiving surface on the stepped portion of the substrate using a mask.