JPH04278988A - Display driving circuit for display panel - Google Patents

Abstract

PURPOSE:To prevent unsightly abnormal display on a display panel even at the time of receiving a display permission signal before sufficient rise of the voltage after the start of power supply to a display driving circuit. CONSTITUTION:A voltage detecting circuit 60 detects the rise of the supply voltage to generate a voltage detection signal, and the status signal of a status storage circuit is set to one logical state in the case of the absence of the voltage detection signal state to invalidate the display permission signal; and when an output command is received after charging a display driving circuit 50 with display data, the status signal is switched to the other logical state on the condition that the voltage detection signal exists, and then, the display permission signal is validated.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention is a display drive circuit for a display panel such as a liquid crystal type or a plasma type. This relates to output based on output commands issued to

0002

2. Description of the Related Art As is well known, in a display panel, a display voltage is applied to a large number of pixels through scanning lines and data lines to perform display, and display data to be carried on all data lines is sent to a display drive circuit. After loading is completed, pixels for one scanning line are displayed simultaneously.

[0003] For this reason, a display drive circuit for a display panel includes a shift register having a number of stages that can sequentially load display data for a large number of pixels for one scanning line, and a latch circuit having a number of latches corresponding to this number of stages. After loading the display data into this shift register, a latch command is given to the latch circuit as an output command, and the display data loaded in the corresponding stage of the shift register is loaded into the latch all at once. Corresponding display voltages are placed on many data lines all at once. FIG. 3 shows a conventional example of a display drive circuit that performs such an operation.

The display panel 1 is schematically shown in the upper right corner of FIG. 3, and each intersection of a data line 1a and a scanning line 1b, shown one by one in the figure, is a pixel 2. many data lines 1
A plurality of display drive circuits 50 for a are usually provided,
Each of them is responsible for, for example, 64 to 128 data lines. A display drive circuit 51 is similarly provided for the scanning line 1b. The figure shows a display drive circuit 5 for the data line 1a.
0, which includes, in addition to the shift register 10 and latch circuit 20 described above, for example, a pre-drive circuit 30 and an output circuit 40 as shown in the figure.

The shift register 10 sequentially reads the display data DD received at the first stage into its n stages in synchronization with the shift pulse SP, and also transmits this to the shift register in the adjacent display drive circuit 50. The latch circuit 20 consists of n latches, and receives the output command LS issued after the display data DD is loaded into the shift register 10 of all the display drive circuits 50 as a latch command, and loads the shift register 10 into each latch. The display data DD loaded in the corresponding stage is read and output to the front drive circuit 30. The front drive circuit 30 also consists of n parallel circuits, and is a logic gate that has a level shift function for converting low-voltage display data DD into a drive signal suitable for the display voltage and a function for opening and closing the drive signal according to the frame signal FS, etc. Consists of etc. The output circuit 40 which receives the drive signal from now on also consists of n parallel circuits, and selects display voltages from V1 to V4 in the example shown in the figure according to the content of the display data DD represented by the drive signal, and outputs it to the output terminal 50a.
The output transistor circuit is mounted on the data line 1a of the display panel 1 via the output transistor circuit.

Now, since it is necessary to be able to start and stop the display at any time, such as when switching the display of characters and images on the display panel 1, the above-mentioned display drive circuit 50 is always supplied with a display permission signal DS. The display state can be specified by specifying the display state, and the display can be stopped immediately by disappearing it when necessary. In the example of FIG. 3, this display permission signal DS is given to the front drive circuit 30, and when it disappears, the front drive circuit 30 immediately stops supplying the drive signal representing the display data DD to the output circuit 40 using its logic gate. As a result, the output circuit 40 fixes the display voltage applied to the data line 1a to, for example, V1. This display permission signal DS is also given to the display drive circuit 51 for the scanning line 1b, and when it disappears, the display voltage or scanning voltage applied to the scanning line 1b is fixed at the same V1.
No voltage is applied to the pixel 2, and the display stops.

[0007]

However, in the above-mentioned conventional display drive circuit, if the display permission signal DS is applied immediately at startup or power supply starts, an abnormal display appears on the screen of the display panel, making it very unsightly. be. This is because the voltage generated by the stabilized power supply for the display drive circuit does not rise immediately upon startup, and during the rise, although it is within a short time, the operating state of the internal circuits 10 to 40 of the display drive circuit 50 becomes unstable. This is because stable, so to speak, random display voltages are applied to the data lines 1a and scanning lines 1b of the display panel 1. In particular, linear random display looks strange and is very unsightly.

[0008] For this reason, conventionally, the electronic circuit that provides signals and commands to the display drive circuit outputs the display permission signal after a certain timing after startup.
If this timing is set sufficiently for safety, the start of display will be delayed. This problem can be solved by issuing the display permission signal after confirming the rise of the power supply voltage on the electronic circuit side, but since the operation of the electronic circuit side is unstable when power supply starts, the display permission signal may be used to drive the display by mistake. The danger to the circuit cannot be completely eliminated. Furthermore, power supply is not necessarily started to the electronic circuit side and the display drive circuit side at the same time, and if the electronic circuit side comes first, abnormal display cannot be prevented.

SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and provide a display drive circuit for a display panel in which there is no possibility of abnormal display occurring at startup or when power supply is started.

0010

[Means for Solving the Problems] According to the present invention, this object is to provide a display voltage on a display panel based on an output command issued each time display data is loaded under the condition that a display permission signal is received as described at the beginning. For the drive circuit that outputs a A state memory circuit is provided that emits a state signal that switches to the other logic state when the logic state is entered and an output command is received under the condition that a voltage detection signal is present, and the display is displayed while this state signal is in one logic state. This is achieved by prohibiting the output of the display voltage to the display panel, giving priority to the permission signal.

It is preferable to use a latch command given to the latch circuit in the display drive circuit as the output command in the above configuration, and it is most preferable to use a flip-flop as the state storage circuit.

[0012] Furthermore, in order to inhibit output of the display voltage to the display panel in preference to the display permission signal when the state signal of the state storage circuit is in one of the logical states, a display permission suppression circuit is provided so that the display is not normally displayed. Advantageously, the enable signal is disabled and the display enable signal is enabled only when the state signal by the state storage circuit is in the other logic state. This display permission suppression circuit can be configured with a logic gate, but in order to ensure its suppressing effect, it needs to be equipped with a resistor that drops the display permission signal to the ground potential point and disables it at all times, and a resistor that receives the state signal of the state storage circuit and suppresses it. It is particularly advantageous to construct this by a series circuit with a transistor which turns on in the other logic state and produces a display enable signal.

Furthermore, in order to prohibit the output of the display voltage to the display drive circuit, the most reliable method is to cut off the supply of the display voltage to the display drive circuit.

[0014]

[Operation] In the present invention, as described in the configuration in the previous section, a voltage detection circuit is first built into the display drive circuit to detect the rise of the power supply voltage at the start of power supply and generate a voltage detection signal, and a state storage circuit is provided. By generating a state signal that enters one of the logic states when there is no voltage detection signal yet, and as long as one of the logic states of this state signal continues, this is given priority over the display permission signal and output of the display voltage is prohibited. , to prevent abnormal display from being displayed on the display panel under conditions where the circuit cannot yet operate normally. Further, in the present invention, by utilizing the fact that the output command is generated after the display drive circuit operates normally and display data is loaded, the state memory circuit By switching the state signal of one to the other logic state, the display drive circuit is placed into a normal operating state.

Note that even if the circuit parts in the display drive circuit are initially in a random state after the power supply voltage rises,
Upon initial loading of the display data and upon switching the state signal to the other logic state and outputting the display voltage based on the output command, the normal state specified by the display data is reliably corrected. Also, after the status signal changes to the other logic state, the display permission signal will take priority unless the voltage detection signal disappears and changes to one logic state, so the display permission signal will not be displayed on the display panel. The display can be started and stopped at any time and at will using this display permission signal.

[0016]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 illustrates a display drive circuit 50 according to the present invention together with its power supply 90 for convenience of explanation, and FIG. 2 shows waveforms of main signals therein, which correspond to FIG. 3 of these figures. Since the parts are given the same reference numerals, a description of the overlapping parts will be omitted. In the embodiment described below, it is assumed that the display drive circuit 50 is used for driving the data line side of a liquid crystal display panel, but the present invention is also applicable to other types of display panels and for driving the scanning line side. This can of course be implemented by suitably adapting the circuit.

In the lower half of FIG. 1, the shift register 10, latch circuit 20, pre-drive circuit 30, and output circuit 40 already explained in FIG. front drive circuit 30 and output circuit 40 with deep
, the contents of the unit circuit are shown. Circuits specific to the present invention are a voltage detection circuit 60, a state storage circuit 70, and a display permission suppression circuit 80, which are shown respectively surrounded by dashed lines in the upper half of FIG. The power supply 90 for the display drive circuit 50 shown on the right side is commonly used for the display voltages V1 to V4 for the display panel, including the low voltage Vd and negative voltage Vn for ordinary MOS circuits, and is used for the shift register 10, latch circuit 20, and voltage detection. The low voltage Vd is supplied to the circuit 60, the state storage circuit 70, and the display permission/suppression circuit 80, and the display voltages V1 to V4 or a part thereof are supplied to the pre-drive circuit 30 and the output circuit 40. It is assumed that the display voltages V1 and V4 are the same as the low voltage Vd and the negative voltage Vn, respectively.

The voltage detection circuit 60 detects a low power supply voltage Vd.
, and a series circuit including a resistor 63 and a transistor 64.
When the gate of the transistor 64 receives a voltage obtained by dividing the power supply voltage Vd between the resistors 61 and 62 and exceeds a predetermined value, the transistor 64 turns on and grounds the resistor 63. The voltage detection signal A derived from the inverter 65 is brought to a high state. Therefore, the power supply voltage Vd rises within the startup time Tr after the power supply start time t0 shown in FIG.
b) The voltage detection signal A of the voltage detection circuit 60 as shown in
goes from low to high. As shown in FIG. 1, this voltage detection signal A is given to the state storage circuit 70, but it is also given to an electronic circuit (not shown) that gives display data DD, output command LS, etc. to the display drive circuit 50, and based on it, the display data D
It is desirable to start the loading operation of D.

The state storage circuit 70 is constructed, for example, by a flip-flop combining two NAND gates 71 and 72 as shown in the figure.
The NAND gate 71 receives the complementary signal B of the output command LS through the NAND gate 71 and outputs the status signal C. Figure 2 (
(c) and (d) of the same figure show the waveforms of these complementary signals B and status signals C, respectively.

State storage circuit 70 within startup time Ts in FIG.
Explain the operation. Since the output command LS within this time Ts is of course low, its complementary signal B rises to high as shown in the figure (c), but the voltage detection signal A shown in the figure (b) received by the NAND gate 71 does not reach time t1. Since it is completely low, it has priority over the complementary signal B which is rising to high and is received by the NAND gate 72, and the state storage circuit 70
The flip-flop for
One logic state is established high in this embodiment as shown in FIG. This state is maintained during the waiting time Tw shown in FIG. 2 until the output command LS arrives.

The display permission suppression circuit 80 is for giving priority to the display permission signal DS when the state signal C is in one of these logical states.
It is composed of a p-channel type MOS transistor 81 that receives d, and a series resistor 82, and receives a status signal C at the gate of the transistor 81, and a display enable signal DS at the interconnection point between the transistor 81 and the resistor 82, and also receives the display enable signal DS at the interconnection point between the transistor 81 and the resistor 82. An internal display permission signal D is derived from the input signal D and is applied to the switch circuit 30a attached to the front drive circuit 30. The value of the series resistor 82 is preferably selected to be sufficiently higher than the on-resistance of the transistor 81, for example, four times or more.

Display permission suppression circuit 8 configured as described above
0, the transistor 8 during the start-up time Ts in FIG.
Since the state signal C rises considerably high while the power supply voltage Vd rises to the extent that the transistor 81 becomes operable, the transistor 81 remains off for this startup time T without turning on.
s and the subsequent waiting time Tw. Therefore, even if the display permission signal DS reaches a high level within this time, it is suppressed by the resistor 82 and the internal display permission signal D is outputted as a low level as shown in FIG. 2(e). When this internal display permission signal D is low, the front drive circuit 3
In the example shown in FIG. 0, the switch circuit 30a that supplies display voltages V1 and V3 is not turned on, so the front drive circuit 30 cannot operate at all, and therefore the display on the display panel is based on the display permission signal DS.
be placed in a prohibited state regardless of the presence or absence of As described above, in the present invention, the display permission signal DS is invalidated and display is prohibited by placing the state signal C in one logic state during the activation time Ts and the waiting time Tw.

During the above-described waiting time Tw, the display drive circuit 5
When the end command LS arrives after the display data DD has been loaded into the zero shift register 10, its complementary signal B becomes low as shown in FIG. 2(c). At this time, the voltage detection signal A received by the NAND gate 71 of the state memory circuit 70 is high as shown in FIG. Then, the state signal C is switched from high to low as shown in FIG. 2(d). As a result, the transistor 8 of the display permission suppression circuit 80
1 is turned on, the potential at the interconnection point with the series resistor 82 is raised to the power supply voltage Vd, and the internal display enable signal D is made high.

[0024] As a result, the display permission signal DS, which had been disabled until then, is enabled, or the first output command L
The display permission signal given with S is accepted,
When the internal display permission signal D goes high, the switch circuit 30a is turned on, and the display operation of the display drive circuit 50 is normally started. From then on, each time the output command LS after loading new display data DD causes the complementary signal to go low as shown in FIG. Display based on the updated display data DD is performed while sequentially sending the scanning lines 1b. Td in FIG. 2 indicates the display operation time for one scanning line. While this display operation is repeated, the status signal C remains low and the internal display permission signal D remains high.If the display permission signal DS is made low during this period, of course only the internal display permission signal D becomes low. Therefore, the display can be interrupted or stopped at any time.

In connection with the above-mentioned operation of the circuit of the present invention, finally, the configuration and operation of the pre-drive circuit 30 and the output circuit 40 will be briefly explained for reference. The output circuit 40 is connected to the power supply 90 to 4
The display voltages V1 to V4 of the seeds are respectively received from four drive signals according to display data from corresponding unit circuits of the front drive circuit 30, and any of the four transistors 41 to 44 is connected to the front drive circuit 30. They are selectively turned on in response to drive signals received at their gates, and as can be easily seen from the figure, any one of the display voltages V1 to V4 is outputted from the output terminal 50a to the display panel.

The pre-drive circuit 30 has a level shift function of converting the display data DD received from the latch circuit 20 into a drive signal at a potential level suitable for each display voltage, and a frame drive signal that corresponds to the content of the display data DD. It has the function of generating electricity while switching according to the signal FS, and each unit circuit includes four transistors 41 to 41 of the output circuit 40.
Four logic gates 31 to 34 respectively corresponding to 44 are provided. These logic gates receive the complementary signal of the frame signal FS via the inverter 30b, the display voltages V1 and V3 in this example, the display data DD, and the complementary data via the inverter 35, as shown in the figure, for example. In this example, output circuit 40 operates on voltage V4.
A drive signal is issued to transistors 41 to 44, respectively. A detailed explanation of its operation will be omitted since it would be complicated.

[0027]

[Effects of the Invention] As explained above, in the present invention, power supply is started to a drive circuit that outputs a display voltage to a display panel based on an output command issued each time display data is loaded under the condition that a display permission signal is received. A voltage detection circuit that detects the rise of voltage in the power supply circuit and issues a voltage detection signal, and a voltage detection circuit that receives the voltage detection signal and output command and enters one logic state with no voltage detection signal, and a voltage detection circuit that generates a voltage detection signal. and a state memory circuit that emits a state signal that switches to the other logic state when an output command is received under the conditions of , and while the state signal is in one logic state, the display panel of the display voltage is given priority over the display permission signal. By prohibiting output to , the following effects can be achieved.

(a) Even if a display permission signal is received at startup or when the power supply voltage rises after power supply starts, the state signal of the state storage circuit changes to one logic state while there is no voltage detection signal from the voltage detection circuit yet. Since the display permission signal is invalidated with priority over the display permission signal, it is possible to reliably prevent unsightly abnormal displays from appearing on the display panel.

(b) It is no longer necessary for the user side of the display drive circuit to delay the timing of the display permission signal or to issue the display permission signal after detecting the rise of the power supply voltage, greatly reducing the burden on the user. can do.

(c) Conventionally, there has been no effective means for preventing abnormal display when the power supply start timing differs between the display drive circuit side and the user side, or when an erroneous power supply permission signal is received due to a malfunction on the user side. However, the present invention makes it possible to reliably prevent this.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a display drive circuit for a display panel according to the present invention.

2 is a waveform diagram showing main signals related to the operation of the embodiment shown in FIG. 1, shown in FIGS.

FIG. 3 is a block circuit diagram showing an outline of a conventional display drive circuit.

[Explanation of symbols]

1 Display panel 50 Display drive circuit 60 Voltage detection circuit 70 State storage circuit or flip-flop 80 Display permission suppression circuit A Voltage detection signal C Status signal DD Display data DS Display permission signal LS Output command Ts Power supply voltage rise time or startup time Vd Power supply voltage V1 Display voltage V2 Display voltage V3 Display voltage V4 Display voltage

Claims (3)

[Claims] 1. A drive circuit that outputs a display voltage to a display panel based on an output command issued each time display data is loaded under conditions in which a display permission signal is received, the voltage of a power supply circuit at the time of starting power supply. A voltage detection circuit detects the rising edge of the voltage and issues a voltage detection signal, and upon receiving the voltage detection signal and output command, enters one logic state with no voltage detection signal, and issues an output command with the voltage detection signal present. and a state memory circuit that emits a state signal that switches to the other logic state when received, and while this state signal is in one logic state, it takes priority over the display permission signal and prohibits output of the display voltage to the display panel. A display drive circuit for a display panel, characterized in that: 2. The circuit according to claim 1, wherein the display permission signal is normally disabled and the display permission signal is enabled only when the state signal from the state storage circuit assumes the other logical state. A display drive circuit for a display panel, comprising a circuit. 3. The circuit according to claim 1, wherein output of the display voltage to the display panel is prohibited by cutting off the supply of the display voltage to the display drive circuit. Display drive circuit.