JPH0348889A - Scanning circuit for display panel device - Google Patents

Abstract

PURPOSE:To prevent the latch-up caused by an induction pulse from a data line by constituting each stage of a shift register so that its stage output is set automatically to a non-selective logical state at the time of turning on a power source and setting a scanning signal voltage immediately after turning on the power source to the intermediate potential. CONSTITUTION:A shift register 10 receives data D by its input Di, and sends it to a shift register of the next scanning circuit from an output Do, while advancing this data by one stage each by a clock pulse CP. Subsequently, when a power source is turned on, all stage outputs of the shift register 10 in a scanning circuit 100 are set automatically to a non-selective state, and scanning signals SV outputted to a scanning line 3 of a display panel 1 from the circuit 100 are all set to the intermediate potentials V1 - V2. Accordingly, even if a pulse is induced to the scanning line 3 through a capacitance of a picture element 2 from a data line 4, it does not exceed power source potentials Vd, Ve. In such a way, the scanning circuit 100 is protected effectively from danger of latch-up.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a scanning circuit for a display panel device using a liquid crystal or the like;
That is, the present invention relates to a circuit for driving a scanning line for causing pixels arranged in a predetermined direction on a display panel to perform simultaneous display.

[Conventional technology]

As is well known, in large liquid crystal display panels for displaying variable images such as those for televisions, a large number of pixels are arranged in a matrix on the panel surface, and scanning lines are arranged orthogonally to each other so that each pixel can be identified by its intersection. and data lines are provided, but 1
When periodically updating the display content of one frame's worth of images, the scanning lines are sequentially driven and each pixel lined up along the scanning line is caused to simultaneously perform a display according to the display data on the corresponding data line. The present invention relates to a scanning circuit for driving one of these scanning lines.

This scanning circuit incorporates a shift register for sequentially specifying the scanning lines to be driven, and while driving this shift register with a clock pulse, sequentially sets the output of each stage to a selected logic state 1, for example, a state of radiance. , thereby driving the scanning line by placing the drive output voltage for the specified scanning line at or near one of the pair of power supply potentials for driving the display panel. This procedure will be explained with reference to FIGS. 4 and 5.

A large number of pixels 2 are arranged in a matrix within the display panel, a portion of which is shown in FIG. For example, 400 scanning lines 3 are provided for the pixels arranged in the horizontal direction, and 640 data lines 4 are provided for the pixels arranged in the vertical direction. Several to ten or more scanning circuits 100 are provided to drive several tens of scanning lines 3, and the data t is
For Is4, data circuit 2 that drives several tens of wires similarly.
Approximately several 00's are provided.

Shift register 10 built into each scanning circuit 100
are connected in series with each other as shown in the figure, and the clock pulse CP
Accordingly, data D is sent one stage at a time among these plurality of shift registers 10. This data D is shown in Figure 5 (al
Since the frame signal FS shown in FIG. Each time the data of this single selection logic state is sent one step at a time by the shift pulse CP, one scanning line 3 is designated.

Each scanning circuit 100 has a pair of electric potentials Vd and Ve for driving the display panel, and an intermediate electric potential V1. V2
is given, and a scanning signal SV having a waveform illustrated in FIG.

Since the scanning signal Sv in this example drives the display panel 1 with AC, the central potential V between the ms potential νd and Ve as shown in the figure.
Φ) in FIG.
shows the waveform of the scanning signal SV3 to the knot register 10.
For example, when the stage output of the 03rd stage is in one selected logic state, it takes the potential Ve or Vd, and takes the potential ν1 or v2 during the remaining period when the stage output is in the non-selected logic state of L.

On the other hand, the data signal Dv output from the data circuit 200 to an arbitrary data line 4 has a waveform shown in FIG. are the same, but the intermediate potential ν3 . It has a waveform that takes v4 or voltage level vd+Vs.

In addition, between the above-mentioned potentials, Vd>Vl>Vm>V2>Ve
and Vd>V3>ν->V4>Ve, and normally Vl>V3. It is assumed that ν2 × v4.

The data signal OV is of course switched in synchronization with the scanning signal SV, for example, as shown by the arrow in FIG.
When the third scanning signal SV3 reaches the potential V@ according to the selection logic state of the shift register, correspondingly, the third scanning signal SV3 becomes the potential V@.
When a certain data signal OV switched for the second time is at the power supply potential νd as shown in the figure, a display is made on the corresponding pixel,
When the potential is at the intermediate potential v3, no display is performed on the corresponding pixel.

In other words, the frame signal PS of FIG.
After switching to the third scanning signal S in the same figure (g))
When the potential of V3 becomes We or Vd, a large number of data signals Dv as shown in CC) in the same figure, which are switched for the third time, change to 1f source potential Vd or Vd depending on the display data, respectively. at vO or at intermediate potential v3 or v4
The display determined by the number of pixels is displayed simultaneously on a large number of pixels lined up along the third scanning line 3.

[Problem to be Solved by the Invention] The above-mentioned scanning circuit is integrated into a CMOS integrated circuit, for example, so that one circuit can drive several dozen scanning lines as described above, but it operates by so-called latch-up when the IT power is turned on. A problem that occurs may occur. As a result of investigation, it was found that the cause of this problem is that the stage output of the shift register in the scanning circuit tends to become unstable when input is turned on.

That is, during normal operation of the shift register, only the output of one stage takes the selection logic state as described above, and correspondingly, the scanning signal from the scanning circuit is as shown in FIG. 5 (b). The power supply potential νd or Ve is taken for a very short period of time, and the intermediate potential V1 or v2 is taken for most of the remaining time. However, if the operation of the shift register becomes unstable when ta is turned on, the outputs of multiple stages are set to the selection logic at the same time. In the worst case, the outputs of all the stages become the selection logic state at the same time, and the scanning signal Sv is always at the power supply potential νd or Ve as shown in FIG. 5(b). It is possible that there may be cases where .

On the other hand, on the data circuit side, a data signal Dv as shown in FIG.
3 or ν4, the scanning line 3 on which the scanning signal is carried via the capacitance of the pixel 2
induce a pulse. If the scanning signal is normal and is at the intermediate potential Vl to v2 most of the time as shown in FIG. 5(b), this pulse will hardly exceed the power supply potential Vd to Ve, ) If the scanning signal is abnormal, the polarity of the pulse will definitely exceed the power supply potential Vd or ve when the polarity is unfavorable.

The output circuit section of the scanning circuit that generates the scanning signal SV has a CMOS configuration, for example, and as is well known, the pair of p-channel and n-channel field effect transistors has four layers similar to a four-layer thyristor structure. The current flowing in response to the above-mentioned pulse becomes a forward current to the gate of this thyristor structure, making it conductive and causing latch-up.

Note that since a large number of data lines correspond to one scanning line as described above, the above-mentioned pulses are almost certainly induced to the scanning line each time display data is switched. At this time, there are cases where multiple pulses cancel each other out with positive and negative, but
In many cases, these composite pulses remain and cause latch-up if their polarity is unfavorable to the scanning signal in the abnormal state. As can be easily seen, the risk of latch-up increases as display panels become larger and have more pixels, and as the gap between pixel electrodes shrinks to make images clearer, the risk of latch-up increases. The larger the capacitance, the more serious the problem becomes.

In order to reduce the risk of latch-up, it is possible to increase the latch-up resistance by increasing the size of the transistor in the output circuit section of the scanning circuit, but this does not necessarily solve the problem fundamentally. Moreover, since the size of the transistor pair increases for each scanning line, the chip size of the entire integrated circuit inevitably increases.

Furthermore, it is not impossible to make the scanning signal corresponding to the selection logic state of the stage output of the shift register take an intermediate potential instead of the aforementioned power supply potential, but this does not make the power supply voltage effective for driving the pixel. This would make the integrated circuit structure unnecessarily complicated.

SUMMARY OF THE INVENTION An object of the present invention is to solve this problem and provide a scanning circuit for a display panel device that is free from the risk of launch-up occurring when the power is turned on.

(Means for Solving the Problems) As described above, the present invention includes a shift register for specifying the scanning line by the output of each stage, and the scanning line is specified by the selection logic state of the stage output of the shift register, for example, h. In a scanning circuit that drives a scanning line by placing the drive output voltage for the scanning line near one of a pair of driving power supply potentials, when each stage of the shift register is powered on, the output of that stage is, for example, − The above object is achieved by configuring the device to be automatically set to a non-selected logical state.

The automatic setting of the output of each stage of the shift register to the non-selected logic state when the power is turned on in the above configuration is, for example, the source and
This can be done by making the resistances between the drains different from each other.

Note that even if each stage of the shift register is automatically set to a non-selected logic state when the power is first turned on as shown above, undefined data may be given to the shift register afterwards, or parts other than the shift register in the scanning circuit may There is a risk that the device may malfunction or enter an abnormal operating state due to an undefined signal from the outside, so in addition to the above configuration, the A periodic pulse instead of a clock pulse can be used to input data into the shift register by inhibiting data input to the shift register, or by creating temporary data in the scanning circuit that instead places only a single stage in a selected logic state. By sequentially advancing this temporary data, it is possible to eliminate the risk of latch-up occurring within a predetermined short time after power is turned on.

[Effect]

As can be seen from the above configuration, the present invention automatically sets each stage of the shift register immediately after power is turned on so that the output of that stage becomes a non-selected logic state, thereby scanning all the scanning signals output from the scanning circuit. The line drive voltage is placed at the aforementioned intermediate potential corresponding to the non-selected state, so that even if a pulse is generated on the scan line due to induction from the data line side, it will not exceed the power supply potential, thus preventing latch-up in the scan circuit. This eliminates the risk of this occurring.

〔Example〕

The present invention will be described in detail with reference to the figures.

FIG. 1 shows an embodiment of a scanning circuit according to the present invention, and the same parts as in FIG. 4 are given the same reference numerals.

FIG. 1(a) shows the internal structure of a display panel 1 and a scanning circuit 100 in a different orientation from FIG. In the scanning circuit 100 carrying the SV, an n-stage shift register 10, n logic circuits 20, and n output circuits 30 are provided.

The shift register 10 receives data D at its input DI,
As usual, this data is advanced one stage at a time by the clock pulse CP and sent from the output Do to the shift register of the next scanning circuit, and depending on the content of the data D, only the output of that one stage is always output as described above. Placed in selection logic state. Hereinafter, in this embodiment, it is assumed that the selected logical state is specified by the logical state of h as usual.

Each logic circuit 20 receives the corresponding stage output from the shift register IO and the frame signal FS having the waveform shown in FIG.
Four signals corresponding to four combinations of % and 'Ll are given to the corresponding output circuits 30.

The output circuit 30 is usually a high-voltage circuit, and includes, for example, four high-voltage transistor switches that receive the aforementioned power supply potentials Vd and Ve and intermediate potentials v1 and v2, respectively. By selecting and outputting one of these four potentials according to the signal,
A scanning signal SV having a waveform as shown in FIG. 5('b) is generated.

An example of the configuration of each stage of the shift register 10 is shown in FIG. Both inverters 11a and 11b and transmitter gate l are connected as shown in the figure.
lc and lld, and as is well known, the transmission gate llc is activated by the clock pulse CP.
While opening and closing the and lid alternately, for example, at the falling edge of clock pulse CP, the old input data from the previous stage on the left side of the diagram is read into the master circuit section, and at the rising edge of clock pulse CP, it is transferred to the slave circuit section. , is provided as output data Do to the next stage on the right side of the figure, and at the same time is outputted as the output of that stage to the corresponding logic circuit 20 on the upper side of the figure.

In the present invention, as described above, in order to automatically set the output of each stage circuit 11 to the non-selected logic state which is t in this embodiment when the power is turned on, for example, the inverter lla is set as shown in FIG. C) Or configured as shown in FIG. 1(d).

FIG. 1 (in the configuration example of the inverter lla of C1, p-channel and n-channel field effect transistors 12P and 12n are connected in series between a pair of tillI potential points vd and ve, and have a common gate connected to receive an input signal si). have different source-drain resistances.

In this example, the source-drain resistance of the n-channel field-effect transistor 12n is set to be sufficiently lower than that of the p-channel field-effect transistor 12p, for example, 1/3, so that when the power supply potential vd rises immediately after power-on, both field-effect transistors The output signal So derived from the interconnection point is forced to the power supply potential ve of the low resistance n-channel field effect transistor 12n side, that is, the t side.

In the stage circuit 11 of FIG. 1~) in which such an inverter lla is incorporated, when the power supply potential V6 rises after the power is turned on, the memory state of - is set in the inverter lla and inverter llb that output this t in the slave circuit section. is established, and a known storage state is likewise established in its master circuitry, so that its stage output is automatically set to the negative logic state.

In the configuration example of the inverter lla shown in FIG. A capacitor 13 is connected to the capacitor 13. Since this capacitor 13 is of course discharged before the power is turned on, when the power supply potential vd rises, the output signal SO is forced to the power supply potential Ve side, that is, to the t side, and as in the above, this inverter The stage circuit 11 incorporating lla is automatically set to a negative stage output when the power is turned on.By connecting such a capacitor 13, the stage circuit 1
Fortunately, the shift register 10 for the scanning circuit does not require very high speed operation.

As can be easily seen from the above, the stage circuit 11 when the power is turned on
For automatic setting to -, set the source-drain resistance of the P-channel field-effect transistor 12p of the inverter llb higher than the n-channel field-effect transistor 12n, or connect the capacitor 13 in parallel to the p-channel field-effect transistor 12p side. You can also do that.

In the embodiment shown in FIG. 1 configured as described above, when the power is turned on, all the stage outputs of the shift register IO in the scanning circuit 100 are automatically set to the non-selected state t'', and the scanning circuit 100 Since the scanning signals SV output to the scanning lines 3 of the display panel 1 are all placed at intermediate potentials Vl to v2, even if a pulse is induced from the data line 4 to the scanning line 3 via the capacitance of the pixel 2, it is not connected to the power source. Potential Vd
or Ve, thereby effectively protecting the scanning circuit 100 from the risk of latch-up.

Fig. 2 shows an embodiment in which the scanning circuit is protected from the risk of latch-up not only immediately after power is turned on, but also for a short period of time until the data, clock pulses, frame signals, etc. received by the scanning circuit are established. Waveforms of signals related to are shown. However, in FIG. 2, only the portion related to the shift register 10 in the scanning circuit 100 is extracted and shown, and each stage circuit 11 is configured as shown in FIG. It is assumed that the output of that stage is automatically set to a - non-selected state immediately after the power is turned on.

In this embodiment, AND gates 14a and 14b and an OR gate 14C are connected to the input O1 side of the shift register 10 in order to inhibit data D that has not yet been established after power is turned on within a short period of time. AND gates 15a and 15b and an OR gate 15C are provided to inhibit pulse CP within a short period of time.

Furthermore, in this example, in order to evaluate the establishment of the signal received by the scanning circuit, the frame signal FS is used as a representative and is used within a short period of time instead of the clock pulse CP. clock pulse CP
is applied to one input of AND gate L5b, and frame signal FS is applied to one input of AND gate L5b. Instead of the data D, the starting data Ds taken from the complementary Q output of the flip-flop 16 is used within a short time, so that the data D is of the AND gate 14a, and the starting data D3 is of the AND gate. 14b. To control these AND gates, a control signal Se, which is the Q output of another flip-flop 17, is used.
is used.

Both frimb flops 16 and 17 both have their D
The trigger input T
As shown in the figure, the first stage output of the shift register 10 and, in this example, the final stage output are respectively applied to the shift register 10.

Immediately after the power is turned on, the stage outputs of the shift register 10 are all b as described above, so the flip-flop 17 is in the reset state, and therefore the control signal Se is in the state t at this time ts as shown in FIG. 3(b). , whereby AND gates 14a and 15a are in a disabled state,
The input of data D and clock pulse CP is prohibited.
Conversely, AND gates 14b and 15b are connected to inverter 17.
It is enabled by the knowledge of the complementary signal of the control signal Se via a. At this time, the frisible flop 16 is of course in the reset state, so the starting data 03 is as shown in FIG.
As shown in C), at this time ts, the state of b is met,
It is applied to the input of the shift register 10 via the AND gate 14b and the OR gate 14c.

In this state, when the frame signal FS is applied as shown in FIG. 3(a), the AND gate 15b and the OR gate 15
This is applied to the shift register 10 as a clock pulse CPI via C, and the - of the starting data D3 applied to its input port 1 is read into the first stage at the rise of the frame signal FS, and the output of that stage becomes b. The flip-flop 16 receiving the trigger input T is set, and the starting data Ds becomes the state b as shown in FIG. 3(C).

Thereafter, each time the frame signal FS is issued, the selection logic state of 1 in the first stage is sequentially transmitted to the next stage and subsequent stages. Frame signal P
S becomes n[1J1N(,) at time t in FIG.

When this selection logic state reaches the final stage of the shift register 10, the output of that stage causes the flip-flop 17 to be activated.
is triggered and set, and the control signal Sθ goes to t, disabling AND gates 14b and 15b and simultaneously enabling AND gates 14a and 15a instead to receive data D and clock pulse CP into shift register 10. moves to the normal state where it enters.

As you will see, in this embodiment, time t in FIG.
During the time T from 3 to te, the outputs of each stage of the shift register 10 are sequentially set to the selected logic state one by one. Even if it is in an abnormal state due to a disturbed input from the outside, etc., it will be corrected to a normal state one by one, and after confirming that the input signal has been established by the frame signal FS arriving a predetermined number of times, the scanning circuit will The receiver is transferred to the normal operating state.

Therefore, in this embodiment, the risk of latch-up can be prevented by almost certainly placing the scanning circuit in a normal operating state throughout the time period T from immediately after the power is turned on until the establishment of the input signal is confirmed. Note that when the frequency of the frame signal PS is 607 as usual, shift register 1
If there are several tens of stages of 0, the above-mentioned time T will be around 1 second. For the clock pulse CPI given to the shift register 10 within this time T, not only the frame signal FS but also other signals can of course be used as appropriate.

The present invention is not limited to the embodiments described above, and the present invention can be implemented in various embodiments. In this embodiment, as a means for automatically setting the output of each stage of the shift register to a non-selected logic state when the power is turned on, the stage circuit is a master-slave type CMO.
In the case of three circuits, the resistance between the source and drain of the pair of complementary transistors for the inverter was made different, or a capacitor was connected in parallel to one of the transistors, but in addition, appropriate measures were taken depending on the circuit system, type of circuit elements, etc. You can take it.

〔Effect of the invention〕

As described above, in the present invention, a shift register is used for a scanning circuit that drives a scanning line by placing the voltage of a scanning signal sequentially specified by the selection logic state of the stage output of a shift register at one of a pair of power supply potentials. By configuring each stage so that the output of that stage is automatically set to a non-selected logic state when the power is turned on, all the scanning signal voltages immediately after the power is turned on are placed at an intermediate potential, and the scanning circuit uses induced pulses from the data line. latch-up can be effectively prevented.

Furthermore, it is possible to inhibit the input of signals to the shift register or to select only a single stage of the shift register within the scan circuit during the time immediately after power-up until the input signal to the scan circuit is established. By creating temporary data to be placed in the scanning circuit and advancing it sequentially using periodic pulses, abnormal operating conditions due to unforeseen causes in the scanning circuit can be corrected, and latch-up of the scanning circuit during this time can also be prevented. , it is possible to completely eliminate the risk of non-operation, malfunction or damage caused by this.

As described above, according to the present invention, an integrated circuit bag for increasing the latch-up resistance of the output circuit section of the scanning circuit is provided! It is possible to fundamentally solve the conventional problems without increasing the chip size, and in the future, display panels will become larger and larger, or the gap between the electrodes of the pixels will be reduced, and pulses will be induced in the scanning line. Even if it becomes easier to use, we can provide a highly integrated scanning circuit with a small chip size at low cost.
This can contribute to the further development and spread of display panel devices.

[Brief explanation of drawings]

1 to 5(C) relate to the present invention, FIG. 1 is a circuit diagram of an embodiment of a scanning circuit for a display panel device according to the present invention, and FIG. 2 is a circuit diagram of a main part of a different embodiment of the present invention. Figure, 3rd
The figure is a waveform diagram of main signals related thereto, FIG. 4 is an overall circuit diagram of the display panel device, and FIGS. 5(a) to (C) are waveform diagrams of minor signals related thereto. FIG. 5(d) is a waveform diagram of the scanning signal when all the stage outputs of the shift register are in the selection logic state in the conventional circuit. : data line, 10+ shift register, 0+ shift register stage circuit, lla, llb; inverter, llc, lid
: transmincing gate, 12P+P channel field effect transistor, 12n+n channel field effect transistor, 13+capacitor, 14a, 14b
:And gate, 14c+or gate, 15a, 15
b: AND GATE, 15c; OR GATE, 16.17
i flip-flop, 17a; inverter, 20: logic circuit in scanning circuit, 30; output circuit in scanning circuit, 1
00: Scanning circuit, 200: Data circuit, CP, CPI
+clock pulse, D: data, old: data input terminal,
DO: data output terminal, Ds: starting data, Dv: data signal, Se2 control signal, SL: inverter input signal, SO: inverter output signal, SV, SV3 j scanning signal, T: time, ts, te: Time, Vd, C e: High voltage power supply potential for display, vsX center potential, Vl ~ C42 Nakasen potential, Vd, C e: Fig. 3 Fig. 1

Claims (1)

[Claims] A scanning circuit for sequentially driving scanning lines to cause pixels arranged in a predetermined direction on a display panel to display images all at once, and equipped with a shift register for specifying the scanning line by the output of each stage. In a device in which the scanning line is driven by placing the drive output voltage for the scanning line specified by the selection logic state of the stage output of the register in the vicinity of one of a pair of drive power supply potentials, each of the shift registers 1. A scanning circuit for a display panel device, characterized in that the stage output is automatically set to a non-selected logic state when power is turned on.