JP3482731B2 - LCD driving method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving method,
More specifically, the present invention relates to a liquid crystal driving method for resetting the data display of a liquid crystal panel when the power is turned on or a noise signal is mixed into the power line.

[0002]

2. Description of the Related Art In a conventional liquid crystal driving method, as a reset function for resetting the display of a liquid crystal panel, there is a power-on reset function (hereinafter referred to as POC function) for automatically performing initial setting when power is turned on.

In the POC function, first, as shown in the flowchart of the initial setting shown in FIG. 15, a display clear process for clearing the display on the liquid crystal panel is executed (step S
1), function set processing (interface data length setting, display line number setting, common, segment array setting, etc.) is executed (step S2), and then display on / off
Off control processing (display off setting, cursor off setting, blink off setting, etc.) is executed, and entry mode setting processing (memory address increment (+1)
Setting, display shift / non-setting, etc.) are performed (step S4).

Further, the logic circuit configuration for controlling the POC function is as shown in FIG.
It is composed of OR circuits 3 and 4 and an SR latch circuit 5. In FIG. 16, input terminals A to C and E are signals (FIG. 1) for instructing various functions from an external control unit (not shown).
1 (a) is input, the display terminal ON / OFF command signal (“display ON”, active level 1) is input to the input terminal A, and the display ON / OFF command signal (“display” is input to the input terminal B). OFF ", active level 0), RESET2 signal (hardware reset, active level 0) is input to the input terminal C, and POC signal (active level 1) is input to the input terminal E.

Depending on the input state of each signal input to these input terminals A to C and E, the display ON / OFF control signal (active level) is output from the output terminal H as shown in FIG. : 1 when display is ON, 0 when display is OFF), a reset (initial setting) signal (active level 1) is output from the output terminal I to a liquid crystal panel (not shown) (not shown) to control the display of the liquid crystal panel. It is being appreciated.

[0006]

However, the POC function in such a conventional liquid crystal driving method operates when the power is turned on. However, during normal use, it may be disturbed by a disturbance or the like. Even if a noise signal is mixed in the power supply line, the POC function operates, that is,
A POC signal is output from the output terminal H of the logic circuit,
There has been a problem that the initial setting process of the liquid crystal panel is performed and the display abnormality of the liquid crystal panel occurs. That is,
When the POC function operates due to the influence of noise or the like during normal use and the initial settings are made, abnormal states such as malfunction of display characters, data destruction, malfunction of instructions, etc. occur, and abnormal display of the liquid crystal panel occurs. After that, there was a problem that it would not return to normal operation unless the power was turned on (reset) again.

The object of the present invention is to reduce P due to the influence of noise and the like.
Even if the OC function operates, only the display of the liquid crystal panel is turned off, abnormalities such as malfunctions of display characters are prevented, and the normal display is automatically restored by succeeding writing of some instruction command and data. Is to provide.

[0008]

The invention according to claim 1 is
In the liquid crystal drive method for displaying the liquid crystal panel based on display data and various instruction signals output by the control means after initializing the control means for driving and controlling the liquid crystal panel at the time of power-on, the control means comprises: , Power on state
Power supply that includes a noise detection circuit that detects a noise signal that exceeds the specified value generated in the power supply line
Generates a turn-on detection circuit and a display ON / OFF control signal
Display ON / OFF control signal generator and display clear / reset
Display clear / reset control signal that generates a set control signal
A power-on reset control circuit including a generation unit; display information storage means for holding the display data; and means for outputting the display data held in the display information storage means to the liquid crystal panel for display. , Turn it on
Is detected by the power-on detection circuit.
From the power-on reset control circuit
The display OFF control signal is output as
The display of the channel is stopped and the display is cleared and reset.
Output the control signal to initialize the display information storage means
Then, the display drive of the liquid crystal panel is started, and the liquid crystal panel is driven.
During the display drive of the channel, when the noise detection circuit of the power-on detection circuit detects the noise signal and generates a noise detection signal, the power-on is performed based on the noise detection signal. The instruction signal from the reset control circuit
The display OFF control signal output only to the stops the display of the liquid crystal panel, to maintain the holding state of said display data in said display information storage means, after the display stop of the liquid crystal panel, a predetermined clock signal as Based on the input of the synchronized release signal to the control means,
In the power-on reset control circuit, the display O
The FF control signal is released, and the display O is used as the instruction signal.
An N control signal is output to output the display data held in the display information storage means to the liquid crystal panel,
The feature is that the display is restarted.

Further, in this case, as described in claim 2, the control means, after the display of the liquid crystal panel is stopped,
A table of the liquid crystal panel is displayed based on the release signal input to the control means and the rising or falling of the leading clock of the predetermined clock signal synchronized with the release signal.
It is possible to output the instruction signal for returning the display state, output the display data held in the display information storage means to the liquid crystal panel, and restart the display.

Further, according to a third aspect of the present invention, the control means includes the release signal inputted to the control means after the display of the liquid crystal panel is stopped, and the predetermined clock signal synchronized with the release signal. The display state of the liquid crystal panel is restored based on the Nth rising or falling of
The above-mentioned instruction signal is output and stored in the display information storage means .
It said display data being lifting to output to the liquid crystal panel, it is possible to resume the display.

[0011]

According to the invention described in claim 1, when the power is turned on,
After initializing the control means for driving and controlling the liquid crystal panel,
In a liquid crystal driving method for displaying the liquid crystal panel, based on display data and various instruction signals output by the control means, the control means detects a power-on state.
A noise signal generated on the power line that exceeds a specified value.
Power-on detection circuit with noise detection circuit for detecting
And a display ON / O that generates a display ON / OFF control signal
FF control signal generator and display clear / reset control signal
Equipped with a display clear / reset control signal generator that generates
Power-on reset control circuit and the display data
Display information storage means to be held and the display information storage means
The held display data is output to the liquid crystal panel and displayed.
When the power is turned on, the power is turned on.
When the power is turned on by the detection circuit, the power is turned on.
The display OF as the instruction signal from the reset control circuit
F control signal is output to stop the display of the liquid crystal panel.
And output the display clear / reset control signal.
After initializing the display information storage means by
The display drive is started, and while the liquid crystal panel display is being driven.
Then, when the noise detection circuit of the power-on detection circuit detects a noise signal generated in the power supply line and exceeds the predetermined value to generate a noise detection signal, the power-on reset control circuit is generated based on the noise detection signal. More said finger
Only the display OFF control signal is output as a display signal ,
To stop the display of the liquid crystal panel, wherein to maintain the holding state of the display data in the display information storage unit, after displaying stop of the liquid crystal panel, release signal synchronized with a predetermined clock signal is inputted to the control means Based on this, the display OFF control signal is released and the instruction
As a signal, the display ON control signal is output, the display data held in the display information storage means is output to the liquid crystal panel, and display is resumed.

Therefore, it is possible to prevent the occurrence of a display abnormality at the time of returning from the display erased state due to noise detection, and to automatically return to the normal display, so that it is not necessary to operate the power supply (reset) or the like again. ,
The operation load on the user can be reduced.

According to a second aspect of the present invention, the control means is configured such that, after the display of the liquid crystal panel is stopped, the release signal input to the control means and the predetermined clock synchronized with the release signal. The display state of the liquid crystal panel is determined based on whether the leading clock of the signal rises or falls.
By outputting the instruction signal to be restored , outputting the display data held in the display information storage means to the liquid crystal panel and restarting the display, the display off / stop state at the time of noise detection is automatically released. By shortening the period, it is possible to confirm the display content before the display is erased earlier.

Further, according to the invention described in claim 3, the control means, after the display of the liquid crystal panel is stopped, the release signal inputted to the control means and the predetermined clock synchronized with the release signal. The display state of the liquid crystal panel is restored based on the Nth rising or falling of the signal.
And outputs the instruction signal to the display information storage means .
By outputting the held display data to the liquid crystal panel and restarting the display, the display stopped state at the time of noise detection can be reliably released and the display content can be confirmed promptly.

[0015]

Embodiments of the present invention will be described in detail below with reference to FIGS. (First Embodiment) FIGS. 1 to 5 are views showing a first embodiment of a liquid crystal display device to which the present invention is applied. First, the configuration will be described. FIG. 1 shows a display control unit 1 of the liquid crystal display device of this embodiment.
It is a figure which shows the block structure of 0. In this FIG.
The display controller 10 of the liquid crystal display device includes a power supply block 11,
Display control block 12, interface block 1
3, a display data memory block 14, a data gradation control block 15, a common driver 16, a segment driver 17 and an LCD 19.

The power supply block 11 contains a DC-DC converter, an LCD drive voltage generation circuit, etc., and generates a control voltage and a drive voltage based on a reference voltage supplied from a battery (not shown) or the like. , Display control block 12,
It is supplied to the common driver 16 and the segment driver 17.

The display control block 12 includes a CPU (Ce (Ce) that controls the common driver 16 and the segment driver 17.
ntral processing unit) and the like, and when the liquid crystal display start is instructed after the power is turned on, the common driver 16 and the segment driver 1 based on the system clock signal SCK input from the interface block 13.
As various timing control signals for controlling 7, the common control signal and the segment control signal are generated and output to the common driver 16 and the segment driver 17. Then, the common driver 16 controls the sequential scanning timing of the scanning line for each field in one frame, and the segment driver 17 controls the sampling timing of the driving voltage of the signal line for each field in one frame.

Further, as shown in FIG. 2, the display control block 12 includes a power-on detection circuit 121 and a reset / PO.
The C control circuit 122 is incorporated. Power-on detection circuit 121
Detects the power-on state of the power supply block 11 and sets the POC signal by the power-on detection to reset / P
While outputting to the input terminal E of the OC control circuit 122,
An instruction command is input to the input terminal G from the main control block (not shown) via the interface block 13.
When the data write instruction signal 13c is input, the POC signal is reset.

In the reset / POC control circuit 122, various signals are input to the input terminals A to D and F from a main control block (not shown), and the interface block 13 is input to the input terminals A, B and D. Display ON / OFF command 13a and display clear command 13b are input via
The reset signal RESET2 and the reset signal RESET1 are directly input to the input terminals C and F, and the POC signal is input from the power-on detection circuit 121 to the input terminal E.

The circuit configuration of the reset / POC control circuit 122 is shown in FIG. In FIG. 3, reset / P
The OC control circuit 122 includes inverter circuits 31 to 33, O.
R circuits 34 and 35, SR latch circuits 36 and 37, and AN
The display ON / OFF control signal generation unit 122a configured by the D circuit 38, the inverter circuit 32, and the OR circuit 3
And a display clear / reset control signal generation unit 122b configured by the reference numeral 9.

Further, the reset / POC control circuit 1 shown in FIG.
The relationship between the function of each signal input to the input terminals A to G of 22 and the active level is shown in FIG. 4A, and the relationship between the function of each signal output from the output terminals H and I and the active level is illustrated. 4 (b). In the display ON / OFF control signal generation unit 122a, when the POC signal (active level 1) is input to the input terminal E from the power-on detection circuit 121 of FIG. 2 when the power is turned on, the SR latch circuit 37 outputs “L” level. The signal is output to the AND circuit 38, and the AND
A “display OFF” control signal is output from the circuit 38 to the common driver 16 and the segment driver 17 via the output terminal H.

In the display ON / OFF control signal generation section 122a, when an instruction command and a data establishment signal are input to the input terminal D from a main control block (not shown), the "display OFF" control signal is released. Then, a normal instruction command (data write command, display clear / reset command, etc.) is output to the display data memory block 14, the common driver 16, and the segment driver 17. In addition, in FIG.
Display control block 12 to display data memory block 1
The instruction instruction output to 2 is shown as a memory control signal.

Further, in the display ON / OFF control signal generation section 122a, the "display ON" (active level 1) of the display ON / OFF command is sent to the input terminals A and B from the main control block (not shown) during the normal operation. ) And “Display O
When FF "(active level 0) is input, the" display ON "control signal and the" display OFF "are sent from the SR latch circuit 36 to the common driver 16 and the segment driver 17 via the output terminal H according to the respective input timings. "A control signal is output.

Further, the display ON / OFF control signal generator 1
In 22a, when the reset signal RESET1 (external reset signal, active level 0) is input from the main control block (not shown) to the input terminal F during normal operation, the SR latch circuit 37 outputs the signal via the output terminal H. “Display O” is displayed on the common driver 16 and the segment driver 17.
The FF "control signal is output.

Display clear / reset signal generator 122b
Then, when the reset signal RESET2 (hardware reset signal, active level 0) is input to the input terminal C from the main control block (not shown) during normal operation, or the display clear command (active level 0) is input to the input terminal G. When 1) is input, the "display clear, reset" control signal is output from the OR circuit 39 to the common driver 16 and the segment driver 17 via the output terminal I.

The interface block 13 generates a system clock signal SCK necessary for LCD display control based on a basic clock signal input from a clock oscillation block (not shown) and outputs the system clock signal SCK to the display control block 12. Display serial code data input from a main control block (not shown) is level-converted and output to the display data memory block 14. Also,
The interface block 13 has various instructions (display ON / OFF) input from the main control block.
Command, display clear command, instruction command / data write, etc.) and reset signal RESET1, R
The ESET 2 is level-converted and output to the display control block 12.

The display data memory block 14 is a character generator ROM (hereinafter referred to as CGROM) for storing character data such as symbols and characters, and this CGR.
A character generator RAM (hereinafter referred to as CGRAM) that temporarily stores character data read from the OM.
And a display data RAM (hereinafter, referred to as a display data RAM) that has a storage area having the same dot configuration as the display dots of the LCD 18 and expands the character data read to the CGRAM to the display position.
(Referred to as DDRAM) and the like.

Therefore, the display data memory block 1
4 reads character data addressed by the serial code data input from the interface block 13 from the CGROM to the CGRAM, and DDR according to the display position designation of the serial code data.
The read character data is expanded in the AM and the expanded character data is output to the data gradation control block 15 as display data.

Further, the display data memory block 14 is
In response to a memory control signal (data write command, display clear / reset command) input from the display control block 12, data expansion to the DDRAM and holding of the expanded data are performed, and at the same time, the expanded data is erased.

The data gradation control block 15 outputs gradation data in which the pulse width of each liquid crystal drive pulse is set based on the display data to the LCD 18 to control the gradation display of the LCD 18. Memory block 1
The display data input from No. 4 is converted into gradation data according to the pulse width setting and output to the segment driver 17.

The common driver 16 sequentially scans and drives a predetermined number of scanning lines in the LCD 18 according to the control timing of the common control signal input from the display control block 12, and resets / P in the display control block 12.
The drive voltage level on the scanning line side is changed to the “H” level (VCC level, display ON) by the display ON / OFF control signal and the display clear / reset signal input from the OC control circuit 122.
) Or "L" level (VSS (ground) level, display OFF, display clear / reset).

The segment driver 17 sequentially selects a predetermined number of signal lines in the LCD 18 according to the control timing of the segment control signal input from the display control block 12, and the grayscale data input from the data grayscale control block 15 is selected. Are sequentially transferred to the selected signal line, and the display ON / OFF control signal input from the reset / POC control circuit 122 in the display control block 12,
The display clear / reset signal sets the driving voltage level on the signal line side to the “H” level (VCC level, when the display is ON), or the “L” level (VSS (ground) level,
Display OFF, display clear / reset).

In the LCD 18, liquid crystal is sealed between a pair of transparent glass substrates, and a plurality of scanning lines and signal lines are formed in a matrix on the opposite surfaces of the pair of transparent glass substrates. Display dots made of liquid crystal are formed at the respective intersections with, and the scanning lines and the signal lines are selectively driven by the drive control by the common driver 16 and the segment driver 17, so that the grayscale data is sequentially displayed on the liquid crystal at the selected intersections. However, the electric charge is accumulated and a character or an image based on the display data is displayed.

Next, the operation of this embodiment will be described. First,
When the liquid crystal display device 10 of the present embodiment is turned on, the power-on detection circuit 121 in the display control block 12 is turned on.
Thus, the power-on state of the power supply block 11 is detected, and the POC signal is set by the power-on detection and is output to the input terminal E of the reset / POC control circuit 122.
Display ON / OFF in the reset / POC control circuit 122
In the control signal generation unit 122a, the SR latch circuit 37 outputs the "L" level signal to the AND circuit 38,
A “display OFF” control signal is output from the circuit 38 to the common driver 16 and the segment driver 17 via the output terminal H.

In the common driver 16 and the segment driver 17, the "display OFF" control signal
The driving voltage level on the scanning line side and the driving voltage level on the signal line side are set to the “L” level (VSS (ground), and the display of the LCD 18 is turned off.

Then, the reset / POC control circuit 122
When an instruction command and a data write signal are input to the input terminal D of the main control block (not shown) through the interface block 13, the display ON / OFF control signal generation unit 122a outputs the "H" signal from the SR latch circuit 37. Is output to the AND circuit 38, and the above "display O"
The FF "control signal is released, and the" display ON "control signal is output from the AND circuit 38 to the common driver 16 and the segment driver 17 via the output terminal H.

Therefore, normal instruction commands (data write command, display clear / reset command, etc.)
, Display data memory block 14, common driver 1
6 and the segment driver 17.

The display serial code data input to the interface block 13 is expanded in the DDRAM in the display data memory block 14, and the display data is output to the data gradation control block 15 and converted into gradation data. Is output to the segment driver 17,
The display control block 12 outputs the common control signal and the segment control signal to the common driver 16 and the segment driver 17. In the common driver 16, the LCD 18 is controlled by the control timing of the input common control signal.
A predetermined number of scanning lines in the LCD are sequentially scanned and driven, and in the segment driver 17, a predetermined number of signal lines in the LCD 18 are sequentially selected according to the control timing of the input segment control signal and input from the data gradation control block 15. The gradation data to be transferred is sequentially transferred to the selected signal line, and normal liquid crystal display driving is started.

Next, during this normal operation, when noise is generated due to disturbance or the like and enters the power supply block 11, it is detected in the power-on detection circuit 121, and the detection process is as shown in FIG. As shown in a), a predetermined noise detection level is preset with respect to the reference voltage, and when the noise detection level exceeds the noise detection level, a POC signal is output as shown in FIG. It

When the POC signal resulting from this noise detection is input to the input terminal E of the reset / POC control circuit 122, the display ON / O in the reset / POC control circuit 122 is turned on.
In the FF control signal generator 122a, the SR latch circuit 37
Outputs an “L” level signal from the AND circuit 38,
Common driver 1 from ND circuit 38 via output terminal H
A "display OFF" control signal is output to 6 and the segment driver 17, and the display on the LCD 18 is turned off. At this time, as shown in FIG. 5D, the common control signal and the segment control signal output from the display control block 12 are stopped (OFF state).

At this time, in this embodiment, the "display OFF" control signal is the common driver 16 and the segment driver 1.
7, the display of the LCD 18 is turned off, and no instruction command is output to the display data memory block 14. Therefore, the display data expanded in the display data memory block 14 is retained. Has been left.

Then, again, as shown in FIG. 5C, the instruction command / data write instruction signal 13c is input from the main control block (not shown) to the input terminal D of the display control block 12 through the interface block 13. Then, the display ON / OFF control signal generation unit 122
In a, the POC output is reset (OFF state), the "H" signal is output from the SR latch circuit 37 to the AND circuit 38, and the "display OFF" control signal is released, as shown in FIG. The “display ON” control signal is output from the AND circuit 38 to the common driver 16 and the segment driver 17 via the output terminal H.

Therefore, normal instruction commands (data write command, display clear / reset command, etc.)
, Display data memory block 14, common driver 1
6 and the segment driver 17 again, and as shown in FIG. 5D, the display control block 12
Then, the output of the common control signal and the segment control signal is restarted (ON state), and the normal display drive state of the LCD 18 is restored.

As described above, in the display control unit 10 of the liquid crystal display device of this embodiment, the reset / POC control circuit 122 provided in the display control block 12 displays ON / OFF the signal operated by the POC detection output. Since only the control signal is used, PO is detected by the noise signal detection during normal operation.
Even if the C signal is output, the display on the LCD 18 is only erased, and the expanded contents of the display data in the display data memory block 14 are retained. Then, the POC is re-input by re-inputting the instruction command and the data write signal.
The output is reset, the display OFF control signal is released,
The display ON control signal is automatically output, and the normal LCD
The display driving state 18 is restored, and the display is restarted by the held display data.

Therefore, even in the case of the conventional POC output that is output due to the influence of noise, the liquid crystal panel initialization processing is performed to cause the liquid crystal panel display abnormality, but in the present embodiment, the display is turned off. Since only the operation is performed and the display data is also held, it is possible to prevent the display abnormality from occurring at the time of restoration. Further, since the normal display is automatically restored, there is no need to perform the power-on (reset) operation again as in the conventional case, and the operation load on the user can be reduced.

In the above embodiment, the "display OFF" control signal is sent to the common driver 16 and the segment driver 1.
When output to 7, the driving voltage level on the scanning line side and the driving voltage level on the signal line side are both at the “L” level (VSS
Although it is set to (ground), the display signal may be turned off by outputting a drive signal that causes one or both of the scanning line side and the signal line side to be "non-selected".

(Second Embodiment) In the first embodiment, the POC output due to noise detection is reset to "display OF".
Although it has been stated that the operation returns to the normal operation "after some instruction instruction or data write has been established" as a method of canceling F ", the second embodiment will be described by taking a specific example of the instruction instruction at the time of returning. For example, the following is given as an example of the instruction instruction of the controller / driver LSI for the character LCD module. The instruction instructions are roughly classified into the following three types.

(1) Instructions (command register) for setting functions of this LSI such as display method and display function (2) Instructions (address register, address data) for giving addresses to internal RAM etc. (3) Internal Instruction for writing data to RAM (data writing) The command register in (1) can operate independently, and can operate in 1 unit (1 unit: 1 SCK x 8 = 8 bits), but (2) , (3), at least 3 units (1 SCK × 3 × 8) of operations are required to select an arbitrary RAM, determine an arbitrary address, and write data to the address.

The instruction of the command register of (1) is: display clear → clear display, display ON / OFF control to initialize all commands → standby to control ON / OFF of all display → DC / DC System set to stop the converter and reduce the power supply current → Dot shift to set the number of display digits → LCD dot control to set the dot shift of display → Test mode to set the value of LCD voltage control → Test mode Make settings Here, if a noise signal is input during normal use in this POC function, the "display OFF" control signal is immediately output, and the command that was executed immediately before the input of the noise signal is Is held by the register of FIG. 3, and if any instruction instruction is input from the input terminal D of FIG. Display OFF "control signal is released, the instruction that has been held is executed.

As an instruction instruction for releasing "display OFF" in this embodiment, a standby (command
Register). The specific contents of the canceling method will be described below with reference to the signal timing charts in FIGS.

That is, as shown in the timing chart of one unit of command in FIG. 6, writing of each instruction data sets the STB signal (data input enable signal) to the “L” level as shown in FIG. 6A. After that, the writing is performed at the rising edge of the SCK signal as shown in FIG. Therefore, as a method of canceling the P0C function, after the completion of the writing, the "display OFF" is canceled after the eighth generation of the SCK signal, and "display ON" is output, so that the display content can be confirmed. It will be possible.

For example, when the POC function operates due to the mixing of the noise signal and the "display OFF" control signal is output during the data writing to the internal RAM of the display data memory block 14 of FIG. A standby command is executed as a release command, and once the power supply block 11
By stopping the internal DC / DC converter and setting the LCD drive voltage to VSS (ground level), the power supply current is reduced, and then the data writing to the internal RAM is restarted, which causes noise, etc. A normal display operation can be performed without the influence of a malfunction due to.

Further, in FIGS. 7A to 7C, when only the command register instruction is written, the POC function is released after the eighth output of the system clock signal SCK after the writing is completed. 8A to 8C, an address register instruction + address instruction + data 1+ is shown in FIGS.
When writing + data n (memory selection + address determination + data writing: at least 3 units), cancel the POC function after completion of the 8th output of the system clock signal SCK after the writing is established. An example is shown. This Figure 7
And as shown in FIG. 8, the POC release method of this embodiment is
The present invention can be applied to examples of other command instructions, and in any case, the display content can be confirmed by canceling the POC function with a specific command.

(Third Embodiment) In the first and second embodiments, as a method of resetting the POC output due to noise detection and releasing "display OFF", the normal operation is performed "after some instruction command or data writing is established". However, in the third embodiment, the PO is generated by the first rising edge (or falling edge) of the system clock signal SCK used in the instruction instruction.
The C function is canceled. The specific contents of the canceling method will be described below with reference to the signal timing charts of FIGS. 9 to 11.

For example, as an example of the instruction instruction of the controller / driver LSI for the character LCD module, (1) to (1) to
There are three types of (3), and the command register of (1) can operate independently, and can operate in 1 unit (1 unit: 1 SCK x 8 = 8 bits), but (2), (3 ), Select an arbitrary RAM, decide an arbitrary address, and write at least 3 units (1
SCK x 3 x 8) operation is required.

Therefore, depending on the set frequency of the system clock signal SCK, it may take a considerable time until the POC function is generated and the POC function for returning to the normal operation is released.

Therefore, as a method of releasing the POC function more quickly, as shown in the timing chart of the command of one unit in FIG. 9, writing of each instruction data is performed by the STB signal (as shown in FIG. 9A). After the data input enable signal) is set to "L" level, the same figure (b)
This is done by writing at the rising edge of the SCK signal as shown in FIG. Therefore, as a method to cancel the P0C function,
"Display OFF" at the first rising edge of SCK signal
By canceling the display and outputting "display ON", the display contents can be confirmed quickly.

In other words, in the present embodiment, when a noise signal enters this LSI during normal use, the POC function immediately operates and is controlled so that only "display OFF" is performed.
The instruction that has been executed up to now is held by the internal register, and the system clock signal SC is input from the input terminal D of FIG.
When the first rising edge signal of K is input, the “display OFF” is released, the command held until then is executed, and the display content can be confirmed earlier.

Further, FIGS. 10A to 10C show an example in which the POC function is canceled by the first rising edge signal of the system clock signal SCK when only the command register instruction is written. 11 (a) to (c), address register instruction + address instruction + data 1 + ... + Data n (memory selection + address determination + data writing:
System clock signal SC for writing at least 3 units)
An example in which the POC function is canceled by the first rising edge signal of K is shown.

As shown in FIGS. 10 and 11, the POC canceling method of this embodiment can be applied to other examples of command instructions, and in any case, the displayed contents can be confirmed earlier. .

(Fourth Embodiment) As an application example of the third embodiment, when the frequency of the system clock signal SCK is too fast, that is, at the first rising edge of SCK, P
When the OC function cannot be released, the release timing is arbitrarily set and P is set by the Nth rising edge of SCK.
There is also a method of canceling the OC function.

This releasing method is particularly effective when the parallel interface is used, since M bits of data are sent at the same time. Further, even during the serial interface, the frequency of the system clock signal SCK can be dealt with by arbitrarily setting the release timing of the system clock signal SCK by the mode (bit) according to the internal timing of the LSI.
It becomes possible to cancel the POC function.

The specific contents of the method for canceling the POC function will be described below with reference to the signal timing charts in FIGS. First, as shown in the timing chart of the command of one unit in FIG. 12, writing of each instruction data is performed by the STB as shown in FIG.
This is performed by setting the signal (data input enable signal) to "L" level and then writing at the rising edge of the SCK signal as shown in FIG. Therefore, as a method of canceling the P0C function, "display OFF" is canceled at the Nth rising edge of the SCK signal, and "display ON" is output, so that the POC function is reliably canceled and the displayed contents It will be possible to quickly confirm.

Further, FIGS. 13A to 13C show an example in which the POC function is canceled by the first rising edge signal of the system clock signal SCK when only the command register instruction is written. 14 (a) to (c), address register instruction + address instruction + data 1 + ... + Data n (memory selection + address determination + data writing:
System clock signal SC for writing at least 3 units)
An example in which the POC function is canceled by the first rising edge signal of K is shown.

As shown in FIGS. 13 and 14, the POC canceling method of this embodiment can be applied to other examples of command instructions, and in any case, the POC function is surely cancelled and the displayed contents are displayed. Can be confirmed earlier. In addition,
It is also possible to change the release timing of the system clock signal SCK for releasing the POC function according to each instruction instruction.

[0066]

According to the first aspect of the present invention, it is possible to prevent the occurrence of a display abnormality at the time of returning from the display erased state due to noise detection, and to automatically return to the normal display, so that the power is turned on again. It is not necessary to operate (reset) or the like, and the operation load on the user can be reduced.

According to the second aspect of the present invention, it is possible to shorten the period for automatically canceling the display stopped state at the time of noise detection, and to confirm the display contents before the display is erased more quickly.

According to the third aspect of the present invention, it is possible to surely cancel the display stopped state at the time of noise detection and confirm the display content promptly.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a display control unit of a liquid crystal display device of a first embodiment to which the present invention is applied.

FIG. 2 is a block configuration diagram inside a display control block of FIG.

FIG. 3 is a circuit configuration diagram in the reset / POC control circuit of FIG.

FIG. 4 is a diagram showing a relationship between a function and an active level of an input signal input to each input terminal of FIG. 3 and an output signal output from each output terminal.

FIG. 5 is a diagram illustrating a case where noise is detected to PO in the display control unit of FIG.
The timing chart of the signal which shows the operation relation of each part until C release.

FIG. 6 is a timing chart of signals when the POC canceling method of the second embodiment is applied to a command of one unit.

FIG. 7 is a timing chart of signals when the POC canceling method of the second embodiment is applied when a write operation of only a command register instruction is established.

FIG. 8 is a timing chart of signals when the POC canceling method of the second embodiment is applied when a plurality of commands are established.

FIG. 9 is a timing chart when the POC cancellation method of the third embodiment is applied to a command of one unit.

FIG. 10 is a timing chart of signals when the POC canceling method of the third embodiment is applied when a write operation of only a command register instruction is established.

FIG. 11 is a timing chart of signals when the POC canceling method of the third embodiment is applied when a plurality of commands are satisfied.

FIG. 12 is a timing chart when the POC canceling method of the fourth embodiment is applied to a command of one unit.

FIG. 13 is a timing chart of signals when the POC release method of the fourth embodiment is applied when a write operation of only a command register instruction is established.

FIG. 14 is a timing chart of signals when the POC canceling method of the fourth embodiment is applied when a plurality of commands are satisfied.

FIG. 15 is a flowchart for explaining a conventional POC function.

FIG. 16 is a circuit configuration diagram of a logic circuit for controlling a conventional POC function.

17 is a diagram showing the relationship between the function and active level of the input signal input to each input terminal of FIG. 16 and the output signal output from each output terminal.

[Explanation of symbols]

10 Display Control Unit 11 Power Supply Block 12 Display Control Block 13 Interface Block 14 Display Data Memory Block (Display Information Storage Means) 15 Data Grayscale Control Block 16 Common Driver 17 Segment Driver 18 LCD 31 to 33 Inverter Circuits 34, 35, 39 OR Circuits 36 and 37 SR latch circuit 38 AND circuit 121 Power-on detection circuit 122 Reset / POC control circuit 122a Display ON / OFF control signal generation unit 122b Display clear / reset control signal generation unit

Claims (3)

(57) [Claims] 1. A liquid crystal drive method for displaying the liquid crystal panel based on display data and various instruction signals output by the control means after initializing a control means for driving and controlling the liquid crystal panel when the power is turned on. The control means detects a power-on state,
A power-on detection circuit having a noise detection circuit that detects a noise signal generated on the power supply line and exceeding a predetermined value, and a display
Display ON / OFF control that generates ON / OFF control signals
Generates a signal generator and display clear / reset control signal
Power with display clear / reset control signal generator
And on reset control circuit, a display information storage means for storing the display data, and means for displaying the display data held in the display information storage unit and outputs to the liquid crystal panel, comprising a, at the time of power-on , Power supply by the power-on detection circuit
When the power-on reset control circuit
The display OFF control signal is output as the instruction signal.
Stop the display of the liquid crystal panel and display
Display information storage means for outputting a clear / reset control signal
After initializing, the display drive of the liquid crystal panel is started.
It was, during the display driving of the liquid crystal panel, the power-on test
Said noise detection circuit detecting circuit is, when generating a noise detection signal by detecting said noise signal, based on the noise detection signal, the finger than the power-on reset control circuit
Only the display OFF control signal is output as a display signal ,
To stop the display of the liquid crystal panel, the to maintain the holding state of the display data in the display information storage unit, after displaying stop of the liquid crystal panel, release signal synchronized with a predetermined clock signal is inputted to the control means Based on this, the display OFF control signal is released and the instruction
The display ON control signal is output as a signal, the display data stored in the display information storage means is output to the liquid crystal panel, and the display is restarted. 2. The control means, after the display of the liquid crystal panel is stopped, the release signal input to the control means and the leading or trailing edge of the leading clock of the predetermined clock signal synchronized with the release signal. And outputting the instruction signal for restoring the display state of the liquid crystal panel, outputting the display data held in the display information storage means to the liquid crystal panel, and restarting the display. The liquid crystal driving method according to claim 1. 3. The control means, after the display of the liquid crystal panel is stopped, the N-th rising or falling of the release signal input to the control means and the predetermined clock signal synchronized with the release signal. And outputting the instruction signal for restoring the display state of the liquid crystal panel, outputting the display data held in the display information storage means to the liquid crystal panel, and restarting the display. The liquid crystal driving method according to claim 1.