JP2006119409A - Driving circuit of matrix device, matrix device, electooptical equipment and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving circuit of a matrix device in which the number of control signals and the number of external connection terminals are reduced and a control system is simplified. <P>SOLUTION: The driving circuit drives the matrix device in which functional elements are arranged at the crossing points of a plurality of row lines and a plurality of column lines. The driving circuit is provided with a row selecting means which selects a specific row line from the plurality of the row lines and a column selecting means which selects a specific column line from the plurality of the column lines. At least one of the row selecting means and the column selecting means is constituted by including a shift register (11) which is constituted so that all shift registers are reset when a reset signal is inputted and the reset signal has a low potential and a start pulse generating circuit (18) which generates a start pulse when a reset signal is inputted and the reset signal has a high potential. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for improving a circuit for driving a matrix device that sequentially selects functional elements arranged in a matrix.

  Matrix devices that sequentially select functional elements arranged in a matrix and operate so as to exhibit a predetermined function are used in various devices. As such a device, for example, there is an electrophoresis apparatus disclosed in Japanese Patent Laid-Open No. 2002-169190 (Patent Document 1). In addition to the electrophoresis device, the matrix device is used in various devices such as a liquid crystal display device, an electroluminescence display device, or a capacitance detection device that is a component of a fingerprint sensor or the like.

  FIG. 8 is a block diagram illustrating a configuration example of a driving circuit of a conventional line sequential matrix device. The drive circuit of the matrix device shown in FIG. 8 is for sequentially selecting functional elements 551 arranged in a matrix, and includes a plurality of scanning lines 532, a scanning driver 520 for selecting the scanning lines, and a plurality of scanning lines. Data line 533 and a data driver 510 for outputting predetermined data to the data line. The functional element 551 is disposed at each intersection of the scanning line 532 and the data line 533. The scan driver 520 includes a scan shift register 521 for determining timing. The scan shift register 521 has a terminal for inputting a scan line selection reference signal CLKY corresponding to a row reference signal for determining operation timing. The data driver 510 includes a data shift register 511 for determining timing. The data shift register 511 has a terminal for inputting a data line selection reference signal CLKX corresponding to a column reference signal for determining operation timing. The operation timing of each reference signal CLKY, CLKX is controlled by an external control circuit. The scan shift register 521 sequentially transfers a signal SPY that is input to the first stage of each shift register, based on a scan line selection reference signal that is a reference signal. The data shift register 511 sequentially transfers the signal SPX input to the first stage of each shift register based on the data line selection reference signal that is a reference signal. Thereby, a signal from DATA is taken into each stage of the data latch corresponding to each output stage of the shift register. When SPX is transferred to the final stage of the shift register and then XLP is input, a signal taken into the data latch is output to the data line 533. Any one of the scanning lines 532 is sequentially selected by the scanning driver 520, and a signal output to the data line is controlled by the data driver, so that any one of the functional elements 551 arranged in a matrix is selected. One row is sequentially selected and a signal of the data line 533 is written to the functional element.

  By the way, in the above-described conventional configuration, as a control signal for controlling the operation timing of the data driver and the scan driver, a row reference signal and a column reference signal, which are two dedicated reference signals, are generated by an external control circuit, respectively. It was controlled by supplying to the shift register. Further, the start pulse signals SPX and SPY are supplied to the first stage of each shift register. Therefore, an external connection terminal for inputting a reference signal and an external connection terminal for inputting a start pulse signal are required for each selection circuit as external connection terminals for inputting a control signal. As described above, the increase in the number of connection terminals increases the restrictions on mounting, and there are problems with ease of mounting, connection reliability, design freedom, inspection efficiency, and the like. Further, in order to control the operation timing of the data driver and the scan driver, it is necessary to synchronize these control signals by the external control circuit, and the external control circuit is complicated. For this reason, there was a problem that the development efficiency was poor.

JP 2001-169190 A

  Therefore, an object of the present invention is to provide a drive circuit for a matrix device in which the number of control signals and the number of external connection terminals is reduced and the control system is simplified.

  The first aspect of the present invention is a drive circuit for driving a matrix device in which a functional element is provided at each intersection of a plurality of row lines and a plurality of column lines, and a specific row is selected from the plurality of row lines. A row selection unit that selects a line; and a column selection unit that selects a specific column line from the plurality of column lines. At least one of the row selection unit and the column selection unit receives a reset signal. A shift register configured to be fully reset when the reset signal is at a low potential, and configured to generate a start pulse when the reset signal is input and the reset signal is at a high potential. And a start pulse generation circuit. The drive circuit for the matrix device.

  According to such a configuration, the signal input / output terminals excluding the power supply can be set as four input terminals for the reset signal, the clock signal, the clock inverted signal, and the data input / output signal. Therefore, a drive circuit for a matrix device can be obtained in which the number of control signals and external connection terminals is reduced and the control system is simplified.

  An end pulse feedback means that feeds back an end pulse that is the output of the final stage of the shift register, the start pulse generated by the start pulse generation circuit, and an end pulse that is fed back by the end pulse feedback means. It is preferable to further include a start pulse detection circuit that outputs a high potential to the first stage of the shift register when either the start pulse or the end pulse that is input becomes a high potential.

  Thus, the data transfer of the shift register can be continued using the end pulse as the start pulse.

  In addition, it is preferable to further include an inverted clock generation unit that receives a clock signal and generates a clock inverted signal obtained by inverting the clock signal.

  Thereby, the number of control signals and external connection terminals can be further reduced.

  It is also preferable that an end pulse output from the shift register included in the column selection unit is input as a row reference signal of the row selection unit.

  This eliminates the need to supply a row base signal from the outside.

  The column selecting means preferably includes a data latch, and the data latch preferably uses the end pulse as a latch pulse.

  Thereby, since the latch pulse input terminal can be omitted, the number of terminals can be further reduced.

  The second aspect of the present invention is a matrix device configured using the drive circuit described above.

  Thereby, a matrix device with a small number of control signals and external connection terminals can be obtained. Such a matrix device can be used for various devices such as an electro-optical device such as an electrophoretic display device, a liquid crystal display device, and an electroluminescence display device, or a capacitance detection device that is a component of a fingerprint sensor.

  The third aspect of the present invention is an electro-optical device (electrophoretic display device) configured using the matrix device described above and using an electrophoretic element as the functional element, wherein the latch pulse is any of the above-described latch pulses. A row line selection pulse is output at a timing at which the row line selection pulse is not output.

  Thereby, an electro-optical device with improved display characteristics can be obtained.

  According to a fourth aspect of the present invention, there is provided an electronic apparatus comprising the above-described matrix device or electro-optical device. Here, “electronic device” refers to a device in general having a certain function, and its configuration is not particularly limited. For example, electronic paper, electronic book, IC card, mobile phone, video camera, personal computer, head mount A display, a rear-type or front-type projector, a fax machine with a display function, a digital camera finder, a portable TV, a PDA, an electronic notebook, and the like are included.

  Hereinafter, an electrophoretic display device to which the present invention is applied will be described as an embodiment of the present invention.

  FIG. 1 is a block diagram illustrating a configuration of an electrophoretic display device according to an embodiment. The electrophoretic display device 1 shown in FIG. 1 includes a plurality of scanning lines 32, a scanning driver 20 for sequentially selecting the scanning lines 32, a plurality of data lines 33 provided so as to intersect the scanning lines 32, A data driver 10 for sequentially selecting the data lines 33; and an active matrix unit 30 including pixel circuits 31 provided at intersections of the scanning lines 32 and the data lines 33 and arranged in a matrix. It consists of The correspondence with the present invention will be described. The scanning line 32 corresponds to a row line, the data line 33 corresponds to a column line, the scanning driver 20 corresponds to a row selection unit, and the data driver 10 serves as a column selection unit. The pixel circuit 31 corresponds to a functional element.

  The data driver 10 includes a data latch 12, a data shift register 11 for sequentially selecting the data latch 12, and a data buffer 13.

  The scan driver 20 includes a scan shift register 21 for sequentially scanning the scan lines 32 and a scan buffer 22.

  A reset signal RST generation circuit (not shown) is connected to each of the data shift register 11 and the scan shift register 21.

  The data driver 10 and the scan driver 20 of the present embodiment include a data shift register 11 and a scan shift register 21, respectively, and sequentially select the data line 33 and the scan line 32 at high speed by their operations. However, in the conventional active matrix driving device, when the variation in potential at the time of turning on the power is erased, it is necessary to perform a full scan with a normal shift register, and it takes an extra time to start up after turning on the power. In order to avoid this, in the present embodiment, the data in the shift register can be collectively reset only by applying the reset signal RST to the data shift register 11 and the scan shift register 21. In response to the reset signal RST, only two stages on the input side of the scan shift register 21 of the scan driver 20 are selected, and all other stages are unselected.

  In the active matrix section 30, pixel circuits 31 including electrophoretic elements are arranged in a matrix, and a plurality of scanning lines 32 and a plurality of low-potential power supply lines 36 are wired along the row direction. The data line 33 is wired along the column direction.

  FIG. 2 is a circuit diagram illustrating a detailed configuration of the pixel circuit 31. As shown in FIG. 2, the pixel circuit 31 includes an electrophoretic element 37, a capacitive element 38 for holding the electropolarization state of the electrophoretic element 37, and a switching operation to store charges in the capacitive element 38. And a selection transistor 34. The selection transistor 34 has a gate connected to the scanning line 32, a source connected to the data line 33, and a drain connected to one end of each of the electrophoretic element 37 and the capacitive element 38. The low potential power supply line 36 is connected to the other end of the capacitive element 38.

  FIG. 3 is a circuit diagram illustrating a detailed configuration of the data driver 10. The data shift register 11 controls the inversion of the clocked inverter 50 that controls the reception of data from the preceding stage, the inverter 51 that inverts the output of the clocked inverter 50, and the output of the inverter 51, that is, the output to the subsequent stage of the shift register. For this purpose, the combination with the clocked NAND 52 is made into one stage, and this is connected over a plurality of stages. The data shift register 11 receives a clock signal CLK and a clock inversion signal CLKB having opposite phases. In the odd-numbered stages of the data shift register 11, the clocked inverter 50 receives the clock signal CLK, and the clocked NAND 52 receives the clock inverted signal CLKB. In the even stages of the data shift register 11, the clocked inverter 50 receives the clock inversion signal CLKB and the clocked NAND 52 receives the clock signal CLK. Therefore, the operation timings of the even and odd stages of the data shift register 11 are opposite to each other. In addition, the data driver 10 has a function of entering a reset state when the reset signal RST is at a low potential. In the reset state, the output stage of the start pulse generation circuit 18 is set to a high potential, and the outputs of each stage of the data shift register 11 are all reset to a low potential.

  As shown in the circuit configuration of FIG. 4, the clocked NAND 52 includes a clocked inverter 52a and reset signal input transistors Tr1 and Tr2. As an input signal IN to the clocked NAND 52, a reset signal RST from a reset signal generation circuit (not shown) and an output signal from the inverter 51 are input. When the potential of the reset signal RST is level L, the transistor Tr2 is inactive, and the transistor Tr1 to which the inverted signal is inverted is activated, so that the output voltage is close to the high potential VDD. Therefore, the output voltage of the clocked NAND 52 becomes level H regardless of the input signal IN. At this time, since the output of the clocked NAND 52 at level H is inverted by the inverter 51, the outputs (N3, N5) at each stage of the shift register are all at level L. When the input signal RST for the clocked NAND 52 is at level H, the transistor Tr2 is active and the transistor Tr1 is inactive. In this case, the clocked NAND 52 is equivalent to a circuit including only the clocked inverter 52a. Accordingly, at this time, the data shift register 11 performs the following normal shift register operation.

  In the odd stage of the data shift register 11, the clocked inverter 50 becomes active in synchronization with the rising edge of the clock signal CLK, and the clocked NAND 52 becomes active in synchronization with the rising edge of the clock inverted signal CLKB. On the other hand, in the even-numbered stage of the data shift register 11, the clocked inverter 50 becomes active in synchronization with the rising edge of the clock inverted signal CLKB, and the clocked NAND 52 becomes active in synchronization with the rising edge of the clock signal CLK. Since the clock signal CLK and the clock inversion signal CLKB are complementary signals, the operation timing is shifted by a half period of CLK between the odd-numbered stage and the even-numbered stage of the data shift register 11.

  The data latch 12 includes a first latch 12a and a second latch 12b. The first latch 12a latches the image data DATA according to the sequential selection signal XSEL {n} (n is a natural number) from the data shift register 11. The second latch 12b latches the signal from each stage of the first latch 12a according to the latch pulse XLP.

  The data buffer 13 increases the driving capability of the sequential selection signal XSEL {n} from the second latch 12b that constitutes the data latch 12 and outputs it.

  The inverted clock generation circuit 14 is formed by combining a plurality of inverters as shown in the figure, and receives the clock signal CLK and generates a clock inverted signal CLKB obtained by inverting the signal. The inverted clock signal CLKB generated by the inverted clock generation circuit 14 is output to each stage of the data shift register 11 together with the clock signal CLK.

  The EP / EPB generation circuit 15 is formed by combining a plurality of inverters as shown in the figure, and an end pulse (end signal) XEP of the data driver 10 is inputted, and based on this, a scan driver reference signal EP and an inverted signal EPB thereof Is generated. The generated signals EP and EPB are input to the column reference signal input terminal of the scan shift register 21 of the scan driver 20. The scan driver reference signal corresponds to the “row reference signal” in the present invention.

  The end pulse feedback means 17 feeds back the end pulse XEP, which is the output of the final stage of the data shift register 11, to the start pulse detection circuit 19.

  The start pulse generation circuit 18 receives the reset signal RST, the clock signal CLK, and the clock inversion signal CLKB, and generates a start pulse XST.

  The start pulse detection circuit 19 is configured using an OR circuit, and outputs a potential to the first stage of the data shift register 11 when the output stage of the start pulse generation circuit 18 is at a high potential. The start pulse detection circuit 19 outputs a high potential to the first stage of the data shift register 11 when the end pulse XEP becomes a high potential. That is, the end pulse XEP becomes a start pulse, and the data shift register 11 is sequentially transferred again to each stage. With this configuration, the data shift register 11 continues data transfer unless a reset signal is input again.

  The output of the start pulse generation circuit 18 is input to the start pulse detection circuit 19. When the reset signal RST is at a high potential, the data shift register 11 is in an operating state, and the data set in the start pulse generation circuit 18 is sequentially transferred according to the clock signal CLK. Since the low potential is input to the start pulse generation circuit 18 while the data shift register 11 is operating, the start pulse generation circuit 18 supplies the data shift register until the next low potential reset signal RST is applied. 11 does not receive the start pulse XSP. When the start pulse XSP is transferred to the final stage of the data shift register 11, the end signal XEP which is the output of the final stage of the data shift register 11 is input to the start pulse detection circuit 19 via the end pulse feedback means 17.

  FIG. 5 is a circuit diagram illustrating a detailed configuration of the scan driver 20. The scan driver 20 has a configuration similar to that of the data driver 10 described above. Two stages on the input side of the scanning shift register 21, that is, the first stage and the second stage are a clocked inverter 60, an inverter 61 that inverts the output of the clocked inverter 60, and an output of the inverter 61 (to the subsequent stage of the shift register). In combination with a clocked NAND 62 for inversion control.

  The scan shift register 21 includes two input terminals corresponding to column selection end signal input means, and column selection end signals EP and EPB having opposite phases corresponding to row reference signals are input through the respective terminals. Is done. In the odd-numbered stages of the scan shift register 21, the clocked inverter 60 receives the clock signal CLK, and the clocked NAND 62 receives the clock inverted signal CLKB. In the even stages of the scan shift register 21, the clocked inverter 60 receives the clock inversion signal CLKB and the clocked NAND 62 receives the clock signal CLK. Therefore, the operation timings of the even and odd stages of the scan shift register 21 are opposite to each other. The detailed configuration of the clocked NAND 62 is the same as that of the clocked NAND 52 described above (see FIG. 4).

  The scan buffer 22 increases the drive capability of the sequential selection signal YSEL {m} (m is a natural number) from the scan shift register 21 and outputs it.

  The end pulse feedback means 27 feeds back an end pulse (end signal) YEP which is the output of the last stage of the scan shift register 21 to the start pulse detection circuit 29.

  The start pulse generation circuit 28 receives the reset signal RST, the scan driver reference signal EP, and the inverted signal EPB thereof, and generates a start pulse YST.

  The start pulse detection circuit 29 is configured using an OR circuit, and outputs a potential to the first stage of the scan shift register 21 when the output stage of the start pulse generation circuit 28 is at a high potential. The start pulse detection circuit 29 outputs a high potential to the first stage of the scan shift register 21 when the end pulse YEP becomes a high potential. That is, the end pulse YEP becomes a start pulse, and the scan shift register 21 is sequentially transferred again to each stage. With this configuration, the scan shift register 21 continues data transfer unless a reset signal is input again.

  The electrophoretic display device 1 of the present embodiment has such a configuration, and the operation thereof will be described next. Operations of the data driver 10 and the scan driver 20 will be described using a timing chart.

  FIG. 6 is a timing chart for explaining the operation of the electrophoretic display device 1 of the present embodiment.

  The data shift register 11 sequentially transfers the start pulse XSP at the rising and falling timings of the clock signal CLK. As a result, the data latch selection pulse XSEL {n} is sequentially output, and the image data DATA is sequentially taken into the first latch 12a in the data latch 12. When the latch pulse LP is input after the final stage data latch selection pulse XSEL {n} is output, the signal fetched into the first latch 12a is transferred to the second latch 12b, and the second latch is applied to each data line 33. The output X {n} of 12b is output.

  The output of the final stage of the data shift register 11, that is, the end pulse EP of the data driver corresponding to the column selection end signal of the present invention and its inverted signal EPB are not connected to the active matrix unit 30 but are included in the scan driver 20. It is output to the scan shift register 21 as a row reference signal.

  The scan shift register 21 sequentially transfers the start pulse YSP at the rising and falling timings of the clock signal CLK. Thereby, the scanning line selection pulse YSEL {m} is sequentially output. At this time, the end pulse EP and its inverted signal EPB of the data driver described above serve as a signal transfer reference signal. That is, after the reset operation, the level H is maintained in the two stages on the input side of the scan shift register 21 until the first end pulse EP is input. This state is the rise and fall of the end pulse EP. It is sequentially transferred to the next stage at the timing. Since the input side of the scan shift register 21 is connected to the low potential power supply line 36, the two stages on the input side always transfer the level L when the end pulse EP and its inverted signal EPB are operating. As a result, the scanning lines YSEL [n] sequentially become level H, and the scanning lines 32 are selected one by one.

  FIG. 7 is a perspective view illustrating an example of an electronic apparatus including an electrophoretic display device. As an example of the electronic apparatus, so-called electronic paper is illustrated. As shown in FIG. 7A, the electronic paper 100 according to this embodiment includes the electrophoretic display device 1 as a display unit 101. FIG. 7B illustrates an example in which the electronic paper 100 is folded in half, and the electrophoretic display device 1 (or 1a) is provided as the display portions 101a and 101b. In addition to the exemplary electronic paper, the electrophoretic display device 1 can be applied to various electronic devices including a display unit (for example, an IC card, a PDA, an electronic notebook, etc.).

  As described above, according to the present embodiment, it is possible to obtain an electrophoretic display device in which the number of control signals and the number of external connection terminals of the drive circuit (data driver, scan driver) is reduced and the control system is simplified.

  In addition, this invention is not limited to the content of each embodiment mentioned above, A various deformation | transformation implementation is possible within the scope of the summary of this invention.

  For example, in the above-described embodiment, the present invention is applied to both the data driver corresponding to the column selection unit and the scan driver corresponding to the row selection unit, but may be applied to only one of them. . Even in such a case, the number of control signals and external connection terminals can be reduced as compared with the conventional case, and the control system can be simplified.

  Further, in each of the above-described embodiments, the description has been given by taking an example of an electrophoretic display device configured using a matrix device and adopting an electrophoretic element as a functional element. Various things, such as a liquid crystal display element, an organic electroluminescent element, an electrostatic capacitance detection element, can be employ | adopted.

It is a block diagram explaining the structure of the electrophoretic display device of one Embodiment. It is a circuit diagram explaining the detailed structure of a pixel circuit. It is a circuit diagram explaining the detailed structure of a data driver. It is a figure shown in the circuit structure of clocked NAND. It is a circuit diagram explaining the detailed structure of a scanning driver. It is a timing chart explaining operation of an electrophoretic display device. It is a perspective view explaining the example of an electronic device provided with an electrophoretic display device. It is a block diagram explaining the structural example of the drive circuit of the conventional matrix apparatus.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Electrophoretic display apparatus, 10 ... Data driver, 11 ... Data shift register, 12 ... Data latch, 13 ... Data buffer, 14 ... Inversion clock generation circuit, 15 ... EP * EPB generation circuit, 17 ... End pulse feedback means, DESCRIPTION OF SYMBOLS 18 ... Start pulse generation circuit, 19 ... Start pulse detection circuit, 20 ... Scan driver, 21 ... Scan shift register, 22 ... Scan buffer, 27 ... End pulse feedback means, 28 ... Start pulse generation circuit, 29 ... Start pulse detection circuit , 30 ... Active matrix part, 31 ... Pixel circuit, 32 ... Scan line, 33 ... Data line, 100 ... Electronic paper

Claims (8)

A drive circuit for driving a matrix device in which a functional element is provided at each intersection of a plurality of row lines and a plurality of column lines,
Row selection means for selecting a specific row line from the plurality of row lines;
Column selecting means for selecting a specific column line from the plurality of column lines,
At least one of the row selection unit and the column selection unit is
A shift register configured to be reset when a reset signal is input and the reset signal is at a low potential;
A start pulse generation circuit configured to generate a start pulse when the reset signal is input and the reset signal becomes a high potential;
A drive circuit for a matrix device, comprising: End pulse feedback means for feeding back an end pulse which is the output of the final stage of the shift register;
When the start pulse generated by the start pulse generation circuit and the end pulse fed back by the end pulse feedback means are input, and either the start pulse or the end pulse becomes a high potential, the shift A start pulse detection circuit that outputs a high potential to the first stage of the register;
The drive circuit of the matrix device according to claim 1, further comprising:   3. The drive circuit for a matrix device according to claim 1, further comprising an inverted clock generation unit that receives a clock signal and generates a clock inverted signal obtained by inverting the clock signal.   4. The configuration according to claim 1, wherein the end pulse output from the shift register included in the column selection unit is input as a row reference signal of the row selection unit. 5. Drive circuit for matrix device.   5. The drive circuit for a matrix device according to claim 1, wherein the column selection unit includes a data latch, and the data latch uses the end pulse as a latch pulse.   6. A matrix device comprising the drive circuit according to claim 1.   7. The matrix device according to claim 6, wherein an electrophoretic element is used as the functional element, and the latch pulse is output at a timing at which a row line selection pulse is not output for any of the row lines. An electro-optical device. An electronic apparatus comprising the matrix device according to claim 6.

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