JPH08248926A - Active matrix type liquid crystal display device and driving method therefor - Google Patents

Abstract

PURPOSE: To prevent error signal from being fetched by providing hold means for holding a video signal and a control means for controlling hold means, thereby transferring the control signal almost without being delayed. CONSTITUTION: In this device, a pixel matrix and at least a signal line driving circuit are formed on the same circuit board, and the signal line driving circuit has sample means for sampling a video signal successively, hold means for holding the video signal sampled by sampling means and a first control means for controlling hold means. Then, a control clock CLK controlling the shifting operation of a shift register SR is simultaneously inputted to an output switch control circuit 101, a reset switch control circuit 102 and a hold switch control circuit 103 to control timings of output signals of these three control circuits. Thus, since the need for supplying control signals from the outside of the same circuit board is eliminated and the delay of the control signal is almost eliminated, the error signal is prevented from being fetched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device and a driving method thereof.

[0002]

2. Description of the Related Art Various driving methods for an active matrix type liquid crystal display device are known, and driving circuits for realizing the driving methods have various configurations. Among them, the drive circuits that are currently the mainstream are roughly classified into a dot sequential system and a line sequential system. They are distinguished by the difference in the timing of writing a signal in the liquid crystal. A line-sequential system is one in which signals are simultaneously written to a plurality of liquid crystals whose writing-holding states are controlled in one scanning line.
A system in which signals are sequentially written in the plurality of liquid crystals is called a dot sequential system. The dot-sequential drive circuit is mainly 10 cm diagonal
It is often used in the following small-sized liquid crystal display devices, and line-sequential drive circuits are often used in medium-sized to large-sized liquid crystal display devices having a diagonal of 10 cm or more. A line-sequential driving circuit is, for example, a flat panel display 199.
1 "The problem of driver LSI is solved by using a single low voltage power supply"
(November 26, 1991, Nikkei BP Publishing, p168
~ P172).

FIG. 2 shows a configuration example of an active matrix type liquid crystal display device using a line-sequential drive circuit as a signal line drive circuit. The TFT-LCD panel 201 includes a signal line driving circuit 206, a scanning line driving circuit 207, and a pixel matrix 202. Further, the signal line drive circuit is composed of a shift register SRX, a level shifter LSX and a sample and hold circuit SH, and the scanning line drive circuit 207 is composed of a shift register SRY and a level shifter LSY. Further, the pixel matrix 202 has n scanning lines G1, G2 ... Gn and m signal lines S1,
S2 ... Sm, and a thin film transistor element 203, a liquid crystal element 204, and a storage capacitor 205 are provided at the intersections of the scanning lines and the signal lines. The signal line driving circuit 206 is provided for the purpose of inputting the video signal VIDEO to the signal lines S1, S2 ... Sm, and the scanning line driving circuit 207 is provided for the thin film transistor elements 203 connected to the scanning lines G1, G2. It is provided for the purpose of controlling the conductive-non-conductive state.

An example of a driving method of the liquid crystal display device shown in FIG. 2 will be described. First, the shift register SRX synchronized with the first clock XCLK sequentially transfers the first signal XIN to the outputs Bit1, Bit2, ... Bitm. The signals output in time series to the outputs Bit1, Bit2 ... Bitm are subjected to voltage level shifting by the level shifter LSX, and are used as signals for controlling the timing of sampling the video signal VIDEO in the sample and hold circuit SH. The video signal is a sample
After being sampled in time series in the hold circuit SH,
It is written to the signal lines S1, S2 ... Sm at the same time as the output of the output enable signal ENBL. At this time, the scanning line driving circuit 207 is connected to a certain scanning line, for example, the scanning line G1 by the shift register SRY synchronized with the second clock CLY and the level shifter LSY for level shifting the output voltage of the shift register. A selection signal for outputting only the thin film transistor group to the conductive state is output. The turned-on thin film transistor group transmits the video signal output from the signal line driving circuit 206 to the signal lines S1, S2 ... Sm to the liquid crystal element and the storage capacitor provided for each pixel. Hereinafter, by repeating this for the scanning lines G2 ... Gn, the video signal can be written in the liquid crystal element of each pixel. Using the above method,
Furthermore, an arbitrary display screen can be obtained by utilizing the electro-optical characteristics of the liquid crystal element.

The shift registers SRX and SRY used in this liquid crystal display device are composed of, for example, the circuit shown in FIG. 5 (a) uses a D-flip flop, and FIG. 5 (b) shows a clocked inverter and an AN.
It uses a D gate. In the former shift register using the D-flip-flop, a shift operation of 1 bit is performed in 1 clock of the clock CLKa, and in the latter shift register, a shift operation of 1 bit is performed in 1/2 clock of the clock CLKb. Be seen. When the shift registers SRX and SRY are composed of MOSFETs or the like, the former structure is often used, and when they are composed of thin film transistors, the latter structure is often used.

Now, the TFT-LCD panel 201 shown in FIG.
Each control signal or video signal required to drive the LCD is generated or modulated in the TFT-LCD unit 309 shown in FIG. An external clock signal ECLK, a horizontal synchronizing signal HSYNC, a vertical synchronizing signal VSYNC, and a video original signal 310 are input to the TFT-LCD unit 301. The output enable signal ENBL is the horizontal synchronization signal H.
It is generated by the ENBL generation circuit 305 using SYNC and the first clock XCLK. The ENBL generation circuit outputs, for example, a counter circuit that counts the number of pulses of the first clock XCLK after being reset by the horizontal synchronization signal and a pulse signal when the count value of the counter circuit reaches a set value. It is composed of a pulse output circuit.
Further, the reset signal RST necessary for the reset operation of the sample and hold circuit is also generated similarly to the output enable signal.

Here, the signal line drive circuit is extracted from the liquid crystal display device having the above structure, and its operation will be further described. FIG. 4 is a diagram illustrating the configuration of the signal line driver circuit 206. The first clock is synchronized with the first clock XCLK.
Sequentially output signal XIN of Bit1, Bit2 ... Bi
shift register SRX for transferring to tm, and level shifter LS for shifting the voltage level of the output of the shift register
The signal output by X and the analog switch AS
W1,1, ASW2,1 ... Controls the conduction state of ASWm, 1. At this time, by sequentially turning on and off the analog switches, the sample capacitance CSPL is added to each signal line S.
It is possible to capture the video signal VIDEO corresponding to 1, S2 ... Sm. After that, the output enable signal EN
When a selection pulse is output to BL, the analog switch group ASW whose conduction state is controlled by the output enable signal
1, 2, ASW2,2 ... ASWm, 2 are rendered conductive, and the video signal sampled by the sample capacitor is transferred to the hold capacitor CHLD. At this time, since the video signal is transferred from the sample capacitor to the hold capacitor by capacitive coupling, accurate transfer cannot be performed if the voltage of the hold capacitor before transfer is different for each signal line unit. Therefore, in order to reset the hold capacitors before transfer, all the hold capacitors are reset by a reset switch group RSW1, RSW2 ... RSW3 whose conduction state is controlled by a reset signal RST, for example, a fixed voltage such as a ground voltage. Is applied in advance. Next, analog buffers B1 and B
2 ... Bm buffers and outputs the video signal transferred to the hold capacitor. When the output of the selection pulse is completed, the analog switch group becomes non-conductive, so that the hold capacitor and the sample capacitor are electrically insulated. From this state, the video signal is sampled to the sample capacity again. After that, by repeating this, it is possible to supply an arbitrary video signal to each signal line.

By using such a driving method, most of one horizontal scanning period except the period in which the selection pulse of the output enable signal is output can be used for writing the video signal to the signal line. As a result, the driving ability of the signal line driving circuit with respect to the load of the signal line or the pixel is improved, and a large area TFT with a display diagonal of 30 cm or more is displayed.
LCDs have also become feasible.

[0009]

In the conventional active matrix type liquid crystal display device, the latch signal such as the output enable signal is delayed by the electrostatic protection circuit formed on the same substrate as the pixel matrix, and the timing is accurate. There was something I couldn't decide. The static electricity protection circuit is obviously a hindrance in terms of the temporal accuracy of signals, but it is said that it protects, for example, the scanning line drive circuit and signal line drive circuit formed on the same substrate as the pixel matrix from damage due to electrostatic discharge. In terms of points, it is extremely effective. If the electrostatic protection circuit is not provided, the yield in the manufacturing process is significantly reduced.

Therefore, conventionally, a latch signal such as an output enable signal is obtained by using a signal source having a large load driving capability. Many of such signal sources have an increased current drive capability, which increases the power consumption of the device. Further, if the driving capability is excessively increased, the signal waveform is distorted, causing a problem of malfunction due to overshoot or the like. For these reasons, it is becoming difficult to guarantee the temporal accuracy of the latch signal such as the output enable signal in the latest active matrix type liquid crystal display device.

The present invention solves the above problems.

[0012]

In an active matrix type liquid crystal display device in which a pixel matrix and at least a signal line drive circuit are formed on the same substrate, the signal line drive circuit includes a sampling means for sequentially sampling a video signal. ,
The above problem is solved by using an active matrix type liquid crystal display device having a holding means for holding the video signal sampled by the sampling means and a first control means for controlling the holding means.

Further, in an active matrix type liquid crystal display device in which a pixel matrix and at least a signal line drive circuit are formed on the same substrate, the signal line drive circuit sequentially samples video signals, and the sampling means. An active matrix having holding means for holding the video signal sampled by the buffer means, buffer means for amplifying or buffering the video signal held by the holding means, and first control means for controlling the holding means. The above problem is solved by using a liquid crystal display device of the type.

Further, in the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line driving circuit are formed on the same substrate, the signal line driving circuit sequentially samples the video signal, and the sampling means. Holding means for holding the video signal sampled by the holding means, buffer means for amplifying or buffering the video signal held by the holding means, and reset means for resetting at least one of the holding means and the buffer means. The above problem is solved by using an active matrix type liquid crystal display device having a first control means for controlling the hold means and a second control means for controlling the reset means.

Further, in the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate, the signal line drive circuit includes at least sampling means for sequentially sampling the video signal,
A holding means for holding the video signal sampled by the sampling means; a buffer means for amplifying or buffering the video signal held by the holding means; and a first control means for controlling the holding means. Then, the sampling means generates sample / latch generation means for generating a latch signal that defines a timing for sampling the video signal, sample holding means for holding the video signal to be sampled, and the sampling / holding means based on the latch signal. An active matrix type liquid crystal display device comprising a sample switching means for sampling a video signal into the sample holding means, and the first control means being substantially equivalent to the sample latch generating means. By using it, the above-mentioned subject is solved.

In the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate, the signal line drive circuit includes at least sampling means for sequentially sampling the video signal,
Holding means for holding the video signal sampled by the sampling means, buffer means for amplifying or buffering the video signal held by the holding means, and intermittently the video signal amplified or buffered by the buffer means The above problem is solved by using an active matrix type liquid crystal display device having a signal line output means for supplying to the signal line of the pixel matrix.

Further, the pixel matrix and at least the signal line drive circuit are formed on the same substrate, and the signal line drive circuit includes at least sampling means for sequentially sampling the video signal and the video image sampled by the sampling means. The sampling means includes: holding means for holding a signal; buffer means for amplifying or buffering the video signal held by the holding means; and first control means for controlling the holding means. Sample / latch generation means for generating from the clock signal a latch signal that defines the timing for sampling the video signal, sample holding means for holding the video signal to be sampled, and the sampled video signal based on the latch signal. Active matrix consisting of sample switching means for sampling to capacitance Type liquid crystal display device, the frequency of the clock signal is variable, and the timing signal for controlling the holding means is an active matrix liquid crystal display device generated from the clock signal by the first control means. Solve the problem.

Further, the pixel matrix and at least the signal line driving circuit are formed on the same substrate, and the signal line driving circuit at least samples the video signals sequentially and the video signals sampled by the sampling means. A method for driving an active matrix liquid crystal display device, comprising: holding means for holding, buffer means for amplifying or buffering the video signal held by the holding means, and reset means for resetting the holding means. When the time required to hold the video signal by the means is th and the time required to reset the holding means by the reset means is tr, at least the relation of th> tr is established. Using the driving method of matrix type liquid crystal display device This solves the above problem.

Further, in the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate, the signal line drive circuit has at least sampling means for sequentially sampling the video signal,
Holding means for holding the video signal sampled by the sampling means, buffer means for amplifying or buffering the video signal held by the holding means, reset means for resetting the holding means, and resetting of the reset means The above problem is solved by using an active matrix type liquid crystal display device having a delay means for controlling the time length from the timing of ending the operation to the timing of starting the hold operation of the hold means.

Further, in the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate, the signal line drive circuit includes at least sampling means for sequentially sampling the video signal,
It has a holding means for holding the video signal sampled by the sampling means, a buffer means for amplifying or buffering the video signal held by the holding means, and a first counting means for controlling the holding means. The above problem is solved by using an active matrix type liquid crystal display device in which a control clock having a constant frequency is input to the sampling means and the first counting means.

In the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate, the signal line drive circuit includes at least sampling means for sequentially sampling the video signal,
Hold means for holding the video signal sampled by the sampling means, buffer means for amplifying or buffering the video signal held by the hold means, and reset means for resetting at least one of the hold means and the buffer means. A first counting means for controlling the holding means and a second counting means for controlling the resetting means, and the sampling means and the first counting means.
The above problem is solved by using an active matrix type liquid crystal display device to which a control clock having a constant frequency is input as the counting means and the second counting means.

In the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate, the signal line drive circuit includes at least sampling means for sequentially sampling video signals,
Hold means for holding the video signal sampled by the sampling means, buffer means for amplifying or buffering the video signal held by the hold means, and reset means for resetting at least one of the hold means and the buffer means. A delay means for controlling the time length from the timing of ending the reset operation of the reset means to the timing of starting the hold operation of the hold means, a first counting means for controlling the hold means, and the reset means. And second counting means for controlling the delay means, and third counting means for controlling the delay means,
The above problem is solved by using an active matrix type liquid crystal display device to which a control clock having a constant frequency is input as the sampling means, the first counting means, the second counting means and the third counting means.

[0023]

In the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate, the signal line drive circuit includes sampling means for sequentially sampling video signals and sampling means for sampling by the sampling means. By using an active matrix type liquid crystal display device having a holding means for holding the generated video signal and a first control means for controlling the holding means, or by using a pixel matrix and at least a signal line driving circuit. In an active matrix type liquid crystal display device formed on the same substrate, the signal line drive circuit includes sampling means for sequentially sampling video signals, holding means for holding the video signals sampled by the sampling means, and The video signal held by the holding means is amplified or Using an active matrix type liquid crystal display device having buffer means for buffering and first control means for controlling the holding means, or the pixel matrix and at least the signal line driving circuit are formed on the same substrate. In the active matrix type liquid crystal display device described above, the signal line drive circuit holds the sampling means for sequentially sampling the video signal, the holding means for holding the video signal sampled by the sampling means, and the holding means. A buffer means for amplifying or buffering the video signal, a reset means for resetting at least one of the hold means and the buffer means, a first control means for controlling the hold means, and a second control means for controlling the reset means. Of active matrix liquid crystal display having By using location, and a signal delay from the first control means from the signal delay and said second control means to said holding means to said reset means is smaller than the conventional.

In the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line driving circuit are formed on the same substrate, the signal line driving circuit includes at least sampling means for sequentially sampling the video signal,
A holding means for holding the video signal sampled by the sampling means; a buffer means for amplifying or buffering the video signal held by the holding means; and a first control means for controlling the holding means. Then, the sampling means generates sample / latch generation means for generating a latch signal that defines a timing for sampling the video signal, sample holding means for holding the video signal to be sampled, and the sampling / holding means based on the latch signal. An active matrix type liquid crystal display device comprising a sample switching means for sampling a video signal into the sample holding means, and the first control means being substantially equivalent to the sample latch generating means. By using it, the minimum arrangement of the signal line drive circuit becomes possible.

In the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line driving circuit are formed on the same substrate, the signal line driving circuit includes at least sampling means for sequentially sampling the video signal,
Hold means for holding the video signal sampled by the sampling means, buffer means for amplifying or buffering the video signal held by the holding means, and intermittently the video signal amplified or buffered by the buffer means By using an active matrix type liquid crystal display device having a signal line output means for supplying to the signal line of the pixel matrix, a high frequency component other than the video signal is not applied to the signal line.

Further, the pixel matrix and at least the signal line drive circuit are formed on the same substrate, and the signal line drive circuit includes at least sampling means for sequentially sampling video signals and the video image sampled by the sampling means. The sampling means includes: holding means for holding a signal; buffer means for amplifying or buffering the video signal held by the holding means; and first control means for controlling the holding means. Sample / latch generation means for generating from the clock signal a latch signal that defines the timing for sampling the video signal, sample holding means for holding the video signal to be sampled, and the sampled video signal based on the latch signal. Active matrix consisting of sample switching means for sampling to capacitance Type liquid crystal display device, the frequency of the clock signal is variable, and the timing signal for controlling the holding means is an active matrix liquid crystal display device generated from the clock signal by the first control means. The time required for the holding means to perform the holding operation of the video signal can be arbitrarily changed externally.

Further, the pixel matrix and at least the signal line drive circuit are formed on the same substrate, and the signal line drive circuit at least sample means for sequentially sampling the video signal and the video signal sampled by the sampling means. A method of driving an active matrix liquid crystal display device, comprising: holding means for holding, buffer means for amplifying or buffering the video signal held by the holding means, and reset means for resetting the holding means. When the time required to hold the video signal by the means is th and the time required to reset the holding means by the reset means is tr, at least a relation of th> tr is satisfied. By using the driving method of It is possible to maximize the time during which the buffer means amplifies and outputs the video signal to the signal line by effectively utilizing the normal retrace line period.

In the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate, the signal line drive circuit includes at least sampling means for sequentially sampling the video signal,
Holding means for holding the video signal sampled by the sampling means, buffer means for amplifying or buffering the video signal held by the holding means, reset means for resetting the holding means, and resetting of the reset means By using an active matrix type liquid crystal display device having a delay means for controlling the time length from the timing of ending the operation to the timing of starting the hold operation of the hold means, the reset operation and the hold operation can be performed in time. No overlapping.

In the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate, the signal line drive circuit includes at least sampling means for sequentially sampling the video signal,
It has a holding means for holding the video signal sampled by the sampling means, a buffer means for amplifying or buffering the video signal held by the holding means, and a first counting means for controlling the holding means. By using an active matrix type liquid crystal display device in which a control clock having a constant frequency is input to the sampling means and the first counting means, or the pixel matrix and at least the signal line driving circuit are provided on the same substrate. In the formed active matrix type liquid crystal display device, the signal line drive circuit includes at least sampling means for sequentially sampling video signals, and holding means for holding the video signals sampled by the sampling means.
Buffer means for amplifying or buffering the video signal held by the holding means, reset means for resetting at least one of the holding means and the buffer means, and first counting means for controlling the holding means,
Second counting means for controlling the reset means,
By using an active matrix type liquid crystal display device in which a control clock having a constant frequency is input to the sampling means, the first counting means and the second counting means, or by using a pixel matrix and at least a signal line driving circuit. In the active matrix type liquid crystal display device in which is formed on the same substrate, the signal line drive circuit has at least sampling means for sequentially sampling video signals, and holding means for holding the video signals sampled by the sampling means, Buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting at least one of the hold means and the buffer means, and the hold means from the timing of ending the reset operation of the reset means Timing to start the hold operation of Delay means for controlling the time length until the delay, first counting means for controlling the holding means, second counting means for controlling the reset means, and third counting means for controlling the delay means. By using an active matrix type liquid crystal display device in which a control clock having a constant frequency is input to the sampling means, the first counting means, the second counting means and the third counting means,
The scale of the circuit that generates the control clock can be reduced.

[0030]

Embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a diagram for explaining an example of a signal line drive circuit of an active matrix panel which constitutes an active matrix type liquid crystal display device using the first embodiment. The signal line driver circuit is formed over the same substrate as the pixel matrix.

The shift register SR transfers the selection signal XIN to each bit output of Bit1, Bit2 ... Bitm, and sample switch groups SW1, 1, SW2, 1 ... S.
Provided to turn on / off Wm, 1 in time series. A level shifter LS is interposed between the shift register and the sample switch group, and the level shifter turns on and off the voltage level or the current level of the bit output of the shift register. Used to raise or lower to a level sufficient to do so. However, if the bit output of the shift register is at a level sufficient to turn on / off the sample switch group, the level shifter is unnecessary. When the sample switch group is turned on and off in time series, the video signal VIDEO has a sample capacitance of C1,1, C2,1 ...
Sequentially sampled to Cm, 1 and the sample capacitor holds a voltage value corresponding to the video signal. At this time, hold switch groups SW1,2, SW2,2 provided between the sample capacitor and the hold capacitors C1,2, C2,2 ... Cm, 2
..SWm, 2 is turned off based on the control signal from the hold switch control circuit. The voltage value held in the sample capacitor finally becomes the analog buffer B1,
B2 ... Signal line S amplified or buffered by Bm
1, S2 ... Sm, but this process is significantly different between the conventional technology and the present invention.

According to the prior art shown in FIG. 4, the TFT-L
Output enable signal EN supplied from outside the CD panel
As BL is input, the voltage value held in the sample capacitor CSPL is transferred to the hold capacitor CHLD, and the analog buffers B1, B2 ... Bm amplify or amplify the voltage value transferred to the hold capacitor. Buffer and output to signal line. On the other hand, in the present invention, the signal corresponding to the output enable signal ENBL can be generated inside the active matrix panel without requiring a complicated circuit configuration. Hereinafter, the description of the present invention will be continued using FIG. 1 again.

As described above, the sample volumes C1, 1, C
It is assumed that a voltage value corresponding to the video signal is continuously held in 2,1, ... Cm, 1. The control clock CLK for controlling the shift operation of the shift register SR is simultaneously supplied with the output switch control circuit 101 and the reset switch control circuit 10.
2 and the hold switch control circuit 103,
The timings of the output signals of these three control circuits are controlled. These three control circuits have a circuit configuration equivalent to that of the shift register, and further have a circuit configuration in which an arithmetic circuit and the like are combined as necessary. Specific circuit configurations of these three control circuits will be described later. The shift register transfers the selection signal XIN to each bit output of Bit1, Bit2 ... Bitm in synchronization with the control clock CLK, and then transfers the selection signal to the output switch control circuit 101. At this time, from the output switch control circuit, output switch groups SW1,3, SW2,3 ... SWm,
A control signal for turning off 3 is output, and the output terminals of the analog buffers B1, B2 ... Bm and the signal lines S1, S2
... Sm is electrically insulated.

Next, in synchronization with the control clock CLK, the output switch control circuit resets the switch control circuit 1
The selection signal is transferred to 02. At this time the reset
From the switch control circuit, the first reset switch group SW1,4, SW2,4 ... SWm, 4 and the second reset switch group SW1,4, SW2,4 ...
A control signal for turning on the switch groups SW1,5, SW2,5 ... SWm, 5 is output. The first reset switch group is provided so as to control the conduction state between the reset signal line RS and the hold capacitor and the input terminal of the analog buffer. Further, the second reset switch group is provided so as to control the conduction state between the reset signal line and the output terminal of the analog buffer. When the first reset switch group is turned on, the voltage value applied to the reset signal line is written to the hold capacitor almost instantly, and the hold capacitor is reset to the voltage value. At the same time, the input terminal of the analog buffer directly connected to the hold capacitor is also reset to the voltage value. When the second reset switch group is turned on, the voltage value applied to the reset signal line is written in the output terminal of the analog buffer,
The output terminal of the buffer is reset to the voltage value. The reason why the output terminal as well as the input terminal of the analog buffer is reset is to stabilize the output at a speed higher than the slew rate of the analog buffer.

After the hold capacitors and the input / output terminals of the analog buffer are reset, the selection signal is then sent from the reset switch control circuit 102 to the hold switch control circuit 103 in synchronization with the control clock. Transferred. At the same time, the reset switch control circuit outputs a control signal for turning off the first reset switch group and the second reset switch group. Further, the hold switch control circuit outputs a control signal for turning on the hold switch groups SW1,2, SW2,2 ... SWm, 2. Along with this, the hold switch group becomes conductive, and the sample capacitors C1,1, C2,1 ... C.
The voltage value held in m, 1 is the hold capacitance C2,1, C2,2.
..Transfer to Cm, 2 almost instantly. The voltage value transferred to the hold capacitor is amplified or buffered by the analog buffer and output from the analog buffer.

Next, the selection signal is transferred from the hold switch control circuit to the output switch control circuit in synchronization with the control clock. At this time, the hold switch control circuit outputs a signal for turning off the hold switch group, and ends the transfer of the voltage value from the sample capacitance to the hold capacitance. On the other hand, the output switch control circuit outputs a control signal for turning on the output switch group.
As a result, the output terminal of the analog buffer is connected to the signal line, and the voltage value amplified or buffered by the analog buffer is output to the signal line. The period until the output switch control circuit outputs the off control signal again, that is, the shift register outputs the new selection signal XI.
The output terminal of the analog buffer and the signal line are electrically connected until N is transferred to each bit of Bit1, Bit2 ... Bitm, and a new video signal VIDEO is sequentially sampled in the sample capacity. The connected state is maintained, and the signal writing to the signal line is continued. By repeating the above operation, an arbitrary video signal can be transferred to each signal line, and an image can be displayed on the active matrix type liquid crystal display device.

By using the present invention, it is not necessary to generate a control signal corresponding to the output enable signal ENBL for controlling the timing of transferring the voltage value from the sample capacitor to the hold capacitor outside the TFT-LCD panel. Therefore, the number of mounting terminals used for connecting the TFT-LCD panel and an external circuit can be reduced, which has advantages such as a reduction in the number of mounting steps and an improvement in yield at the time of mounting. In addition, the output switch control circuit, the reset switch control circuit, and the hold switch control circuit have a circuit configuration equivalent to that of the shift register, or include many parts having an equivalent circuit configuration. Most of these three control circuits can be designed by simply increasing the number of bits in the shift register. Therefore, the layout area of the circuit can be minimized and the TFT-LCD panel can be narrowed. Moreover, since the design addition is greatly reduced compared to the case where a special circuit configuration is added, it is possible to remove the cause of the design error in advance. Further, in the conventional method of supplying the output enable signal from the mounting terminal, an electrostatic protection circuit for preventing circuit destruction due to static electricity is often provided near the mounting terminal on the TFT-LCD panel, but the electrostatic protection circuit is extremely large. It usually has a parasitic capacitance, which inevitably delays the output enable signal. On the other hand, according to the present invention, since the electrostatic protection circuit is unnecessary, the output enable signal without delay can be obtained. As a result, the timing of signal transfer from the sample capacity to the hold capacity is accurately determined, and it is possible to reliably prevent the erroneous signal from being captured.

Further, in the present invention, the output of the analog buffer is intermittently applied to the signal line by using the output switch group and the output switch control circuit. This is provided so that the voltage of the reset signal line is not applied to the signal line when the output of the analog buffer is reset by the second reset switch group. In the case of the conventional signal line drive circuit, the signal line is also reset, so that an unnecessary high frequency is superimposed on the signal line. In the present invention, since only the video signal can be applied to the signal line by the function of the output switch group and the output switch control circuit, it is possible to suppress the domain generation due to the abnormal orientation of the liquid crystal enclosed near the signal line, It is possible to realize an active matrix type liquid crystal display device having a high contrast ratio without light leakage from the domain. Further, it is possible to prevent the signal line output unit from unnecessarily charging and discharging the parasitic capacitance of the signal line by the buffer unit, so that the power consumption of the signal line drive circuit can be reduced.

Hereinafter, the first embodiment of the present invention will be described more specifically. First, a case where the shift register SR of FIG. 1 is configured by the D-flip-flop shown in FIG. 5A will be described. FIG. 6 shows a portion 10 of FIG.
6 is a diagram illustrating an example of a specific circuit configuration of No. 6; FIG. Terminal 6
01 is a terminal for inputting a selection signal transferred from the shift register SR of FIG. The wiring 602 is the first line in FIG.
Reset switch group SW1,4, SW2,4 ... SWm,
4 and second reset switch group SW1,5, SW2,5
..Wiring connected to the control terminals of SWm, 5. The wiring 603 is a hold switch group SW1, 2, SW of FIG.
2,2 ... Wirings connected to the control terminals of SWm, 2.
The wiring 604 is the output switch group SW1,3, SW2,3 of FIG.
... A wiring connected to the control terminal of SWm, 3.
A level shifter LS may be interposed between the wirings 602, 603 and 604 and each of the switch groups to raise or lower the voltage level or the current level. The output switch control circuit 101 has a D-
Flip-flops 605 and 607 and resettable D
It consists of a flip-flop 606 and a NOR gate 608. The reset switch control circuit 102 and the hold switch control circuit 103 are composed of D-flip-flops themselves. In this embodiment, the D-flip-flop synchronized with the control clock CLK is 605 → 1.
The order is 02 → 103 → 607, and it is clear that this circuit configuration is equivalent to the circuit configuration of the shift register in FIG.

Next, the operation of the circuit shown in FIG. 6 will be described with reference to the timing chart shown in FIG. FIG. 1 is also used in the following description.

First, in the horizontal scanning period 801, excluding the horizontal blanking period 802, the shift register SR shown in FIG. 1 is sequentially set to Bit1, Bi in synchronization with the control clock CLK.
t2 ... Outputs a selection pulse to each bit of Bitm. At this time, as described above, the signal corresponding to the video signal is sampled in the sample capacity provided for each bit. On the other hand, the selection pulse output to the m-th bit Bitm is also input to the terminal 601 at the same time.

[Period 803] Receiving the selection pulse, the output terminal Q (point P61) of the D-flip-flop 605 outputs a high level voltage during the next one clock of the control clock. This is input to the clock terminal CK of the D-flip-flop 606, and the D-flip-flop 606
The output terminal Q (point P65) of is changed from the low level to the high level. Here, the D-flip-flop 606
Is a 1-bit counter, the pulse signal is input to the clock terminal CK (point P61) again,
Alternatively, this state is maintained until a high level signal is input to the reset terminal R. Well, NOR
The gate 608 receives the high-level signal at the point P65 and outputs the low-level signal to the wiring 604 (point P66). Thus, in the period 803, the analog signal of FIG.
The output switches SW1,3, SW2,3, ... To do so.

[Period 804] During the next one clock of the control clock, the output terminal Q (point P62) of the D-flip-flop also serving as the reset switch control circuit 102 and the wiring 602 are at the high level, and the first The reset switch group SW1,4, SW2,4 ... SWm, 4 and the second reset switch group SW1,5, SW2,5 ... SWm, 5 are in a conductive state. Thus, in the period 804, the input / output terminals of the analog buffer group and the hold capacitors C1, 2, C
2,2 ... Cm, 2 are reset to the voltage level of the reset signal line RS. Simultaneously with the end of the period 804, the output terminal Q of the D flip-flop also serving as the reset switch control circuit 102 becomes low level, and the first reset switch group and the second reset switch group are in non-conduction state. Becomes

[Period 805] During the next one clock of the control clock, the output terminal Q (point P63) of the D-flip-flop also serving as the hold switch control circuit 103 and the wiring 603 are at the high level, and the hold switch. The groups SW2,1, SW2,2 ... SWm, 2 are brought into conduction.
As a result, a signal is transferred from the sample capacitors C1,1, C2,1 ... Cm, 1 to the hold capacitor, and each analog buffer amplifies or buffers the signal and outputs it from the output terminal. Thus, in the period 805, a signal is written in the hold capacitor and the output of the analog buffer is stabilized. Simultaneously with the end of the period 805, the output terminal Q of the D-flip-flop which doubles as a hold switch control circuit.
Becomes a low level, and the hold switch group becomes non-conductive. This electrically insulates the sample capacitance from the hold capacitance, and the hold capacitance continues to hold the voltage value at the end of the period 805 until the first reset switch group is opened again.

[Period 806] During the next one clock of the control clock, the output terminal Q of the D-flip-flop 607.
(Point P64) becomes high level, and the high level is input to the reset terminal R of the resettable D-flip-flop 606 connected to the output terminal, so that the resettable D-flip-flop is reset and the output terminal Q (point P65) outputs a low level. At this time, the two input terminals of the NOR gate, that is, point P64 and point P
65 is high level and low level respectively, and the output (point P66) is still low level,
The output switch group remains off.

At the same time that the clock next to the control clock is input, the output terminal Q of the D-flip-flop (point P
64) goes low, the two input terminals of the NOR gate both go low, and the output (point P66)
Becomes a high level. As a result, the output switch group becomes conductive, and the signal held in the hole capacitance is amplified or buffered and output from the analog buffer to the signal line.

When the horizontal retrace period 802 ends after the above series of operations is completed, the series of operations starting from the sampling of the video signal by the shift register is repeated.
As described above, the latch signal for controlling each switch group can be obtained inside the signal line drive circuit of the active matrix type liquid crystal display device.

In the timing chart of FIG.
The length of each period from 03 to 806 is different. This is because the time required to complete the above-described operation in each period is different. In a general video signal, the horizontal erasing period 802 is only about 20% of the horizontal scanning period 801, so that it is necessary to effectively distribute each of the above periods within the horizontal blanking period. In the period 804, since the input / output capacitance of the analog buffer and the hold capacitance are charged / discharged to the voltage level applied to the reset signal line, the period 804 takes the longest time among these periods 803-806. . Next, it takes a period 805, and in the period 805, the video signal is transferred from the sample capacitor to the hold capacitor. Since the transfer is performed by capacitive coupling through the hold switch group, it can be shorter than at least the period 804. Period 80
If 5 is too short, the transfer may not be performed sufficiently and may cause a problem in terms of accuracy, so some time is required depending on the accuracy required. On the other hand, in the period 803, only the time for turning off the output switch group is required, and in the period 806, only the time for turning on the output switch group is required. In the periods 803 and 806, a margin may be taken for the delay of the output switch control circuit,
The time may be shorter than the period 805. From these, at least the relationship of period 804> period 805 is established, and further period 804> period 805> period 803≈period 806.
The relationship holds. It can be considered that this relationship is not an absolute condition but a condition that minimizes the time allocated to the periods 803 to 806. In other words, satisfying the above condition means that the output switch is in the ON state for the longest time.
This has the advantage that the signal lines can be sufficiently written by the analog buffer group.

The time of each of the above-mentioned periods varies depending on the active matrix type liquid crystal display device having different specifications. Here, the timing of each period is variably controlled by making the frequency of the control clock variable. In this case, only the circuit for generating the control clock needs to be variable, the versatility of the external circuit is enhanced, and the manufacturing cost of the active matrix liquid crystal display device is reduced.

Next, the shift register SR shown in FIG.
The case where the clocked inverter and the AND gate shown in (b) are used will be described. FIG. 9 is a diagram illustrating an example of a specific circuit configuration of the portion 106 of FIG. The terminal 901 is a terminal that receives a transfer signal from the shift register SR. The wiring 902 is a wiring that connects the reset switch control circuit 102 to the control terminals of the first reset switch group and the second reset switch group. A wiring 903 is a wiring that connects the hold switch control circuit 103 and the control terminal of the hold switch group. The wiring 904 is a wiring that connects the output switch control circuit 101 and the control terminal of the output switch group. Reference numerals 904 and 905 represent N-type thin film transistors. All clocked inverters in the figure operate only when the control signal is at a high level. In the example of FIG. 9, these three control circuits are mainly composed of clocked inverters, and among them, the reset switch control circuit and the hold switch control circuit are the same as those of the shift register shown in FIG. It can be seen that it is equivalent to the circuit configuration. Functionally, it is almost the same as the circuit shown in FIG.

Next, the circuit operation will be briefly described with reference to the timing chart shown in FIG. In order to drive the clocked inverter type shift register and the control circuit as shown in FIG. 9, the control clock CLK and the control clock CL having an exclusive logic relationship with the control clock CLK.
Since K * is required, it is assumed here that the control clock CLK * is obtained in advance by taking the exclusive logic of the control clock CLK using an inverter or the like.

First, immediately before entering the horizontal blanking period 802, the selection signal of the m-th bit Bitm is input to the terminal 901.

[Period 121] When entering the horizontal scanning period 802, the control clock CLK becomes high level, the clocked inverter controlled by the control clock CLK operates, and the selection signal goes to points P91 and P92. And transferred. The point P92 becomes high level and the clocked inverter 908 operates as an inverter. At this time point P92
Is a high level, the N-type thin film transistor 905
Is in the conductive state, and the point P99 is fixed to the ground voltage (low level). Since the point P91 is at the low level, the clocked inverter 907 does not function as an inverter. Therefore, the clocked inverter 90
The point P98, which is the output terminal of No. 3, goes high. N
Point P98 connected to the input terminal of the OR gate 909
Is high, the NOR gate outputs a low level. As a result, the output switch group connected to the wiring 904 is turned off.

[Period 122] Next, when the control clock CLK becomes low level, the reset switch control circuit 10
2 outputs a high level to the point P93, and the first reset switch group and the second switch group are turned on. Thus, similarly to the above, the hold capacitors and the output terminals of the analog buffer group are applied with the voltage of the reset signal line and reset.

[Period 123] Next, when the control clock CLK becomes the high level again, the hold switch control circuit 103 outputs the high level to the point P94, and the hold switch group is turned on. At the same time, the first reset switch group and the second reset switch group are turned off, and the voltage value held in the sample capacitor is transferred to the hold capacitor. On the other hand, in the output switch control circuit, the point P91 becomes high level,
The clocked inverter 907 starts the inverter operation. Since both clocked inverters 907 and 908 operate as inverters, points P98 and P99, which are the input / output terminals, are high level and low level, respectively.
Stabilize at the level.

[Period 124] Next, when the control clock CLK becomes low level again, the point P95 becomes low level, the gate terminal of the N-type thin film transistor 906 becomes high level, and the N-type thin film transistor becomes conductive. Becomes At this time, at the same time, the clocked inverter 90
Since point 8 does not function as an inverter, point P98 is fixed to the ground voltage (low level). Since the input terminal (point P96) of the NOR gate 909 is at high level at this point, the output of the NOR gate (point P97) remains at low level.

Next, when the control clock CLK becomes high level again, the point P95 becomes high level and the point P96.
Becomes low level. When the point P95 becomes high level, the clocked inverter 908 starts the inverter operation and keeps the point P98 fixed at low level. Well, N
Two input terminals of OR gate 909, points P96 and P9
Since both 8 are at low level, the NOR gate outputs high level to the wiring 904 (point P97). In this way, the output switch group is turned on, and the analog
The output of the buffer group can be written to the signal line.

An arbitrary video signal can be written in each signal line by performing the above series of operations every horizontal scanning period.

Here, the high level / low level used in the description of the present text refers to the voltage level corresponding to the correctness / erroneousness of the circuit logic operation. Further, the plurality of switch groups described above are N-type thin film transistor analog switches, etc., which are conductive (ON) when the control signal is at a high level and are insulated (OFF) when the control signal is at a low level. Is assumed.

Next, a specific circuit configuration of the portion 107 of FIG. 1 including each switch group, analog buffer, etc. will be described. FIG. 7 is a diagram illustrating a specific configuration of the portion 107 of FIG. Sample switch group SW1, in the figure
1, SW2,1 ... and hold switch group SW1,2, S
W2,2 ... and output switch group SW1,3, SW2,3 ...
Is composed of a bi-complementary transfer gate composed of a thin film transistor. Further, in the figure, the first reset switch group SW1,4, SW2,4 ... And the second reset switch group SW1,5, SW2,5 ... are composed of analog switches composed of N-type thin film transistors. Has been done. The sample switch group, the hold switch group, the first reset switch group, and the second reset switch group and the output switch group are dual-complement transfer switches.
It may be composed of any of a gate, an N-type thin film transistor, and a P-type thin film transistor. Also, these are all
It may be configured by a rectifying element such as a thin film diode.

In the above description of the first embodiment, the shift register, the sample switch group, and the sample capacitance are shown as the sampling means, and the hold switch group and the hold capacitance are shown as the hold means. An output switch control circuit, a hold switch control circuit, and a sample switch control circuit are shown as the control means for controlling the hold means. From these, in the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate, the signal line drive circuit includes a sampling means for sequentially sampling the video signal and a sampling means for sampling by the sampling means. It can be said that the present invention is characterized by having a holding means for holding the generated video signal and a first control means for controlling the holding means.

In the above description of the first embodiment, the analog buffer is shown as the buffer means. From these, in the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate, the signal line drive circuit includes a sampling means for sequentially sampling the video signal and a sampling means for sampling by the sampling means. The present invention has a holding means for holding the generated video signal, a buffer means for amplifying or buffering the video signal held by the holding means, and a first control means for controlling the holding means. It can be said that this is a feature of the invention.

According to the present invention, the control signal generated by the control means is transmitted to the holding means and the sampling means with almost no delay, so that an erroneous signal is prevented from being captured. Further, since the control signal is generated on the same substrate by the control means and does not need to be supplied from outside the same substrate, the number of mounting terminals can be reduced. This has the effect of reducing the number of mounting steps and improving the yield in the mounting steps.

In the above description of the first embodiment, the reset switch group and the reset signal line are shown as the reset means. From these, in the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate, the signal line drive circuit includes a sampling means for sequentially sampling the video signal and a sampling means for sampling by the sampling means. Holding means for holding the generated video signal, buffer means for amplifying or buffering the video signal held by the holding means, reset means for resetting at least the holding means or one of the buffer means, and the hold It can be said that the present invention has the first control means for controlling the means and the second control means for controlling the reset means. According to the present invention, the control signal generated by the control means is transmitted to the sampling means, the holding means, and the reset means with almost no delay, so that an erroneous signal is prevented from being captured. Further, conventionally, the control signal of the reset means and the control signal of the hold means may temporally overlap each other due to the delay of the control signal, and the reset signal leaks to the video signal transferred to the hold means. There was an occasion. In the present invention, since there is almost no delay in the control signal, it is possible to prevent the reset signal from leaking.

Further, in the above description of the first embodiment, a shift register is shown as sample / latch generating means for generating a latch signal that defines the timing for sampling the video signal, and the sampled video signal is held. The sample capacitance is shown as the sample holding means, and the bi-complement type transfer gate is shown as the sample switching means for sampling the video signal to the sample holding means based on the latch signal. From these, in the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line driving circuit are formed on the same substrate, the signal line driving circuit includes at least sampling means for sequentially sampling the video signal, and the sampling means. Holding means for holding the sampled video signal, buffer means for amplifying or buffering the video signal held by the holding means, and first holding means for controlling the holding means.
And a sampling holding means for generating a latch signal defining a timing for sampling the video signal, and a sample holding means for holding the video signal to be sampled. Sample switching means for sampling the video signal to the sample holding means on the basis of the latch signal.
It can be said that the feature of the present invention is that the control means of (1) is composed of means substantially equivalent to the sample / latch generation means. According to the present invention, since the control means can be constructed by increasing the number of output bits of the sample / latch generation means, the circuit layout area can be minimized, and the active matrix type liquid crystal display device can be narrowed. .. There is also an advantage that the factor of design mistake can be reduced as compared with the case where the control means is designed with a completely different configuration from the sample latch generation means.

In the description of the first embodiment, the output switch group is used as the signal line output means for intermittently supplying the video signal amplified or buffered by the buffer means to the signal line of the pixel matrix. And an output switch control circuit. From these, in the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line driving circuit are formed on the same substrate, the signal line driving circuit includes at least sampling means for sequentially sampling the video signal, and the sampling means. Hold means for holding the sampled video signal, buffer means for amplifying or buffering the video signal held by the holding means, and intermittently the pixel matrix for the video signal amplified or buffered by the buffer means It can be said that the present invention has a signal line output means for supplying the signal line to the signal line. According to the present invention, a high-frequency component other than the video signal is not applied to the signal line, so that the alignment state of the liquid crystal sealed in the vicinity of the signal line is not unnecessarily changed. Therefore, it is possible to suppress the generation of liquid crystal domains due to abnormal alignment and prevent light leakage due to the domains, and thus it is possible to realize an active matrix type liquid crystal display device with high image quality. Further, it is possible to prevent the capacitance parasitic on the signal line from being unnecessarily charged / discharged by the buffer means, so that the power consumption of the active matrix type liquid crystal display device can be reduced because the signal line output means can be prevented. .

In the above description of the first embodiment, the sample latch signal output from the sample control circuit is shown as the timing signal for controlling the sampling means, and the hold signal is shown as the timing signal for controlling the holding means. The hold / latch signal output from the control circuit is shown. From these, the pixel matrix and at least the signal line driving circuit are formed on the same substrate, and the signal line driving circuit at least samples the video signal sequentially and the video signal sampled by the sampling means. Holding means for holding, buffer means for amplifying or buffering the video signal held by the holding means, and first control means for controlling the holding means, and the sampling means includes the video signal Sample / latch generating means for generating from the clock signal a latch signal defining the timing of sampling, sample holding means for holding the video signal to be sampled, and the video signal to the sample capacitance based on the latch signal. Active matrix liquid composed of sample switching means for sampling In the display device, the clock signal is a frequency variable, it can be said that the timing signal for controlling the holding means by the first control means to be generated from the clock signal, which is a feature of the present invention. According to the present invention, the hold timing can be changed only by changing the frequency of the clock signal. When the signal line driving circuit of the present invention is used, the external circuit can be shared by the active matrix type liquid crystal display devices having different specifications, so that the manufacturing cost of the external circuit can be reduced. Also,
Even in the active matrix type liquid crystal display device having the same specifications, it is possible to compensate for the timing shift due to the variation of the characteristics by the external circuit, and it is possible to remedy the defective product in the past.

Further, in the above description of the first embodiment, the period 805 and the period 123 are reset as the time th required to hold the video signal by the hold means, and the hold means is reset by the reset means. The period 804 and the period 122 are shown as the time tr required for. From these, the pixel matrix and at least the signal line drive circuit are formed on the same substrate, and the signal line drive circuit holds at least the sampling means for sequentially sampling the video signal and the video signal sampled by the sampling means. A method for driving an active matrix liquid crystal display device, comprising: holding means; buffer means for amplifying or buffering the video signal held by the holding means; and reset means for resetting the holding means, Driving an active matrix type liquid crystal display device in which at least a relation of th> tr is satisfied, where th is a time required to hold the video signal and tr is a time required to reset the holding means by the reset means. It can be said that the method is a feature of the present invention. It According to the present invention, the horizontal blanking period can be effectively used, and the time during which the buffer means amplifies and outputs the video signal to the signal line can be maximized. Therefore, the video signal is sufficiently written in the signal line, and a high-contrast active matrix type liquid crystal display device can be realized.

(Second Embodiment) FIG. 11 is a diagram for explaining an example of a signal line driving circuit of an active matrix panel which constitutes an active matrix type liquid crystal display device using the second embodiment. FIG. 11 shows a circuit corresponding to the portion 106 of FIG. Therefore, in the second embodiment,
Assuming that only the portion 106 in FIG. 1 is replaced with the circuit in FIG. 11, FIG. 1 will be used together in the description. The signal line driver circuit is formed on the same substrate as the pixel matrix.

In this figure, a delay circuit 112 is provided between the reset switch control circuit 102 and the hold switch control circuit 103. The delay circuit is
The switch group and the hold switch group are turned on at the same time,
This is provided in order to prevent the phenomenon that the voltage level applied to the reset signal line continues to leak to the hold capacitor and the video signal is not accurately transferred from the sample capacitor to the hold capacitor. When the circuit described in the first embodiment functions as designed, the reset switch group and the hold switch group do not turn on at the same time, but such a phenomenon rarely occurs. For example, the reset
When the control signal output from the reset switch control circuit is delayed due to variations in the characteristics of the thin film transistors forming the switch control circuit, the reset switch group is turned off and the hold switch is turned off.
Since the switch groups are turned on almost at the same time, these timings may overlap. In addition, such a phenomenon is also observed when the delay from the reset switch control circuit to the reset switch group is larger than the delay from the hold switch control circuit to the hold switch group. Therefore, in the second embodiment, the provision of the delay circuit 112 prevents at least the reset switch group and the hold switch group from being turned on at the same time.

In FIG. 11, the delay circuit is controlled by the control clock CLK, but it does not necessarily have to be controlled by the control clock. For example, when a CR integrating circuit is used as the delay circuit, it is not necessary to connect the control clock.

Next, an example of a concrete circuit configuration of the second embodiment will be described with reference to FIGS. 12 and 13. FIG.
2 is a diagram illustrating a specific circuit configuration of the delay circuit 112 when a D-flip-flop is used as the shift register (see FIG. 5A). FIG. 13 is a timing chart explaining the operation of FIG. The delay circuit 112 in FIG. 12 is composed of a D-flip-flop, and has a configuration substantially equivalent to the shift register, the reset switch control circuit, the hold switch control circuit, and the output switch control circuit. From the view of the circuit configuration of the output bit unit of the shift register, it can be seen that the delay circuit can be realized by adding only 1 bit to the circuit of FIG. Therefore, the narrowing of the signal line drive circuit can be realized as in the first embodiment. Further, there is no increase in the load at the design stage caused by adding the delay circuit, and the factor such as a design error can be removed in advance.
From an operation point of view, as can be seen by comparing FIG. 13 and FIG. 8, a period 323 in which the reset switch group is in the ON state (corresponding to the period 804 in FIG. 8) and a hold switch group. A delay period 324 by the delay circuit is provided between a period 325 in which is on (corresponding to the period 805 in FIG. 8). When the delay period 324 is sufficiently long compared to the time when the reset switch group shifts from the ON state to the OFF state, the reset switch group and the hold switch group do not turn ON at the same time. As a result, the video signal is accurately transferred from the sample capacitor to the hold capacitor, so that a highly accurate signal line drive circuit can be realized.

Further, an example of a concrete circuit configuration of the second embodiment will be described with reference to FIGS. 14 and 15. FIG. 14 shows a delay circuit 11 when a clocked inverter is mainly used as a shift register (see FIG. 5B).
It is a figure explaining the concrete circuit structure of No. 2. FIG. 15 is a timing chart for explaining the operation of FIG. The delay circuit 112 of FIG. 14 is mainly composed of a clocked inverter, and has a configuration substantially equivalent to the shift register, the reset switch control circuit, the hold switch control circuit, and the output switch control circuit. From the configuration of the output bit unit of the shift register, it can be seen that the delay circuit can be realized by adding only 1 bit to the circuit of FIG. Therefore, the narrowing of the signal line drive circuit can be realized as in the first embodiment. Further, there is no increase in the load at the design stage caused by adding the delay circuit, and the factor such as a design error can be removed in advance. From an operation point of view, as can be seen by comparing FIG. 15 and FIG. 10, a period 513 (corresponding to the period 122 in FIG. 10) in which the reset switch group is in the ON state, and a hold switch group. A delay period 514 provided by the delay circuit is provided between the period 515 in which is on (corresponding to the period 123 in FIG. 10). When the delay period 514 is sufficiently longer than the time when the reset switch group shifts from the ON state to the OFF state, the reset switch group and the hold switch group do not turn ON at the same time. As a result, the video signal is accurately transferred from the sample capacity to the hold capacity.
A highly accurate signal line drive circuit can be realized.

In the above description of the second embodiment, the delay circuit is shown as the delay means. From these, in the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line driving circuit are formed on the same substrate, the signal line driving circuit includes at least sampling means for sequentially sampling the video signal, and the sampling means. Hold means for holding the sampled video signal, buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting the hold means, and reset operation of the reset means are completed. It can be said that a feature of the present invention is to have a delay unit that controls the time length from the timing to the timing when the hold operation of the hold unit is started. According to the present invention, the period in which the reset unit performs the reset operation and the period in which the hold unit performs the hold operation do not overlap with each other, and the video signal can be transferred from the sample unit to the hold unit with high accuracy. It is possible to realize an active matrix type liquid crystal display device having an excellent gradation resolution display capability.

(Third Embodiment) FIG. 16 is a diagram for explaining an example of a signal line drive circuit of an active matrix panel which constitutes an active matrix type liquid crystal display device using the third embodiment. FIG. 16 shows a circuit corresponding to the portion 106 of FIG. Therefore, in the third embodiment,
1 will be used together in the description, assuming that only the portion 106 of FIG. 1 is replaced with the circuit of FIG. The signal line driver circuit is formed on the same substrate as the pixel matrix.

Although the main part of the circuit configuration is the same as in FIG. 11 used in the description of the second embodiment, the control signal for controlling the reset switch control circuit, the delay circuit and the hold switch control circuit is the control clock. Counting circuits 610, 611, 61 for counting CLK by a set number
Supplied from 2. In the first and second embodiments, the operating time of each control circuit is controlled by changing the frequency of the control clock, but in the third embodiment, this control clock CLK is the shift register. Is a constant frequency that is equal to the frequency at which the control clock is operated.
Controls the operating time of each control circuit. The count end set number of the count circuit can be obtained, for example, by a method of providing a ROM of several bits in parallel with the count circuit or a method of supplying data of several bits from an external circuit through a mounting terminal. In the figure, the count circuits 610, 611, 612
The arrow on the upper side of represents the count start signal, and the arrow on the right side represents the reset signal.

By providing the count circuit between the control clock and each control circuit, the control clock need not be variable. Since the clock generation circuit of the external circuit only needs to be an oscillation circuit of a constant frequency, the circuit configuration becomes simpler, and it is possible to generate a highly accurate control clock. In addition, cost reduction and power saving can be achieved by reducing the circuit scale around the clock generation circuit.

Next, an example of a concrete circuit configuration of the third embodiment will be described. FIG. 17 shows the shift register D
-When using a flip-flop (see FIG. 5B)
FIG. 17 is a diagram illustrating a specific circuit configuration of a portion 106 of FIG. FIG. 18 is a diagram for explaining the operation of the circuit of FIG. The count circuit 610 is the output switch control circuit 1
The D-flip-flop 715 of 01 receives the high level output, and starts to count the control clock CLK. The counting circuit 610 counts the control clock until it reaches a set number, and then outputs a clock to the clock terminal CK of the D-flip-flop that functions as the reset switch control circuit 102, and the reset switch control circuit 102 resets. A high level signal for turning on the switch group is output to the wiring 712. Similarly, the output from the count circuit 611 is the clock terminal CK of the D-flip-flop that functions as the delay circuit 112.
And the output from the count circuit 612 is input to the clock terminal CK of the D-flip-flop that functions as the hold switch control circuit 103. Thus
A period 813 in which the reset switch control circuit turns on the reset switch group, a period 814 delayed by the delay circuit, and a period 815 in which the hold switch control circuit turns on the hold switch group, Can be controlled by each set count number of the count circuits 610, 611, 612.

In the third embodiment, the counting circuit 612 is shown as the first counting means, the counting circuit 610 is shown as the second counting means, and the counting circuit 611 is shown as the third counting means. From these, in the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line driving circuit are formed on the same substrate, the signal line driving circuit includes at least sampling means for sequentially sampling the video signal, and the sampling means. The sampling means includes holding means for holding the sampled video signal, buffer means for amplifying or buffering the video signal held by the holding means, and first counting means for controlling the holding means. It can be said that the present invention is characterized in that an active matrix type liquid crystal display device to which a control clock having a constant frequency is input is used as the first counting means.

Alternatively, in an active matrix type liquid crystal display device in which a pixel matrix and at least a signal line drive circuit are formed on the same substrate, the signal line drive circuit has at least sampling means for sequentially sampling video signals, and the sample means. Holding means for holding the video signal sampled by the holding means, buffer means for amplifying or buffering the video signal held by the holding means, and reset means for resetting at least one of the holding means and the buffer means, It has a first counting means for controlling the holding means and a second counting means for controlling the resetting means, and the sampling means, the first counting means and the second counting means have a constant value. Using an active matrix liquid crystal display device to which a frequency control clock is input , It can be said to be characteristic of the present invention.

Alternatively, in the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate, the signal line drive circuit has at least sampling means for sequentially sampling the video signal, and the sample means. Holding means for holding the video signal sampled by the means, buffer means for amplifying or buffering the video signal held by the holding means, and reset means for resetting at least one of the holding means or the buffer means, Delay means for controlling the time length from the timing of ending the reset operation of the reset means to the timing of starting the hold operation of the hold means, a first counting means for controlling the hold means, and a control for the reset means Control the second counting means and the delay means. A third counting means for, the,
It is a feature of the present invention that an active matrix type liquid crystal display device to which a control clock having a constant frequency is input is used as the sampling means, the first counting means, the second counting means and the third counting means. Can be said.

According to the present invention, the scale of the circuit for generating the control clock can be reduced and a highly accurate clock can be obtained. In addition, power consumption of the active matrix type liquid crystal display device can be saved by reducing the circuit scale.

(Fourth Embodiment) FIGS. 19, 20 and 2
FIG. 1 is a diagram illustrating an example of a signal line drive circuit of an active matrix panel which constitutes an active matrix type liquid crystal display device using the fourth embodiment. The signal line driver circuit is formed on the same substrate as the pixel matrix.

FIG. 19 shows a reset switch control circuit 9
21 and the hold switch control circuit 922 are added to the rear part of the m-th bit of the shift register SR. The difference from the first embodiment is that there is no output switch group and that there is no output switch control circuit for controlling it. In the first embodiment, the output switch group and the output switch control circuit are the analog buffer group B1,
It is provided for the purpose of controlling the electrical connection between B2 ... Bm and the signal lines S1, S2 ... Sm. However, in a small-sized active matrix type liquid crystal display device, there is a large area restriction, and it may not be possible to arrange the output switch group and the output switch control circuit. That is, in order to arrange the circuits for controlling the sample switch group, the reset switch group, and the hold switch group on the same substrate as the pixel matrix in the minimum area, the portion 920 of the signal line driver circuit is reset switch control. Optimally, it consists of a circuit and a hold switch control circuit. The control clock C in FIG.
LK has a variable frequency.

In FIG. 21, the frequency of the control clock is variable in FIG.
1. Control the hold switch control circuit 922. This effect is similar to that of the third embodiment. Since the output switch control circuit and the output switch group are not provided, the total area of the circuit is smaller than that of the third embodiment.

In FIG. 22, a delay circuit 927 is provided between the reset switch control circuit 921 and the hold switch control circuit 922. This effect is similar to that of the second embodiment. Since the output switch control circuit and the output switch group are not provided, the total area of the circuit is smaller than that of the second embodiment.

From the description of the fourth embodiment, in the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate,
The signal line drive circuit includes sampling means for sequentially sampling video signals, holding means for holding the video signals sampled by the sampling means, and a buffer for amplifying or buffering the video signals held by the holding means. It can be said that the present invention is characterized by having the means and the first control means for controlling the holding means. Further, in an active matrix type liquid crystal display device in which a pixel matrix and at least a signal line drive circuit are formed on the same substrate, the signal line drive circuit is sampled by a sampling means for sequentially sampling a video signal and the sampling means. Hold means for holding the video signal, buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting at least one of the hold means and the buffer means, and the hold means It can be said that a feature of the present invention is to use an active matrix type liquid crystal display device having a first control means for controlling the above and a second control means for controlling the resetting means.

According to the present invention, the control signals generated by the first control means and the second control means are transmitted to the holding means and the sampling means with almost no delay, so that an erroneous signal is captured. Is prevented in advance. Further, since the control signal is generated by the first control means and the second control means and does not need to be supplied from outside the same board, the number of mounting terminals can be reduced. Further, since the total area of the signal line driver circuit is reduced, the active matrix liquid crystal display device can be narrowed.

[0090]

In the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate, the signal line drive circuit has sampling means for sequentially sampling the video signal, and the sampling means. By using an active matrix type liquid crystal display device having a holding means for holding the video signal sampled by the above, and a first control means for controlling the holding means, or a pixel matrix and at least a signal line driving circuit. In the active matrix type liquid crystal display device in which and are formed on the same substrate, the signal line drive circuit includes sampling means for sequentially sampling video signals, and holding means for holding the video signals sampled by the sampling means. , The video signal held by the holding means A buffer means for width or buffer,
And a first control means for controlling the holding means, or an active matrix liquid crystal display in which a pixel matrix and at least a signal line driving circuit are formed on the same substrate. In the apparatus, the signal line drive circuit includes a sampling unit that sequentially samples a video signal, a holding unit that holds the video signal sampled by the sampling unit, and an amplifier that amplifies the video signal held by the holding unit. Buffer means for buffering, reset means for resetting at least one of the hold means or the buffer means, first control means for controlling the hold means, and second control means for controlling the reset means,
By using the active matrix type liquid crystal display device having, the control signals generated by the first control means and the second control means are transmitted to the holding means and the sampling means with almost no delay, False signals are prevented from being captured. The control signal is generated by the first control means and the second control means,
Since it is not necessary to supply from outside the same substrate, the number of mounting terminals can be reduced. This includes a reduction in the number of mounting processes,
This has the effect of improving the yield in the mounting process. Further, conventionally, the control signal of the reset means and the control signal of the hold means may temporally overlap each other due to the delay of the control signal, and the reset signal leaks to the video signal transferred to the hold means. However, since there is almost no delay in the control signal in the present invention, leakage of the reset signal can be prevented in advance.

In the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line driving circuit are formed on the same substrate, the signal line driving circuit includes at least sampling means for sequentially sampling the video signal,
A holding means for holding the video signal sampled by the sampling means; a buffer means for amplifying or buffering the video signal held by the holding means; and a first control means for controlling the holding means. Then, the sampling means generates sample / latch generation means for generating a latch signal that defines a timing for sampling the video signal, sample holding means for holding the video signal to be sampled, and the sampling / holding means based on the latch signal. An active matrix type liquid crystal display device comprising a sample switching means for sampling a video signal into the sample holding means, and the first control means being substantially equivalent to the sample latch generating means. By using the first control means, the number of output bits of the sample latch generation means Because that can be configured simply by many,
The circuit layout area can be minimized, and the active matrix liquid crystal display device can be narrowed. Further, there is an advantage that the design load and the factor of design error can be reduced as compared with the case where the control means is designed with a completely different configuration from the sample latch generation means.

Further, in the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate, the signal line drive circuit has at least sampling means for sequentially sampling the video signal,
Holding means for holding the video signal sampled by the sampling means, buffer means for amplifying or buffering the video signal held by the holding means, and intermittently the video signal amplified or buffered by the buffer means By using the active matrix type liquid crystal display device having the signal line output means for supplying the signal line of the pixel matrix to the signal line, a high frequency component other than the video signal is not given to the signal line. There is no need to change the orientation of the liquid crystal enclosed in. Therefore, generation of liquid crystal domains due to abnormal alignment can be suppressed, and light leakage due to the domains can be prevented.
A high-quality active matrix type liquid crystal display device can be realized. Further, it is possible to prevent the capacitance parasitic on the signal line from being unnecessarily charged / discharged by the buffer means, so that the power consumption of the active matrix type liquid crystal display device can be reduced because the signal line output means can be prevented. .

No high frequency component other than the video signal is applied to the signal line.

Further, the pixel matrix and at least the signal line drive circuit are formed on the same substrate, and the signal line drive circuit includes at least sampling means for sequentially sampling the video signal and the video image sampled by the sampling means. The sampling means includes: holding means for holding a signal; buffer means for amplifying or buffering the video signal held by the holding means; and first control means for controlling the holding means. Sample / latch generation means for generating from the clock signal a latch signal that defines the timing for sampling the video signal, sample holding means for holding the video signal to be sampled, and the sampled video signal based on the latch signal. Active matrix consisting of sample switching means for sampling to capacitance Type liquid crystal display device, the frequency of the clock signal is variable, and the timing signal for controlling the holding means is an active matrix liquid crystal display device generated from the clock signal by the first control means. The hold timing can be changed only by changing the frequency of the clock signal.
When the signal line driving circuit of the present invention is used, the external circuit can be shared by the active matrix type liquid crystal display devices having different specifications, so that the manufacturing cost of the external circuit can be reduced. Further, even in the active matrix type liquid crystal display device having the same specifications, it is possible to compensate for the timing shift due to the variation of the characteristics, and it is possible to remedy a defective product which has been conventionally formed.

Further, the pixel matrix and at least the signal line drive circuit are formed on the same substrate, and the signal line drive circuit at least samples the video signals sequentially and the video signals sampled by the sampling means. A method for driving an active matrix liquid crystal display device, comprising: holding means for holding, buffer means for amplifying or buffering the video signal held by the holding means, and reset means for resetting the holding means. When the time required to hold the video signal by the means is th and the time required to reset the holding means by the reset means is tr, at least the relation of th> tr is satisfied. By using the driving method of It is possible to maximize the time during which the buffer means amplifies and outputs the video signal to the signal line by effectively utilizing the normal retrace line period. For this reason,
The video signal is sufficiently written to the signal line, and a high-contrast active matrix type liquid crystal display device can be realized.

Further, in the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate, the signal line drive circuit has at least sampling means for sequentially sampling the video signal,
Holding means for holding the video signal sampled by the sampling means, buffer means for amplifying or buffering the video signal held by the holding means, reset means for resetting the holding means, and resetting of the reset means By using an active matrix type liquid crystal display device having a delay means for controlling the time length from the timing of ending the operation to the timing of starting the hold operation of the hold means, a period during which the reset means performs the reset operation is provided. The period during which the hold means performs the hold operation does not overlap, the transfer of the video signal from the sample means to the hold means can be performed with high accuracy, and the active matrix type liquid crystal display device having an excellent gradation resolution display capability. Can be realized.

In the active matrix type liquid crystal display device in which the pixel matrix and at least the signal line drive circuit are formed on the same substrate, the signal line drive circuit includes at least sampling means for sequentially sampling the video signal,
It has a holding means for holding the video signal sampled by the sampling means, a buffer means for amplifying or buffering the video signal held by the holding means, and a first counting means for controlling the holding means. By using an active matrix type liquid crystal display device in which a control clock having a constant frequency is input to the sampling means and the first counting means, or the pixel matrix and at least the signal line driving circuit are provided on the same substrate. In the formed active matrix type liquid crystal display device, the signal line drive circuit includes at least sampling means for sequentially sampling video signals, and holding means for holding the video signals sampled by the sampling means.
Buffer means for amplifying or buffering the video signal held by the holding means, reset means for resetting at least one of the holding means and the buffer means, and first counting means for controlling the holding means,
Second counting means for controlling the reset means,
By using an active matrix type liquid crystal display device in which a control clock having a constant frequency is input to the sampling means, the first counting means and the second counting means, or by using a pixel matrix and at least a signal line driving circuit. In the active matrix type liquid crystal display device in which is formed on the same substrate, the signal line drive circuit has at least sampling means for sequentially sampling video signals, and holding means for holding the video signals sampled by the sampling means, Buffer means for amplifying or buffering the video signal held by the hold means, reset means for resetting at least one of the hold means and the buffer means, and the hold means from the timing of ending the reset operation of the reset means Timing to start the hold operation of Delay means for controlling the time length until the delay, first counting means for controlling the holding means, second counting means for controlling the reset means, and third counting means for controlling the delay means. By using an active matrix type liquid crystal display device in which a control clock having a constant frequency is input to the sampling means, the first counting means, the second counting means and the third counting means,
The scale of the circuit that generates the control clock can be reduced, and a highly accurate clock can be obtained. In addition, power consumption of the active matrix type liquid crystal display device can be saved by reducing the circuit scale.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an example of a signal line driving circuit of an active matrix type liquid crystal display device using a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a conventional TFT-LCD panel.

FIG. 3 is a diagram illustrating a configuration of a conventional TFT-LCD module.

FIG. 4 illustrates a conventional signal line driver circuit.

FIG. 5 illustrates a circuit configuration of a shift register.

FIG. 6 is a diagram illustrating an example of a specific circuit configuration of a signal line drive circuit of an active matrix type liquid crystal display device using the first embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of a specific circuit configuration of a signal line driving circuit of an active matrix type liquid crystal display device using the first embodiment of the present invention.

8 is a timing chart illustrating an example of a driving method of the signal line driver circuit illustrated in FIG.

FIG. 9 is a diagram illustrating an example of a specific circuit configuration of a signal line drive circuit of an active matrix type liquid crystal display device using the first embodiment of the present invention.

10 is a timing chart illustrating an example of a driving method of the signal line driver circuit illustrated in FIG.

FIG. 11 is a diagram illustrating an example of a signal line drive circuit of an active matrix type liquid crystal display device using a second embodiment of the present invention.

FIG. 12 is a diagram illustrating an example of a specific circuit configuration of a signal line drive circuit of an active matrix type liquid crystal display device using a second embodiment of the present invention.

13 is a timing chart illustrating an example of a driving method of the signal line driver circuit illustrated in FIG.

FIG. 14 is a diagram illustrating an example of a specific circuit configuration of a signal line drive circuit of an active matrix type liquid crystal display device using a second embodiment of the present invention.

15 is a timing chart illustrating an example of a driving method of the signal line driver circuit illustrated in FIG.

FIG. 16 is a diagram illustrating an example of a signal line drive circuit of an active matrix type liquid crystal display device using a third embodiment of the present invention.

FIG. 17 is a diagram illustrating an example of a specific circuit configuration of a signal line drive circuit of an active matrix type liquid crystal display device using a third embodiment of the present invention.

18 is a timing chart illustrating an example of a driving method of the signal line driver circuit illustrated in FIG.

FIG. 19 is a diagram illustrating an example of a signal line drive circuit of an active matrix type liquid crystal display device using a fourth embodiment of the present invention.

FIG. 20 is a diagram illustrating an example of a signal line drive circuit of an active matrix type liquid crystal display device using a fourth embodiment of the present invention.

FIG. 21 is a diagram illustrating an example of a signal line drive circuit of an active matrix type liquid crystal display device using a fourth embodiment of the present invention.

[Explanation of symbols]

CLK ・ ・ ・ Control clock XIN ・ ・ ・ Selection signal VIDEO ・ ・ ・ Video signal SR ・ ・ ・ Shift register LS ・ ・ ・ Level shifter SW1,1, SW2,1 ・ ・ ・ SWm, 1 ・ ・ ・ Sample ・
Switch group SW1,2, SW2,2 ・ ・ ・ SWm, 2 ・ ・ ・ Hold ・
Switch group SW1,3, SW2,3 ・ ・ ・ SWm, 3 ・ ・ ・ Output switch group SW1,4, SW2,4 ・ ・ ・ SWm, 4 ・ ・ ・ First reset switch group SW1,5, SW2, 5 ... SWm, 5 ... Second reset switch group Bit1, Bit2 ... Bitm ... Bit output RS ... Reset signal line B1, B2 ... Bm ... Analog buffer C1 , 1, C2,1 ・ ・ ・ Cm, 1 ・ ・ ・ Sample capacitance C1,2, C2,2 ・ ・ ・ Cm, 2 ・ ・ ・ Hold capacitance 101 ・ ・ ・ Output switch control circuit 102 ・ ・ ・ Reset switch Control circuit 103 ・ ・ ・ Hold switch control circuit 104, 105 ・ ・ ・ Part of output switch control circuit 106, 107 ・ ・ ・ Part of signal line drive circuit 201 ・ ・ ・ TFT-LCD panel 202 ・ ・ ・ n rows × Pixel matrix with m columns 20・ ・ ・ Thin film transistor 204 ・ ・ ・ Liquid crystal 205 ・ ・ ・ Storage capacity 206 ・ ・ ・ Signal line drive circuit 207 ・ ・ ・ Scan line drive circuit S1, S2 ・ ・ ・ Sm ・ ・ ・ Signal line G1, G2 ・ ・ ・ Gn・ ・ ・ Scan line SRX ・ ・ ・ X side shift register LSX ・ ・ ・ X side level shifter SRY ・ ・ ・ Y side shift register LSY ・ ・ ・ Y side level shifter SH ・ ・ ・ Sample and hold circuit COM ・ ・ ・ Counter voltage XCLK・ ・ ・ X side clock XIN ・ ・ ・ X side selection signal VIDEO ・ ・ ・ Video signal RST ・ ・ ・ Reset signal ENBL ・ ・ ・ Output enable signal YIN ・ ・ ・ Y side selection signal YCLK ・ ・ ・ Y side clock 301 ・.... Opposing voltage COM generation circuit 302 ... Video signal VIDEO modulation circuit 303 ... X-side clock X CLK generation circuit 304 ・ ・ ・ X side selection signal XIN generation circuit 305 ・ ・ ・ Output enable signal ENBL generation circuit 307 ・ ・ ・ Y side selection signal YIN generation circuit 308 ・ ・ ・ Y side clock YCLK generation circuit 309 ・ ・ ・ TFT -LCD unit 310 ・ ・ ・ Video original signal 311 ・ ・ ・ Reset signal RST generation circuit ECLK ・ ・ ・ External clock HSYNC ・ ・ ・ Horizontal sync signal VSTNC ・ ・ ・ Vertical sync signal ASW1,1, ASW2,1 ・ ・ ・ ASWm , 1 ・ ・ ・ Analog switch group ASW1,2, ASW2,2 ・ ・ ・ ASWm, 2 ・ ・ ・ Analog switch group RSW1, RSW2 ・ ・ ・ RSWm ・ ・ ・ Reset ・
Switch group CSPL ・ ・ ・ Sample capacity HLLD ・ ・ ・ Hold capacity 501 ・ ・ ・ D-flip-flop 502 ・ ・ ・ Clocked inverter 503 ・ ・ ・ Inverter 504 ・ ・ ・ AND gates CLKa, CLKb, CLKb * ・ ・ ・Clock DIN ... Selection signal 601 ... Terminals 602, 603, 604 ... Wiring 605, 607 ... D-flip-flop 606 ... Resettable-D-flip-flop 608 ... NOR gates P61 to P66・ ・ ・ Points P61 to P66 701,702 ・ ・ ・ Wiring from bit output 703 ・ ・ ・ Wiring from hold switch control circuit 704 ・ ・ ・ Wiring from reset switch control circuit 705 ・ ・ ・ Output switch control circuit Wiring from 706, 707 ... Signal line Wiring 801 ... horizontal scanning period 802 ... horizontal retrace period 803,804,805,806 ... period 901 ... terminal 902 ... first reset switch group and the second
To the reset switch group 903 ... to the hold switch group 904 ... to the output switch group 905, 906 ... N-type thin film transistors 907, 908 ... clocked inverter 909 ... .. NOR gates P91 to P99 ... Points P91 to P99 CLK, CLK * ... Control clocks 121, 122, 123, 124 ... Period 111 ... Terminal 112 ... Delay circuit 211 ... Terminal 212, 213, 214 ... Wiring 215, 217 ... D-flip-flop 216 ... Resettable D-flip-flop 218 ... NOR gate P21-P26 ... Points P21-P26 320 ... Horizontal Scanning period 321 ... Horizontal blanking period 322, 323, 324, 325 ··· Period 401 ・ ・ ・ Terminals 402, 403, 404 ・ ・ ・ Wiring 405, 406 ・ ・ ・ Clocked inverters 407, 408 ・ ・ ・ N-type thin film transistors 409 ・ ・ ・ Inverters P41 to P49 ・ ・ ・ Points P41 to P49 510 ・ ・ ・ Horizontal scanning period 511 ・ ・ ・ Horizontal retrace line period 512, 513, 515, 516 ・ ・ ・ Period 514 ・ ・ ・ Delay period 610, 611, 612 ・ ・ ・ Count circuit 711 ・ ・ ・ Terminal 712 713, 714 ... Wiring 715, 717 ... D-flip-flop 716 ... Resettable D-flip-flop 718 ... NOR gate P71-P77 ... Point P71-P77 810 ... Horizontal scanning period 811 ・ ・ ・ Horizontal retrace period 812, 813, 815, 816 ・ ・ ・ Period 814 ... delay period 920 ... portions 921 ... reset switch control circuit 922 ... hold switch control circuit 925,926 ... count circuit 927 ... delay circuit

Claims (15)

[Claims] 1. In an active matrix type liquid crystal display device in which a pixel matrix and at least a signal line driving circuit are formed on the same substrate, the signal line driving circuit includes sampling means for sequentially sampling video signals, and the sampling means. An active matrix type liquid crystal display device comprising: a holding unit that holds the video signal sampled by the above; and a control unit that controls the holding unit. 2. In an active matrix type liquid crystal display device in which a pixel matrix and at least a signal line driving circuit are formed on the same substrate, the signal line driving circuit includes sampling means for sequentially sampling video signals, and the sampling means. And holding means for holding the video signal sampled by the holding means, buffer means for amplifying or buffering the video signal held by the holding means, and control means for controlling the holding means. Active matrix liquid crystal display device. 3. An active matrix type liquid crystal display device in which a pixel matrix and at least a signal line drive circuit are formed on the same substrate, wherein the signal line drive circuit has a sampling means for sequentially sampling a video signal, and the sampling means. Holding means for holding the video signal sampled by the holding means, buffer means for amplifying or buffering the video signal held by the holding means, and reset means for resetting at least one of the holding means and the buffer means. An active matrix liquid crystal display device comprising: first control means for controlling the holding means and second control means for controlling the reset means. 4. An active matrix liquid crystal display device in which a pixel matrix and at least a signal line drive circuit are formed on the same substrate, wherein the signal line drive circuit includes at least sampling means for sequentially sampling video signals, and the sample. Holding means for holding the video signal sampled by the holding means, buffer means for amplifying or buffering the video signal held by the holding means, and control means for controlling the holding means. Is a sample / latch generating means for generating a latch signal that defines a timing for sampling the video signal, a sample holding means for holding the video signal to be sampled, and the sample signal for the video signal based on the latch signal. And a sample switching means for sampling to the holding means. An active matrix type liquid crystal display device characterized in that the control means is constituted by means substantially equivalent to the sample / latch generation means. 5. In an active matrix type liquid crystal display device in which a pixel matrix and at least a signal line drive circuit are formed on the same substrate, the signal line drive circuit has at least sampling means for sequentially sampling video signals, and the sample. Holding means for holding the video signal sampled by the holding means, buffer means for amplifying or buffering the video signal held by the holding means, and control means for controlling the holding means. Is a sample / latch generating means for generating a latch signal that defines a timing for sampling the video signal, a sample holding means for holding the video signal to be sampled, and the sample signal for the video signal based on the latch signal. And a sample switching means for sampling to the holding means. 4. The active matrix type liquid crystal display device according to claim 1, wherein the control means is constituted by means substantially equivalent to the sample latch generation means. 6. In an active matrix type liquid crystal display device in which a pixel matrix and at least a signal line drive circuit are formed on the same substrate, the signal line drive circuit includes at least a sampling means for sequentially sampling a video signal, and the sample. Holding means for holding the video signal sampled by the means, buffer means for amplifying or buffering the video signal held by the holding means, and intermittently the video signal amplified or buffered by the buffer means An active matrix type liquid crystal display device, comprising: a signal line output means for supplying the signal lines of a pixel matrix. 7. In an active matrix type liquid crystal display device in which a pixel matrix and at least a signal line drive circuit are formed on the same substrate, the signal line drive circuit has at least a sampling means for sequentially sampling a video signal, and the sample. Holding means for holding the video signal sampled by the means, buffer means for amplifying or buffering the video signal held by the holding means, and intermittently the video signal amplified or buffered by the buffer means 6. A liquid crystal display device according to claim 1, further comprising a signal line output unit that supplies the signal line of the pixel matrix. 8. A pixel matrix and at least a signal line drive circuit are formed on the same substrate, and the signal line drive circuit includes at least sampling means for sequentially sampling video signals and the video sampled by the sampling means. The sampling means includes a holding means for holding a signal, a buffer means for amplifying or buffering the video signal held by the holding means, and a control means for controlling the holding means. Sampling / latch generating means for generating a latch signal defining a sampling timing from a clock signal, sample holding means for holding the video signal to be sampled, and sampling the video signal to the sample capacitance based on the latch signal. Active matrix liquid crystal display composed of sample switching means In the device, the frequency of the clock signal is variable, and a timing signal for controlling the holding means is generated from the clock signal by the control means, and an active matrix type liquid crystal display device. 9. A pixel matrix and at least a signal line drive circuit are formed on the same substrate, and the signal line drive circuit includes at least sampling means for sequentially sampling a video signal and the video image sampled by the sampling means. The sampling means includes a holding means for holding a signal, a buffer means for amplifying or buffering the video signal held by the holding means, and a control means for controlling the sampling means and the holding means. , A sample / latch generating means for generating a latch signal that defines a timing for sampling the video signal from a clock signal, a sample holding means for holding the video signal to be sampled, and the video signal based on the latch signal. An active capacitor comprising sample switching means for sampling to the sample volume. 9. In the trix type liquid crystal display device, the frequency of the clock signal is variable, and the timing signal for controlling the hold means is generated from the clock signal by the hold control means. The active matrix liquid crystal display device described. 10. A pixel matrix and at least a signal line drive circuit are formed on the same substrate, and the signal line drive circuit at least sample means for sequentially sampling a video signal, and the video signal sampled by the sampling means. A method of driving an active matrix liquid crystal display device, comprising: holding means for holding, buffer means for amplifying or buffering the video signal held by the holding means, and reset means for resetting the holding means. When the time required to hold the video signal by the means is th and the time required to reset the holding means by the reset means is tr, at least the relation of th> tr is established. Driving method of matrix type liquid crystal display device. 11. An active matrix type liquid crystal display device in which a pixel matrix and at least a signal line drive circuit are formed on the same substrate, wherein the signal line drive circuit includes at least a sampling means for sequentially sampling a video signal, and the sample. Holding means for holding the video signal sampled by the means, buffer means for amplifying or buffering the video signal held by the holding means,
An active device comprising: a reset device for resetting the hold device; and a delay device for controlling a time length from a timing of ending the reset operation of the reset device to a timing of starting the hold operation of the hold device. Matrix type liquid crystal display device. 12. In an active matrix type liquid crystal display device in which a pixel matrix and at least a signal line drive circuit are formed on the same substrate, the signal line drive circuit includes at least sampling means for sequentially sampling a video signal, and the sample. Holding means for holding the video signal sampled by the means, buffer means for amplifying or buffering the video signal held by the holding means,
It has a reset means for resetting the hold means, and a delay means for controlling the time length from the timing of ending the reset operation of the reset means to the timing of starting the hold operation of the hold means. Item 5. The active matrix liquid crystal display device according to item 3. 13. In an active matrix type liquid crystal display device in which a pixel matrix and at least a signal line drive circuit are formed on the same substrate, the signal line drive circuit includes at least sampling means for sequentially sampling a video signal, and the sample. Holding means for holding the video signal sampled by the means, buffer means for amplifying or buffering the video signal held by the holding means,
An active matrix type liquid crystal display device, comprising: first holding means for controlling the holding means, and a control clock having a constant frequency is input to the sampling means and the first counting means. 14. An active matrix liquid crystal display device in which a pixel matrix and at least a signal line drive circuit are formed on the same substrate, wherein the signal line drive circuit includes at least sampling means for sequentially sampling a video signal, and the sample. Holding means for holding the video signal sampled by the means, buffer means for amplifying or buffering the video signal held by the holding means,
A reset means for resetting at least one of the hold means and the buffer means, a first counting means for controlling the hold means, and a second for controlling the reset means.
14. The active matrix type device according to claim 13, further comprising: counting means, and a control clock having a constant frequency is input to the sampling means, the first counting means, and the second counting means. Liquid crystal display device. 15. In an active matrix type liquid crystal display device in which a pixel matrix and at least a signal line drive circuit are formed on the same substrate, the signal line drive circuit has at least a sampling means for sequentially sampling a video signal, and the sample. Holding means for holding the video signal sampled by the means, buffer means for amplifying or buffering the video signal held by the holding means,
Reset means for resetting at least one of the hold means and the buffer means; delay means for controlling the time length from the timing of ending the reset operation of the reset means to the timing of starting the hold operation of the hold means; The first counting means for controlling the holding means, the second counting means for controlling the resetting means, and the third counting means for controlling the delaying means are provided, and the sampling means and the first counting means are provided. 15. The active matrix type liquid crystal display device according to claim 13 or 14, wherein a control clock having a constant frequency is input to the counting means, the second counting means and the third counting means.