JPH04278575A - Semiconductor device - Google Patents

Abstract

PURPOSE:To offer a semiconductor device, whose operating speed is fast, in which a WSi2 electrode layer is never peeled and which is constituted of a capacitor having a capacity and/or a transistor. CONSTITUTION:A semiconductor device is constituted in such a way that an N<+> first polysilicon electrode layer, a silicon oxide layer and an N<+> second polysilicon electrode layer are laminated in order on a substrate and moreover, a WSi2 electrode layer is laminated on this N<+> second polysilicon electrode layer interposing an N<+> third polysilicon electrode layer having an electric resistance larger than that of the N<+> second polysilicon electrode layer between the N<+> second polysilicon electrode layer and the WSi2 electrode layer and a capacitor and/or a transistor are/is constituted.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device including a capacitor and/or a transistor.

0002

2. Description of the Related Art The following three types of conventional semiconductor devices are known. The first is 30Ω on the substrate 11 as shown in FIG.
/D first N+ polysilicon electrode layer 12, silicon oxide layer 13, and second N+ polysilicon electrode layer 1 of 30Ω/D.
4 is stacked in order to form a capacitor. The second one is 30Ω on the substrate 11 as shown in FIG.
/D first N+ polysilicon electrode layer 12, silicon oxide layer 13, and second N+ polysilicon electrode layer 14 of 30Ω/D.
and WSi2 electrode layer 16 are sequentially stacked to form a capacitor. Third, as shown in FIG. 5, a first N+ polysilicon electrode layer 12 of 30 Ω/D, a silicon oxide layer 13, a third N+
This is a semiconductor device in which a polysilicon electrode layer 15 and a WSi2 electrode layer 16 are sequentially stacked to form a capacitor.

0003

SUMMARY OF THE INVENTION Although the first conventional semiconductor device described above can secure a stable capacitance, there is a problem in that the operation speed is slow due to the polysilicon gate. Second
This semiconductor device has a problem in that the WSi2 electrode layer 16 peels off. In the third semiconductor device, the operating speed is faster and the WSi2 electrode layer 16 does not peel off, but the majority carriers in the third N+ polysilicon electrode layer 15 move due to the applied bias and a depletion layer is formed. Due to dependence, there is a problem that stable capacity cannot be secured.

The present invention was made in order to solve the above problems, and provides a capacitor and/or transistor with a high operating speed (response speed to input signals), no peeling of the WSi2 electrode layer, and a stable capacitance. The present invention aims to provide a semiconductor device composed of the following.

[0005]

[Means for Solving the Problems] According to the present invention, a first N+ polysilicon electrode layer, a silicon oxide layer, and a second N+ polysilicon electrode layer are laminated in this order on a substrate, and a second N+ polysilicon electrode layer is further stacked on top of this. A third N+ polysilicon electrode layer having higher electrical resistance than the electrode layer is interposed to form WSi2
A semiconductor device is provided in which electrode layers are stacked to form a capacitor and/or a transistor.

[0006] The substrate is usually a silicon substrate on which elements are formed and an insulating film is formed on the surface.

The first N+ polysilicon electrode layer is used to constitute an electrode of a capacitor or a source/drain of a transistor, and preferably has a resistance of usually 10 to 50 Ω/D.

The silicon oxide layer is used to constitute a dielectric of a capacitor or a gate insulating film of a transistor, and usually has a thickness of 100 to 300 Å.

The second N+ polysilicon electrode layer is used to constitute a capacitor electrode or a transistor gate electrode, and preferably has a resistance of usually 10 to 50 Ω/D.

The third N+ polysilicon electrode layer is for adhering the WSi2 electrode layer laminated thereon to prevent peeling, and is made of N+ polysilicon having a higher electrical resistance than the second N+ polysilicon electrode layer. It is preferably composed of silicon and typically has an electrical resistance of 100 to 1000 Ω/D.

The WSi2 electrode layer is used to increase the operating speed (response speed to an input signal) of the capacitor or transistor, and preferably has a resistance value smaller than that of the second N+ polysilicon electrode layer, and usually has a resistance value of 1 to 1. 10
It has a resistance of Ω/D.

In the present invention, the silicon oxide layer is used as a dielectric layer, the first N+ polysilicon electrode layer is used as the lower electrode, and the three layers of the second N+ polysilicon electrode layer, the third N+ polysilicon electrode layer and the WSi2 electrode layer are used as the upper electrode. A capacitor can be configured. In addition, the silicon oxide layer is used as a gate insulating film, the first N+ polysilicon electrode layer is used as a source,
A transistor can be constructed by using three layers as a drain, a second N+ polysilicon electrode layer, a third polysilicon electrode layer, and a WSi2 electrode layer as a gate electrode.

In the present invention, a semiconductor device can be constructed by appropriately arranging the capacitor and/or the transistor on one substrate.

[0014]

[Function] The 3rd N+ polysilicon layer with high electrical resistance interposed between the 2nd N+ polysilicon layer and the WSi2 layer does not form a depletion layer due to the applied bias.
Make the i2 layer adhere well.

[0015]

[Embodiment] An embodiment of the present invention will be explained with reference to the drawings.

As shown in FIG. 1, a first N+ polysilicon electrode layer 2 of 30 Ω/D is formed and patterned on a silicon substrate 1 on which elements are formed. Next, a 100 Å thick silicon oxide layer 3 is formed on the first N+ polysilicon electrode layer 2 by thermal oxidation. Next, polysilicon is laminated thereon to form a second N+ polysilicon electrode layer 4 of 30 Ω/D. Next, layer polysilicon to form a 300Ω/D 3N layer.
+Polysilicon electrode layer 5 is formed. Next, WS on top of this
An i2 film 6 is formed.

Next, as shown in FIG. 2, it is patterned to use the silicon oxide layer 3 as a dielectric layer, the first N+ polysilicon electrode layer 2 as the lower electrode, the second N+ polysilicon electrode layer 4, the third N+ polysilicon electrode layer 4, and the like. WSi2 electrode layer 6-3
A capacitor is constructed by using the layer as an upper electrode, and the silicon oxide layer 3 is used as a gate insulating film, and the first N+ polysilicon electrode layer 2 is used as a source and drain, and the second N+ polysilicon electrode layer 4, the third N+ polysilicon electrode layer 5, and WSi2
A semiconductor device is manufactured by forming a transistor using the three electrode layers 6 as gate electrodes.

[0018]

According to the present invention, it is possible to provide a semiconductor device constituted by a capacitor and/or transistor that has a high operating speed (response speed to input signals) and a stable capacitance without peeling of the WSi2 electrode layer. Can be done.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the manufacturing process of a semiconductor device manufactured in an example of the present invention.

FIG. 2 is an explanatory diagram of a semiconductor device manufactured in an example of the present invention.

FIG. 3 is an explanatory diagram of a conventional semiconductor device.

FIG. 4 is an explanatory diagram of a conventional semiconductor device.

FIG. 5 is an explanatory diagram of a conventional semiconductor device.

[Explanation of symbols]

1 Silicon substrate on which elements are formed 2 First N+ polysilicon electrode layer 3 Silicon oxide layer 4 Second N+ polysilicon electrode layer 5 Third
N+ polysilicon electrode layer 6 WSi2 electrode layer

Claims (1)

[Claims] 1. A first N+ polysilicon electrode layer on a substrate;
A silicon oxide layer and a second N+ polysilicon electrode layer are laminated in this order, and a WSi2 electrode layer is further laminated thereon with a third N+ polysilicon electrode layer having a higher electrical resistance than the second N+ polysilicon electrode layer. as well as/
Or a semiconductor device composed of a transistor.