JPH0427588B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an apparatus for processing vector operations, and relates to a function of reducing throughput to main memory.

[Background of the invention]

In scientific and technical calculations, DO as shown in Figure 1
There is a demand for faster FORTRAN programs that include loops. In response to this demand, as one approach, vector processing devices have been developed that use pipeline control to speed up vector processing. Among these, CARY-1 (US) and S-
A vector processing device like the 810 (Hitachi) uses a large number of high-speed registers called vector registers.
By retaining it within the CPU, it is possible to avoid storing intermediate results in main memory, thereby reducing the load on main memory. In the program shown in Figure 1, arrays T and F are read from main memory and array
Writing to TN is the main load on main memory. In current vector processing devices, the performance of such programs is often hampered by the main memory network. However, in the program shown in Figure 1, vector data T(I, J)I=1,
…,NT(I+1,J)I=1,…,NT(I-
1, J) It is composed of vector data that is shifted by only one element, such as I = 1, ..., N, but in current vector processing, each of the three vector data is read from the main memory and written to the vector register. This puts an unnecessary load on main memory. Such programs are frequently used in numerical solutions of partial differential equations.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a vector processor having a vector register configuration that can significantly reduce the load on main memory.

[Summary of the invention]

In order to achieve the above object, in the present invention, guard elements (R7 _i1 , R7 _i2 ) capable of holding several elements are added to a normal vector register as shown in FIG.
will be established. When vector data is loaded from the main memory to the vector register, by providing an instruction to load adjacent data to the guard element and a shift instruction between vector elements, we aim to make effective use of the data once netched from the main memory. , reducing the load on main memory.

[Embodiments of the invention]

An embodiment of the present invention will be described below. A second example of a vector processor configuration to which the present invention is applied is shown below.
As shown in the figure. FIG. 2 is a simplified version of the vector processor shown in Japanese Patent Application No. 1983-42314.
That is, this vector processor includes a scalar processing unit SP, a vector processing unit VP, a main memory (MS) C1 provided in common to these units,
It has a main storage control circuit (SCU) C2. The main storage device C1 contains a scalar instruction sequence to be executed by the scalar processing unit SP and a vector processing unit.
A vector instruction sequence for execution by the VP is stored separately, and vectors and scalar data are also stored, and these are re-accessed by the main memory control circuit C2.

The storage control circuit C2 includes a scalar processing unit SP
In response to a request to read data or a scalar instruction from the unit SP, the data or scalar instruction specified by the address given by the unit SP is read from the main memory C1 and sent to the scalar processing unit SP. Furthermore, in response to a data write request from the scalar processing unit SP, the storage control circuit C2
The data given from the unit SP is stored in the location in the main memory C1 specified by the address given from the unit SP. Similarly,
The storage control circuit C2 is a vector processing unit VP.
In response to a request to read data or vector instructions from the main memory C1, the vector processing unit
Send to VP. The storage control circuit C2 also accesses the main storage device C1 in response to a data write request from the vector processing unit VP.

In this way, the storage control circuit C2 used in the present invention
is configured to respond separately to access requests from the scalar processing unit SP and the vector processing unit VP.

The scalar processing unit SP has a scalar instruction register (SIR) R1, a general purpose register (GR) R2, a scalar arithmetic unit C3, and a control section SC that controls these, and uses these to execute a scalar instruction string in the main memory C1. do. This scalar instruction string includes general scalar instructions, such as the manual "System/370 Principles of Operation" published by IBM.
(GC-22-7000). The scalar processing unit SP uses these instructions to access general register (GR) R2 or main memory C.
A scalar operation is performed on the scalar data within 1, and the result is stored in GR, R2 or main memory C1.
Store in.

In addition to these scalar instructions, the scalar processing unit SP of the vector processor used in the present invention
The information necessary for the vector processing unit VP to operate is read from the general purpose register (GR) R2, and a plurality of scalar instructions to be given to this unit VP and a scalar instruction to instruct the activation of the vector processing unit VP are executed. As a result, the number of elements of vector data to be subjected to vector operation (vector length), the address of the number of first elements of vector data, and the
Address increment values between vector data elements are set in the vector length register (VLR) R4, vector address register (VAR) R5, and vector address increment register (VAIR) R6, respectively, and the vector to be executed is The address of the first instruction in the instruction string is the vector instruction address register (VIAR).
Set to R3.

Based on these registers, a vector instruction sequence starting from the vector instruction specified by VIAR and R3 is read out from the main storage device C1 via the storage control device C2 under the control of the control unit VC, and is stored in the vector register (VR) R7. Using vector operator C4
Perform vector operations with .

The present invention relates to a method of providing a guard element in a vector register and controlling an instruction to load data longer than the vector length and a shift instruction between vector elements in the above vector operation. The vector calculation program shown in FIG. 6 will be explained below with reference to FIGS. 3 to 5.

A vector object sequence as shown in FIG. 6b is developed for the FORTRAN program shown in FIG. 6a. Vector length register (VLR) R4, required for the execution of these vector objects;
Vector address register (VAR) R5, vector address increment register (VAIR)
It is assumed that R6 and the vector instruction address register (VIAR) R3 are set by the scalar processing unit SP as described above. Here, the sixth
The vector instructions in Figures bV1 to V6 will be explained.
These instructions have instruction code field R80
and three fields R81 and R8 specifying the first, second, and third register operands, respectively.
2, R83. (Figure 3).

() LOADE (V1) Normal LOAD instruction uses the second operand R8
(VAR)+(VAIR)*l l= φ,…,
N vector data indicated by address N-1 are stored in vector register R7 _i specified by field R1. (Figure 4).

Furthermore, in the LOADE instruction, R7 _i1 , R
7. Load the adjacent element of the vector data into the guard element of each i-th register VR _i , indicated by _i2 . In the embodiment of FIG. 4, the guard element register is R7 _i
1 , R7 _i2 , the data to be loaded is address (VAR) - (VAIR) and (VAR) +
These are two pieces of data indicated by (VAIR)*N.

() SHIFTL instruction (V2) In this instruction, the data in the vector register indicated by the second operand R82 is shifted by the number indicated by the third operand, and stored in the vector register indicated by the first operand R81. In the embodiment, guard element register R7
Since there are two, _i1 and R7 _i2 , the number of shifts is limited to one. In other words, the data from the first element to the Nth element on the vector register indicated by the second operand R82 is the data from the φth element to the N-1th element on the vector register indicated by the first operand R81.
element (ie, R7 _i on the vector register excluding the guard element) (FIG. 4).

() SHIFTL instruction (V4) Same as the SHIFTL instruction except that the shift direction is reversed. That is, the second operand R8
Data from the −1st element to the N−2th element on the vector register indicated by 2 is moved from the φth element to the N−1th element on the vector register indicated by the first operand R81.

() ADD instruction (V3, V5) The second operand R is a known vector addition instruction.
The data on the vector register indicated by 82 is added for each data element on the vector register indicated by the third operand R83, and the first
Store in the vector register indicated by operand R81. At this time, no operation is performed between the data on the guard elements of the vector register.

() STORE instruction (V5) This is a known vector store instruction that transfers the data in the vector register excluding guard elements R7 _i1 and R7 _i2 indicated by the first operand R81 to the register VAR R5 indicated by the second operand R82 and the third operand. Register indicated by R83
By VAIR R6 (VAR) + (VAIR)*l l=φ,…,N
-1 is stored in the main memory indicated by the address.

Hereinafter, the operating state of the apparatus shown in FIGS. 3, 4 and 5 will be explained with reference to FIG. 6b.

When the vector instruction control circuit C5 of the vector processing unit VP is activated by the scalar processing unit SP via line 1, it receives the vector instruction address previously set in the vector instruction address register (VIAR) R3 via line 2. is through line 3
SCU, sent to C2, based on this address,
The first instruction of the vector instruction string in main memory C1 is read out and set in vector instruction register R8 via SCU, C2 and line 4. In the example of FIG. 6, the first vector instruction designated V1 is set. A vector instruction is set, the instruction code field R80 of this instruction is decoded by the decoder L1, flip-flops (hereinafter abbreviated as FF) F1, F2, and F3 corresponding to this instruction are set, and their outputs are sent to the vector instruction control circuit C5,
The signal is sent to the vector address circuit C7 and the vector register control circuit C8, and used to control the execution of the instruction. At the same time, the contents of VITR, R3 are incremented by one by the constant addition circuit L2 to point to the next vector instruction, and are set to VIAR, R3 again. These series of operations are controlled by the vector instruction control circuit C5, and the instructions are read out one after another and set in the vector instruction registers VIR and R8.
It will be executed. FF and F1 are instructions that write to the vector register starting from -1 element, that is,
Set at the time of the LOADE command. FF, F2,
F3 is set to different values depending on the position of the element number of the vector register to be read. That is, in the case of a SHIFTR instruction, which is an instruction to read from the -1st element, both FFF, F2, and F3 are set. Normal instruction to read from the φth element, ADD instruction,
When STORE, both FF, F2, and F3 are reset. an instruction to read from the first element;
When using the SHIFTL command, FF and F2 are reset,
FF and F3 are set. The operation of each vector instruction V1 to V6 will be explained below.

(Step V1) When the LOADE instruction indicated by V1 is set, FF and F1 are set as described above, and FF and F1 are set.
2, F3 is reset. In addition, the instruction code R80 is sent to the vector instruction control circuit C5 via line 21.
is input and the LOADE command is decoded. line 11
The register number "φ" of the vector address register (VAR) R5 indicating the start address of vector data is read out, and the register number "φ" of the vector address increment register (VAIR) R6 indicating the address between vector elements is read out on the line 12. The number "φ" is read out and these data are input to the vector address circuit C7. In the vector address circuit C7 (Fig. 5), selectors L23, L
24, the contents of the φ vector address register VAR, R5 specified by lines 11 and 12, and φ
number vector address increment register
The contents of VAIR and R6 are read out onto lines 25 and 14, respectively. Note that the vector address register
VAR, R5 and vector address increment register VAIR, R6 are processed by the scalar processing unit SP as shown in Japanese Patent Application No. 56-42314.
From GR, R2 via line 2, selector L27, L
28 and has already been set. Adder C10 is used to shift the address to be loaded by one element in order to load the vector data start address in excess of the guard element.
That is, when FF and F1 are set and the signal "1" is on the output line 5 as in the LOADE command,
An inter-element address between vectors is input to the adder C10 by the selector L21. At the time of other commands, φ is inputted by the selector L21 in response to the signal "φ" on the output line 5. This operation will
In V1, by subtraction by adder C10, (VARφ)
−(VAIRφ) The start address of the vector data including the guard element is output on line 13. Also, at this time, the number of elements of vector data to be read is
The number of guard elements R7 _i1 and R7 _i2 increases by 2, but
This is controlled using adder C11. The vector length N specified by the program has already been set in one input VLR, R4 of this adder C11 by the scalar processing unit. The other input is +2 corresponding to the signal "1" on the output line 5 of FF, F1, and +φ corresponding to the signal "φ". Therefore, in the case of this LOADE instruction, N+2 is set in the work vector length register WVLR, R10,
It is input to the vector command control circuit C5 via the output line 15. The start address of the vector data to be loaded and the address between vector elements are line 1.
3 and 14 to the vector reference control circuit C6 (FIG. 3). The vector reference control circuit C6 is
Based on these read data, vector T
The storage address for reading out the elements of (I, J) by the working vector length N+2 is transmitted via line 31.
Input to SCU and C2 sequentially. As a result, line 20
Above, N+2 elements of vector data T(I, J) are read out in sequence. On the other hand, the data read out on line 20 is transmitted to LOADE command decode signal 22.
is selected by the selector L5, and is sequentially stored in the designated vector register under the control of the vector register control circuit C8 according to the write register number on the line 10 and the distributor L3. In the vector register control circuit C8 (Fig. 4), FF,
The output line 5 of F1 is input to the distributor L12, and the line O _p selected by the line 10 from which the write vector register number "φ" is read.
is output to. FIG. 4 shows a diagram of the device related to the i-th register. The device consisting of adder C30 and selectors L7 and L9 is a vector register.
Shows the counter when writing data to VR _i .
In the case of the LOADE command, -2 is selected by the selector L7 in accordance with the signal "1" on the output line _Op , and is input to the selector L9. At the beginning of vector operation, selector L9 selects the input of selector L7, and adder C3 selects the input of selector L7.
It is input to 0. Other input of adder C30 +1
is for updating the write element position in the vector register, and as a result of the addition, the element position -1 of the vector register to be written first is output on line 50. Day distributor L5
The first element of the vector data on the twisted line 51 _i is stored in the -1st element R7 _i1 of the vector register VR _i according to the value of the counter on the line 50 -1. Selector L9 then selects the value on line 50 as input. Then, the updated element position of the vector register to be written is output on the line 50, and the data on the line _51i is sequentially stored from the -1st element to the Nth element of the vector register according to the address.

In addition, when the instruction is not LOADE, selector L7 selects -1, so when data is written to the vector register for the first time, the data on line 50 indicates φ, and data is stored sequentially starting from the φ-th element of the vector register. be done.

(Step V2) When the SHIFTL command indicated by V2 is set, FF, F1, and F2 are reset as described above.
FF and F3 are reset. An instruction code R80 is input to the vector instruction control circuit C5 via line 21, and the SHIFTL instruction is decoded. The vector register number '1' to be shifted is read out on the line 11, and the selector L4 reads out the first vector register onto the upper data lines 17 and 19 in sequence, and the selector L5 reads out the vector register number '1' on the line 17 and 19. The data on line 19 is selected, and according to the write register number "2" read out on line 10, the distributor L3 sequentially stores it in the vector register No. 2. Vector register control circuit C8 at this time
(Fig. 4) will be explained. Distributor L13 is related to the read side vector register, and when the instruction is not STORE, the second operand R82 and third operand R83 of the vector instruction are used.
The register number designated by is input to the distributor L13 through lines 11 and 12, and the outputs from output lines 6 and 7 indicating the read position of the vector register are read out to I _OP2 and I _OP3 . When using the STORE command,
The register address designated by the first operand R81 of the vector instruction is input to the distributor L13 via line 10, and the outputs on output lines 6 and 7 indicating the read position of the vector register are read out to _IOP1 . Selector L8, to which the output of distributor L13 is input, has signals on lines 6 and 7 that are "1".
-2 when "1", -1 when "φ", "φ"
When it is "1", φ is selected. At the time of the V2 SHIFTL instruction, since the lines 6 and 7 are "φ" and "1", φ is input to the selector L10. Adder C3
1. A device composed of selector L10 indicates a counter when reading data to vector register VR _i . At the beginning of vector calculation, the selector 10 selects the input of the selector L8, which is input to the adder C31. The other input +1 of the adder C31 is for updating the read element position in the vector register, and the element position +1 of the vector register to be read first is output on the addition result line 55. Selector L6 selects the vector register.
The first element of VR ₁ is selected and read out on line 52i. Selector L10 then selects data on line 55. Then, the element position to be read in the vector register is updated and output on the line 55, and according to the address, the first element to the Nth element are sequentially read out on the line 52i. Further, this vector data passes through lines 17 and 19 and is sequentially stored in the second register according to the write register number "2" read out on line 10. At this time, the selector L7, which constitutes the counter indicating the write element position of the vector register, is set to -1 as described above, so the second vector register
The data is sequentially stored from the φth element to the N-1th element of VR ₂ , and a left shift between the elements on the vector register has been realized. Furthermore, since the selector L22 selects φ in a command other than the LOADE instruction as described above, the vector element length is N, which is the same as the vector element length specified in the source program, and is used for control.

(Step V3) In the ADD instruction shown in V3, as mentioned above, FF,
F1, F2 and F3 are reset (FIG. 3).
The instruction code R80 is inputted to the vector instruction control circuit C5 via line 21, and the ADD instruction is decoded.
Vector register numbers "1" and "2" to be added are read out on lines 11 and 12, respectively, and selector L4 selects vector registers VR ₁ and VR _2.
The data are sequentially read out onto lines 17 and 18, and are added by vector arithmetic unit C4. The result is line 19
The selector L5 selects the data on line 19, and the write register number "3" read on line 10 causes the distributor L3 to sequentially store the data in the 3rd vector register. . The vector register control circuit C8 at this time will be explained (FIG. 4). The distributor L13 reads the outputs on the signal lines 6 and 7 to I ₁ and I ₂ according to the read register numbers "1" and "2" on the lines 11 and 12, respectively. At this time, "φ" and "φ" are read out from the signal lines 6 and 7, respectively, according to FF, F2, and F3. At this time, selector L8 selects -1. Therefore, the element position of the power vector register to be read first is φ. Regarding the vector length, since the selector L22 selects φ, the vector length is the same as the length specified in the source program.
Therefore, the φth element to the N-1th element of the vector register VR ₁ and the φth element to the N-1th element of the vector register VR ₂ are sequentially read out.
Control on the writing side is similar to the SHIFTL instruction.

(Step V4) The SHIFTR instruction indicated by V4 differs from the SHIFTL instruction only in that FF, F1 are reset, and FF, F2, F3 are reset.

That is, the selector L8 that controls the first element position of the vector register to be read in the vector register control circuit C8 that uses this output is FF,
The difference is that -2 is selected according to the outputs of F2 and F3. Therefore, the elements from the −1st element to the N−2th element of the read vector register VR ₁ are read out sequentially, and the φth element of the write side vector register VR ₄ is read out in sequence.
The data will be written from the element to the N-1th element.

(Step V5) The only difference from step V3 is the register number.

(Step V6) When the STORE command indicated by V6 is set, FF, F1, F2, and F3 are reset as described above. Further, an instruction code R80 is input to the vector instruction control circuit C5 via line 21, and the STORE instruction is decoded. On line 11, the register number "1" of vector address register (VAR) R5 indicating the start address of vector data is read out, and on line 12, the register number "1" of vector address register (VAR) R5 indicating the address between vector elements is read out.
The register number "1" of R6 is read out and input to the respective vector address circuits C7. In the vector address circuit C7 (FIG. 5), the selector L2
3, L24 reads the contents of the first vector address register R5 and the first vector address increment register R6 designated by lines 11 and 12 onto lines 25 and 14, respectively. Also, the selector L21 selects φ at this time, and the line 2 is on the line 13.
The No. 1 vector address register, which is the same as No. 5, is read out. Then, the start address of the vector data to be stored and the inter-vector element address are sent to the vector reference control circuit C6 via lines 13 and 14. Further, at this time, the selector L5 selects φ as the vector element length, and the vector element length becomes N, which is the same as specified in the source program (FIG. 6a). And the first
The register number “5” to be read from the operand R81 is sent to the distributor L1 by the line 10.
3, and the outputs of output lines 6 and 7 indicating the read position of the vector register are read out to _I5 . The outputs of output lines 6 and 7 are set to selector L according to “φ” and “φ”.
8 selects -1. Therefore, the φth element to the N-1th element of the fifth vector register are read out to the line 52a and sent to the SCU and C2 via the line 32. The vector data sent to SCU and C2 is
Vector reference circuit C6 connects SCU via line 31 to
The data is stored in the main storage device C1 according to the address sent to C2.

In the above embodiment, a case has been described in which each vector register has two guard elements, but it is also possible to further increase the number of shifts that can be specified by the SHIFTL and SHIFTR instructions.

〔Effect of the invention〕

According to the present invention, there is no need to read out each piece of vector data from the main memory separately for a large amount of vector data that is shifted by only one element, which frequently appears in programs for numerical solution of partial differential equations, which occupy a large proportion in the field of scientific and technical computing. Since the target vector data can be obtained by reading one vector data onto the vector register and shifting the vector data between elements, the load on the main memory can be greatly reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a FORNTRAN program including a DO loop, FIG. 2 is a diagram showing the overall configuration of a vector processing device used in the present invention, FIG. 3 is a diagram showing the configuration of a vector processing unit in the present invention, and FIG. The figure shows the configuration of the vector register control circuit in the present invention, Figure 5 shows the configuration of the vector address circuit in the present invention, and Figure 6 shows the configuration of the vector address circuit in the present invention.
1 is a diagram showing an example of a FORTRAN program and a vector instruction sequence for the program; FIG. VR _i ...i number vector register, R7 _i1 ...i
Guard element register 1 of number vector register, R
7 _i2 ... Guard element register 2 of the i-th vector register, R7 _i ... Main part of the i-th vector register consisting of N elements.

Claims (1)

[Claims] 1 A vector register into which vector data is loaded from main memory, a guard element register that holds vector elements adjacent to the vector data when the vector data is loaded into the vector register, and the vector register and the guard. means for concatenating and shifting the element register;
A vector processing device that performs vector processing using the output of the shift means.