JPH04273444A - Formation of bump electrode for semiconductor photodetector - Google Patents
Formation of bump electrode for semiconductor photodetectorInfo
- Publication number
- JPH04273444A JPH04273444A JP3058416A JP5841691A JPH04273444A JP H04273444 A JPH04273444 A JP H04273444A JP 3058416 A JP3058416 A JP 3058416A JP 5841691 A JP5841691 A JP 5841691A JP H04273444 A JPH04273444 A JP H04273444A
- Authority
- JP
- Japan
- Prior art keywords
- film
- melting point
- forming
- bump electrode
- thick
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 230000015572 biosynthetic process Effects 0.000 title 1
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 238000002844 melting Methods 0.000 claims abstract description 19
- 230000008018 melting Effects 0.000 claims abstract description 18
- 125000006850 spacer group Chemical group 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 11
- 238000007747 plating Methods 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 39
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 150000002739 metals Chemical class 0.000 description 7
- 150000001875 compounds Chemical class 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- -1 Ti and Pt Chemical class 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Light Receiving Elements (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体受光素子バンプ電
極形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming bump electrodes of semiconductor light receiving elements.
【０００２】0002
【従来の技術】化合物半導体は光通信用素子などに広く
用いられてきている。その一例として光通信のための受
光素子として開発が進められているＩｎＧａＡｓｐｉｎ
−フォトダイオードがあげられる。この素子の応答特性
の高速化のためには接合径を小さくして接合容量を低減
する必要がある。しかし、接合容量を低減すると、入射
光の光結合トレランスの低下という問題が生ずる。この
トレードオフを回避するためには、基板裏面にマイクロ
レンズを形成した裏面入射型にして、有効受光径を接合
径よりも大きくすることが有効である。更にこのような
裏面入射型素子の場合、素子にバンプ電極を形成し、サ
ブマウントあるいは増幅器ＩＣ上にフリップチップ実装
することで、浮遊容量、寄生インピーダンスを低減でき
るメリットもある。このバンプ電極は、電気的アイソレ
ーションを保つために素子をサブマウント（あるいはＩ
ＣＡ基板）から浮かせるスペーサの役割も持つため、数
μｍ オーダーの高さが必要となる。ＡｕＳｎなどの低
融点金属でこのバンプ電極を形成する技術が検討されて
きている。2. Description of the Related Art Compound semiconductors have been widely used in optical communication devices and the like. One example is InGaAspin, which is being developed as a light receiving element for optical communication.
-Photodiodes are examples. In order to increase the response characteristics of this element, it is necessary to reduce the junction capacitance by reducing the junction diameter. However, reducing the junction capacitance causes a problem of reduced optical coupling tolerance for incident light. In order to avoid this trade-off, it is effective to use a back-illuminated type with microlenses formed on the back surface of the substrate and to make the effective light-receiving diameter larger than the junction diameter. Furthermore, in the case of such a back-illuminated element, there is an advantage that stray capacitance and parasitic impedance can be reduced by forming bump electrodes on the element and flip-chip mounting it on a submount or amplifier IC. This bump electrode is used to submount the device (or to maintain electrical isolation).
Since it also serves as a spacer to float it from the CA substrate, it requires a height on the order of several μm. Techniques for forming bump electrodes using low melting point metals such as AuSn have been studied.
【０００３】0003
【発明が解決しようとする課題】バンプ電極には数μｍ
オーダーの高さが必要であるが、ウェットプロセスで
電極を形成する場合再現性が悪く、また厚さが数μｍ
もあると、リフトオフも非常に困難になるという問題点
があった。このため厚膜パターンの形成が容易なＡｕな
どの選択メッキ膜で高さを稼ぎ、その上にＡｕＳｎ等の
低融点金属薄膜を形成する方法もあるが、この場合素子
実装時の加熱圧着時に、ＡｕＳｎ中のＳｎがＡｕ厚膜中
に拡散してしまい、ＡｕＳｎの融点が上昇してしまう。
このように、従来の方法には再現性および融点に関し解
決すべき課題があった。[Problem to be solved by the invention] The bump electrode has a thickness of several μm.
A height of the order of magnitude is required, but when forming electrodes using a wet process, reproducibility is poor and the thickness is several μm.
There was a problem that lift-off would also be extremely difficult if there was a problem. For this reason, there is a method of increasing the height by using a selective plating film such as Au, which is easy to form a thick film pattern, and then forming a thin film of a low melting point metal such as AuSn on top of it. Sn in AuSn diffuses into the thick Au film, raising the melting point of AuSn. As described above, the conventional methods had problems to be solved regarding reproducibility and melting point.
【０００４】本発明の目的は、上記従来の欠点を取り除
き、従来のものより融点が高くないバンプ電極を再現性
よく形成する方法の提供にある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned conventional drawbacks and to provide a method for forming bump electrodes with good reproducibility whose melting point is not higher than that of the conventional ones.
【０００５】[0005]
【課題を解決するための手段】前述の課題を解決するた
めに本発明が提供する半導体受光素子のバンプ電極形成
方法は、スペーサとしての金属厚膜を形成する工程と、
この厚膜上にＴｉ，Ｐｔなどの高融点金属を含む多層金
属膜を形成する工程と、この金属多層膜上にＡｕＳｎ，
Ｓｎなどの低融点金属膜を形成する工程とを有すること
を特徴とする。[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a method for forming bump electrodes of a semiconductor light receiving element, which includes the steps of forming a thick metal film as a spacer;
A step of forming a multilayer metal film containing high melting point metals such as Ti and Pt on this thick film, and a step of forming a multilayer metal film containing high melting point metals such as Ti and Pt, and a step of forming a multilayer metal film containing high melting point metals such as Ti and Pt, and
The method is characterized by comprising a step of forming a film of a low melting point metal such as Sn.
【０００６】[0006]
【実施例】以下本発明の一実施例について図面を参照し
て詳細に説明する。まず、図１（ａ）に示すように化合
物半導体１の表面に絶縁膜２を形成し、その後フォトレ
ジスト３を塗布し、露光、現像により特定領域のフォト
レジストを除去する。次に図１（ｂ）のようにＴｉ膜４
／Ａｕ膜５を０．１μｍ ／０．２μｍ 蒸着する。続
いて図１（ｃ）に示すようにフォトレジスト６を塗布し
、露光、現像により、フォトレジスト３を除去した領域
内の特定領域のフォトレジスト６を除去する。次に図１
（ｄ）に示すように、この特定領域に選択メッキにより
Ａｕ膜７を５μｍ形成し、続いてＴｉ膜８／Ｐｔ膜９を
０．２μｍ ／０．２μｍ 蒸着する。しかる後、図１
（ｅ）に示すようにフォトレジストを剥離してリフトオ
フ技術により絶縁膜２上の特定領域のみに選択的にＴｉ
膜４／Ａｕ膜５、Ａｕ膜７、Ｔｉ膜８／Ｐｔ膜９を残す
。次に、図１（ｆ）に示すようにフォトレジスト１０を
塗布し、露光、現像によりＴｉ膜８／Ｐｔ膜９上の特定
領域のフォトレジストを除去した後、ＡｕＳｎ膜１１を
１μｍ 蒸着する。最後に、フォトレジストを剥離した
リフトオフ技術によりＴｉ膜８／Ｐｔ膜９上の特定領域
にＡｕＳｎ１１膜を選択的に形成する（図１（ｇ））。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. First, as shown in FIG. 1(a), an insulating film 2 is formed on the surface of a compound semiconductor 1, and then a photoresist 3 is applied, and the photoresist in a specific area is removed by exposure and development. Next, as shown in FIG. 1(b), the Ti film 4
/Au film 5 of 0.1 μm /0.2 μm is deposited. Subsequently, as shown in FIG. 1C, a photoresist 6 is applied, and by exposure and development, the photoresist 6 in a specific area within the area from which the photoresist 3 has been removed is removed. Next, Figure 1
As shown in (d), an Au film 7 of 5 μm thickness is formed in this specific region by selective plating, and then a Ti film 8/Pt film 9 of 0.2 μm/0.2 μm is vapor-deposited. After that, Figure 1
As shown in (e), the photoresist is peeled off and Ti is selectively applied to only specific areas on the insulating film 2 using a lift-off technique.
Film 4/Au film 5, Au film 7, and Ti film 8/Pt film 9 are left. Next, as shown in FIG. 1F, a photoresist 10 is applied, and after removing the photoresist in a specific area on the Ti film 8/Pt film 9 by exposure and development, a 1 μm thick AuSn film 11 is deposited. Finally, an AuSn11 film is selectively formed in a specific region on the Ti film 8/Pt film 9 using a lift-off technique in which the photoresist is removed (FIG. 1(g)).
【０００７】次に図１（ｄ）の工程について、詳しく説
明する。バンプ電極は、電極であると同時にスペーサの
役割も持つので数μｍ オーダーの高さが必要となる。
本発明ではこのスペーサとしてＡｕ膜７を用いており、
選択メッキにより形成するので厚さ数μｍ の膜でも容
易に特定領域のみに選択的に形成することができる。ま
た、Ｔｉ膜８／Ｐｔ膜９は、素子の加熱圧着時にＡｕＳ
ｎ１１膜中のＳｎがＡｕ７膜中に拡散しＡｕＳｎの融点
が上昇してしまうのを防ぐためのバリア層である。Next, the process shown in FIG. 1(d) will be explained in detail. Since the bump electrode has the role of a spacer as well as an electrode, it needs to have a height on the order of several μm. In the present invention, the Au film 7 is used as this spacer,
Since it is formed by selective plating, even a film several micrometers thick can be easily formed selectively only in specific areas. In addition, the Ti film 8/Pt film 9 is made of AuS when the device is bonded under heat and pressure.
This is a barrier layer for preventing Sn in the n11 film from diffusing into the Au7 film and increasing the melting point of AuSn.
【０００８】なお、上記実施例ではバリアメタルとして
Ｔｉ、Ｐｔを用いた場合を示したが、他の高融点金属で
も同様の効果が得られる。また、ＡｕＳｎ１１膜につい
てもＳｎなどの他の低融点金属を用いることができる。[0008] In the above embodiments, Ti and Pt were used as barrier metals, but similar effects can be obtained with other high melting point metals. Furthermore, other low melting point metals such as Sn can be used for the AuSn11 film.
【０００９】[0009]
【発明の効果】以上に説明したように、本発明によれば
、充分な高さを持った融点の低い半導体受光素子のバン
プ電極が再現性よく得られる。As described above, according to the present invention, a bump electrode of a semiconductor light-receiving element having a sufficient height and a low melting point can be obtained with good reproducibility.
【図１】本発明の一実施例の製造工程を示す断面模式図
である。FIG. 1 is a schematic cross-sectional view showing the manufacturing process of an embodiment of the present invention.
１ 化合物半導体 ２ 絶縁膜 ３，６，１０ フォトレジスト ４，８ Ｔｉ膜、 ５，７ Ａｕ膜 ９ Ｐｔ膜 １１ ＡｕＳｎ膜 1 Compound semiconductor 2 Insulating film 3, 6, 10 Photoresist 4,8 Ti film, 5,7 Au film 9 Pt film 11 AuSn film
Claims (1)
工程と、この厚膜上にＴｉ，Ｐｔなどの高融点金属を含
む多層金属膜を形成する工程と、この金属多層膜上にＡ
ｕＳｎ，Ｓｎなどの低融点金属膜を形成する工程とを有
することを特徴とする半導体受光素子のバンプ電極形成
方法。1. A step of forming a thick metal film as a spacer, a step of forming a multilayer metal film containing a high melting point metal such as Ti or Pt on the thick film, and a step of forming a multilayer metal film containing a high melting point metal such as Ti or Pt on the thick film.
1. A method for forming a bump electrode for a semiconductor light receiving element, comprising the step of forming a low melting point metal film such as uSn or Sn.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3058416A JP3049800B2 (en) | 1991-02-28 | 1991-02-28 | Method for forming bump electrode of semiconductor light receiving element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3058416A JP3049800B2 (en) | 1991-02-28 | 1991-02-28 | Method for forming bump electrode of semiconductor light receiving element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04273444A true JPH04273444A (en) | 1992-09-29 |
| JP3049800B2 JP3049800B2 (en) | 2000-06-05 |
Family
ID=13083780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3058416A Expired - Fee Related JP3049800B2 (en) | 1991-02-28 | 1991-02-28 | Method for forming bump electrode of semiconductor light receiving element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3049800B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013125768A (en) * | 2011-12-13 | 2013-06-24 | Japan Oclaro Inc | Solder bonding device and reception module |
| US9615464B2 (en) | 2013-03-21 | 2017-04-04 | Fujitsu Limited | Method of mounting semiconductor element, and semiconductor device |
-
1991
- 1991-02-28 JP JP3058416A patent/JP3049800B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013125768A (en) * | 2011-12-13 | 2013-06-24 | Japan Oclaro Inc | Solder bonding device and reception module |
| US9615464B2 (en) | 2013-03-21 | 2017-04-04 | Fujitsu Limited | Method of mounting semiconductor element, and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3049800B2 (en) | 2000-06-05 |
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